xref: /linux/drivers/gpio/gpio-grgpio.c (revision 25489a4f556414445d342951615178368ee45cde) 
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Driver for Aeroflex Gaisler GRGPIO General Purpose I/O cores.
4  *
5  * 2013 (c) Aeroflex Gaisler AB
6  *
7  * This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
8  * IP core library.
9  *
10  * Full documentation of the GRGPIO core can be found here:
11  * http://www.gaisler.com/products/grlib/grip.pdf
12  *
13  * See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
14  * information on open firmware properties.
15  *
16  * Contributors: Andreas Larsson <andreas@gaisler.com>
17  */
18 
19 #include <linux/bitops.h>
20 #include <linux/err.h>
21 #include <linux/gpio/driver.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/irq.h>
26 #include <linux/irqdomain.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/of.h>
30 #include <linux/platform_device.h>
31 #include <linux/slab.h>
32 #include <linux/spinlock.h>
33 #include <linux/string_choices.h>
34 
35 #define GRGPIO_MAX_NGPIO 32
36 
37 #define GRGPIO_DATA		0x00
38 #define GRGPIO_OUTPUT		0x04
39 #define GRGPIO_DIR		0x08
40 #define GRGPIO_IMASK		0x0c
41 #define GRGPIO_IPOL		0x10
42 #define GRGPIO_IEDGE		0x14
43 #define GRGPIO_BYPASS		0x18
44 #define GRGPIO_IMAP_BASE	0x20
45 
46 /* Structure for an irq of the core - called an underlying irq */
47 struct grgpio_uirq {
48 	u8 refcnt; /* Reference counter to manage requesting/freeing of uirq */
49 	u8 uirq; /* Underlying irq of the gpio driver */
50 };
51 
52 /*
53  * Structure for an irq of a gpio line handed out by this driver. The index is
54  * used to map to the corresponding underlying irq.
55  */
56 struct grgpio_lirq {
57 	s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
58 	u8 irq; /* irq for the gpio line */
59 };
60 
61 struct grgpio_priv {
62 	struct gpio_chip gc;
63 	void __iomem *regs;
64 	struct device *dev;
65 
66 	u32 imask; /* irq mask shadow register */
67 
68 	/*
69 	 * The grgpio core can have multiple "underlying" irqs. The gpio lines
70 	 * can be mapped to any one or none of these underlying irqs
71 	 * independently of each other. This driver sets up an irq domain and
72 	 * hands out separate irqs to each gpio line
73 	 */
74 	struct irq_domain *domain;
75 
76 	/*
77 	 * This array contains information on each underlying irq, each
78 	 * irq of the grgpio core itself.
79 	 */
80 	struct grgpio_uirq uirqs[GRGPIO_MAX_NGPIO];
81 
82 	/*
83 	 * This array contains information for each gpio line on the irqs
84 	 * obtains from this driver. An index value of -1 for a certain gpio
85 	 * line indicates that the line has no irq. Otherwise the index connects
86 	 * the irq to the underlying irq by pointing into the uirqs array.
87 	 */
88 	struct grgpio_lirq lirqs[GRGPIO_MAX_NGPIO];
89 };
90 
91 static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
92 			     int val)
93 {
94 	struct gpio_chip *gc = &priv->gc;
95 
96 	if (val)
97 		priv->imask |= BIT(offset);
98 	else
99 		priv->imask &= ~BIT(offset);
100 	gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
101 }
102 
103 static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
104 {
105 	struct grgpio_priv *priv = gpiochip_get_data(gc);
106 
107 	if (offset >= gc->ngpio)
108 		return -ENXIO;
109 
110 	if (priv->lirqs[offset].index < 0)
111 		return -ENXIO;
112 
113 	return irq_create_mapping(priv->domain, offset);
114 }
115 
116 /* -------------------- IRQ chip functions -------------------- */
117 
118 static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
119 {
120 	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
121 	unsigned long flags;
122 	u32 mask = BIT(d->hwirq);
123 	u32 ipol;
124 	u32 iedge;
125 	u32 pol;
126 	u32 edge;
127 
128 	switch (type) {
129 	case IRQ_TYPE_LEVEL_LOW:
130 		pol = 0;
131 		edge = 0;
132 		break;
133 	case IRQ_TYPE_LEVEL_HIGH:
134 		pol = mask;
135 		edge = 0;
136 		break;
137 	case IRQ_TYPE_EDGE_FALLING:
138 		pol = 0;
139 		edge = mask;
140 		break;
141 	case IRQ_TYPE_EDGE_RISING:
142 		pol = mask;
143 		edge = mask;
144 		break;
145 	default:
146 		return -EINVAL;
147 	}
148 
149 	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
150 
151 	ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
152 	iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
153 
154 	priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
155 	priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
156 
157 	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
158 
159 	return 0;
160 }
161 
162 static void grgpio_irq_mask(struct irq_data *d)
163 {
164 	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
165 	int offset = d->hwirq;
166 	unsigned long flags;
167 
168 	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
169 
170 	grgpio_set_imask(priv, offset, 0);
171 
172 	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
173 
174 	gpiochip_disable_irq(&priv->gc, d->hwirq);
175 }
176 
177 static void grgpio_irq_unmask(struct irq_data *d)
178 {
179 	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
180 	int offset = d->hwirq;
181 	unsigned long flags;
182 
183 	gpiochip_enable_irq(&priv->gc, d->hwirq);
184 	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
185 
186 	grgpio_set_imask(priv, offset, 1);
187 
188 	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
189 }
190 
191 static const struct irq_chip grgpio_irq_chip = {
192 	.name			= "grgpio",
193 	.irq_mask		= grgpio_irq_mask,
194 	.irq_unmask		= grgpio_irq_unmask,
195 	.irq_set_type		= grgpio_irq_set_type,
196 	.flags = IRQCHIP_IMMUTABLE,
197 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
198 };
199 
200 static irqreturn_t grgpio_irq_handler(int irq, void *dev)
201 {
202 	struct grgpio_priv *priv = dev;
203 	int ngpio = priv->gc.ngpio;
204 	unsigned long flags;
205 	int i;
206 	int match = 0;
207 
208 	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
209 
210 	/*
211 	 * For each gpio line, call its interrupt handler if it its underlying
212 	 * irq matches the current irq that is handled.
213 	 */
214 	for (i = 0; i < ngpio; i++) {
215 		struct grgpio_lirq *lirq = &priv->lirqs[i];
216 
217 		if (priv->imask & BIT(i) && lirq->index >= 0 &&
218 		    priv->uirqs[lirq->index].uirq == irq) {
219 			generic_handle_irq(lirq->irq);
220 			match = 1;
221 		}
222 	}
223 
224 	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
225 
226 	if (!match)
227 		dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
228 
229 	return IRQ_HANDLED;
230 }
231 
232 /*
233  * This function will be called as a consequence of the call to
234  * irq_create_mapping in grgpio_to_irq
235  */
236 static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
237 			  irq_hw_number_t hwirq)
238 {
239 	struct grgpio_priv *priv = d->host_data;
240 	struct grgpio_lirq *lirq;
241 	struct grgpio_uirq *uirq;
242 	unsigned long flags;
243 	int offset = hwirq;
244 	int ret = 0;
245 
246 	if (!priv)
247 		return -EINVAL;
248 
249 	lirq = &priv->lirqs[offset];
250 	if (lirq->index < 0)
251 		return -EINVAL;
252 
253 	dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
254 		irq, offset);
255 
256 	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
257 
258 	/* Request underlying irq if not already requested */
259 	lirq->irq = irq;
260 	uirq = &priv->uirqs[lirq->index];
261 	if (uirq->refcnt == 0) {
262 		raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
263 		ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
264 				  dev_name(priv->dev), priv);
265 		if (ret) {
266 			dev_err(priv->dev,
267 				"Could not request underlying irq %d\n",
268 				uirq->uirq);
269 			return ret;
270 		}
271 		raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
272 	}
273 	uirq->refcnt++;
274 
275 	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
276 
277 	/* Setup irq  */
278 	irq_set_chip_data(irq, priv);
279 	irq_set_chip_and_handler(irq, &grgpio_irq_chip,
280 				 handle_simple_irq);
281 	irq_set_noprobe(irq);
282 
283 	return ret;
284 }
285 
286 static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
287 {
288 	struct grgpio_priv *priv = d->host_data;
289 	int index;
290 	struct grgpio_lirq *lirq;
291 	struct grgpio_uirq *uirq;
292 	unsigned long flags;
293 	int ngpio = priv->gc.ngpio;
294 	int i;
295 
296 	irq_set_chip_and_handler(irq, NULL, NULL);
297 	irq_set_chip_data(irq, NULL);
298 
299 	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
300 
301 	/* Free underlying irq if last user unmapped */
302 	index = -1;
303 	for (i = 0; i < ngpio; i++) {
304 		lirq = &priv->lirqs[i];
305 		if (lirq->irq == irq) {
306 			grgpio_set_imask(priv, i, 0);
307 			lirq->irq = 0;
308 			index = lirq->index;
309 			break;
310 		}
311 	}
312 	WARN_ON(index < 0);
313 
314 	if (index >= 0) {
315 		uirq = &priv->uirqs[lirq->index];
316 		uirq->refcnt--;
317 		if (uirq->refcnt == 0) {
318 			raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
319 			free_irq(uirq->uirq, priv);
320 			return;
321 		}
322 	}
323 
324 	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
325 }
326 
327 static void grgpio_irq_domain_remove(void *data)
328 {
329 	struct irq_domain *domain = data;
330 
331 	irq_domain_remove(domain);
332 }
333 
334 static const struct irq_domain_ops grgpio_irq_domain_ops = {
335 	.map	= grgpio_irq_map,
336 	.unmap	= grgpio_irq_unmap,
337 };
338 
339 /* ------------------------------------------------------------ */
340 
341 static int grgpio_probe(struct platform_device *ofdev)
342 {
343 	struct device_node *np = ofdev->dev.of_node;
344 	struct device *dev = &ofdev->dev;
345 	void  __iomem *regs;
346 	struct gpio_chip *gc;
347 	struct grgpio_priv *priv;
348 	int err;
349 	u32 prop;
350 	s32 *irqmap;
351 	int size;
352 	int i;
353 
354 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
355 	if (!priv)
356 		return -ENOMEM;
357 
358 	regs = devm_platform_ioremap_resource(ofdev, 0);
359 	if (IS_ERR(regs))
360 		return PTR_ERR(regs);
361 
362 	gc = &priv->gc;
363 	err = bgpio_init(gc, dev, 4, regs + GRGPIO_DATA,
364 			 regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
365 			 BGPIOF_BIG_ENDIAN_BYTE_ORDER);
366 	if (err) {
367 		dev_err(dev, "bgpio_init() failed\n");
368 		return err;
369 	}
370 
371 	priv->regs = regs;
372 	priv->imask = gc->read_reg(regs + GRGPIO_IMASK);
373 	priv->dev = dev;
374 
375 	gc->owner = THIS_MODULE;
376 	gc->to_irq = grgpio_to_irq;
377 	gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
378 	if (!gc->label)
379 		return -ENOMEM;
380 
381 	gc->base = -1;
382 
383 	err = of_property_read_u32(np, "nbits", &prop);
384 	if (err || prop <= 0 || prop > GRGPIO_MAX_NGPIO) {
385 		gc->ngpio = GRGPIO_MAX_NGPIO;
386 		dev_dbg(dev, "No or invalid nbits property: assume %d\n",
387 			gc->ngpio);
388 	} else {
389 		gc->ngpio = prop;
390 	}
391 
392 	/*
393 	 * The irqmap contains the index values indicating which underlying irq,
394 	 * if anyone, is connected to that line
395 	 */
396 	irqmap = (s32 *)of_get_property(np, "irqmap", &size);
397 	if (irqmap) {
398 		if (size < gc->ngpio) {
399 			dev_err(dev,
400 				"irqmap shorter than ngpio (%d < %d)\n",
401 				size, gc->ngpio);
402 			return -EINVAL;
403 		}
404 
405 		priv->domain = irq_domain_create_linear(of_fwnode_handle(np), gc->ngpio,
406 						     &grgpio_irq_domain_ops,
407 						     priv);
408 		if (!priv->domain) {
409 			dev_err(dev, "Could not add irq domain\n");
410 			return -EINVAL;
411 		}
412 
413 		err = devm_add_action_or_reset(dev, grgpio_irq_domain_remove,
414 					       priv->domain);
415 		if (err)
416 			return err;
417 
418 		for (i = 0; i < gc->ngpio; i++) {
419 			struct grgpio_lirq *lirq;
420 			int ret;
421 
422 			lirq = &priv->lirqs[i];
423 			lirq->index = irqmap[i];
424 
425 			if (lirq->index < 0)
426 				continue;
427 
428 			ret = platform_get_irq(ofdev, lirq->index);
429 			if (ret <= 0) {
430 				/*
431 				 * Continue without irq functionality for that
432 				 * gpio line
433 				 */
434 				continue;
435 			}
436 			priv->uirqs[lirq->index].uirq = ret;
437 		}
438 	}
439 
440 	err = devm_gpiochip_add_data(dev, gc, priv);
441 	if (err) {
442 		dev_err(dev, "Could not add gpiochip\n");
443 		return err;
444 	}
445 
446 	dev_info(dev, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n",
447 		 priv->regs, gc->base, gc->ngpio, str_on_off(priv->domain));
448 
449 	return 0;
450 }
451 
452 static const struct of_device_id grgpio_match[] = {
453 	{.name = "GAISLER_GPIO"},
454 	{.name = "01_01a"},
455 	{},
456 };
457 
458 MODULE_DEVICE_TABLE(of, grgpio_match);
459 
460 static struct platform_driver grgpio_driver = {
461 	.driver = {
462 		.name = "grgpio",
463 		.of_match_table = grgpio_match,
464 	},
465 	.probe = grgpio_probe,
466 };
467 module_platform_driver(grgpio_driver);
468 
469 MODULE_AUTHOR("Aeroflex Gaisler AB.");
470 MODULE_DESCRIPTION("Driver for Aeroflex Gaisler GRGPIO");
471 MODULE_LICENSE("GPL");
472