1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel Granite Rapids-D vGPIO driver 4 * 5 * Copyright (c) 2024, Intel Corporation. 6 * 7 * Author: Aapo Vienamo <aapo.vienamo@linux.intel.com> 8 */ 9 10 #include <linux/array_size.h> 11 #include <linux/bitfield.h> 12 #include <linux/bitmap.h> 13 #include <linux/cleanup.h> 14 #include <linux/device.h> 15 #include <linux/err.h> 16 #include <linux/gfp_types.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/irq.h> 20 #include <linux/math.h> 21 #include <linux/module.h> 22 #include <linux/overflow.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm.h> 25 #include <linux/spinlock.h> 26 #include <linux/types.h> 27 28 #include <linux/gpio/driver.h> 29 30 #define GNR_NUM_PINS 128 31 #define GNR_PINS_PER_REG 32 32 #define GNR_NUM_REGS DIV_ROUND_UP(GNR_NUM_PINS, GNR_PINS_PER_REG) 33 34 #define GNR_CFG_PADBAR 0x00 35 #define GNR_CFG_LOCK_OFFSET 0x04 36 #define GNR_GPI_STATUS_OFFSET 0x14 37 #define GNR_GPI_ENABLE_OFFSET 0x24 38 39 #define GNR_CFG_DW_HOSTSW_MODE BIT(27) 40 #define GNR_CFG_DW_RX_MASK GENMASK(23, 22) 41 #define GNR_CFG_DW_INTSEL_MASK GENMASK(21, 14) 42 #define GNR_CFG_DW_RX_DISABLE FIELD_PREP(GNR_CFG_DW_RX_MASK, 2) 43 #define GNR_CFG_DW_RX_EDGE FIELD_PREP(GNR_CFG_DW_RX_MASK, 1) 44 #define GNR_CFG_DW_RX_LEVEL FIELD_PREP(GNR_CFG_DW_RX_MASK, 0) 45 #define GNR_CFG_DW_RXDIS BIT(4) 46 #define GNR_CFG_DW_TXDIS BIT(3) 47 #define GNR_CFG_DW_RXSTATE BIT(1) 48 #define GNR_CFG_DW_TXSTATE BIT(0) 49 50 /** 51 * struct gnr_gpio - Intel Granite Rapids-D vGPIO driver state 52 * @gc: GPIO controller interface 53 * @reg_base: base address of the GPIO registers 54 * @pad_base: base address of the vGPIO pad configuration registers 55 * @ro_bitmap: bitmap of read-only pins 56 * @lock: guard the registers 57 * @pad_backup: backup of the register state for suspend 58 */ 59 struct gnr_gpio { 60 struct gpio_chip gc; 61 void __iomem *reg_base; 62 void __iomem *pad_base; 63 DECLARE_BITMAP(ro_bitmap, GNR_NUM_PINS); 64 raw_spinlock_t lock; 65 u32 pad_backup[]; 66 }; 67 68 static void __iomem *gnr_gpio_get_padcfg_addr(const struct gnr_gpio *priv, 69 unsigned int gpio) 70 { 71 return priv->pad_base + gpio * sizeof(u32); 72 } 73 74 static int gnr_gpio_configure_line(struct gpio_chip *gc, unsigned int gpio, 75 u32 clear_mask, u32 set_mask) 76 { 77 struct gnr_gpio *priv = gpiochip_get_data(gc); 78 void __iomem *addr = gnr_gpio_get_padcfg_addr(priv, gpio); 79 u32 dw; 80 81 if (test_bit(gpio, priv->ro_bitmap)) 82 return -EACCES; 83 84 guard(raw_spinlock_irqsave)(&priv->lock); 85 86 dw = readl(addr); 87 dw &= ~clear_mask; 88 dw |= set_mask; 89 writel(dw, addr); 90 91 return 0; 92 } 93 94 static int gnr_gpio_request(struct gpio_chip *gc, unsigned int gpio) 95 { 96 struct gnr_gpio *priv = gpiochip_get_data(gc); 97 u32 dw; 98 99 dw = readl(gnr_gpio_get_padcfg_addr(priv, gpio)); 100 if (!(dw & GNR_CFG_DW_HOSTSW_MODE)) { 101 dev_warn(gc->parent, "GPIO %u is not owned by host", gpio); 102 return -EBUSY; 103 } 104 105 return 0; 106 } 107 108 static int gnr_gpio_get(struct gpio_chip *gc, unsigned int gpio) 109 { 110 const struct gnr_gpio *priv = gpiochip_get_data(gc); 111 u32 dw; 112 113 dw = readl(gnr_gpio_get_padcfg_addr(priv, gpio)); 114 115 return !!(dw & GNR_CFG_DW_RXSTATE); 116 } 117 118 static int gnr_gpio_set(struct gpio_chip *gc, unsigned int gpio, int value) 119 { 120 u32 clear = 0; 121 u32 set = 0; 122 123 if (value) 124 set = GNR_CFG_DW_TXSTATE; 125 else 126 clear = GNR_CFG_DW_TXSTATE; 127 128 return gnr_gpio_configure_line(gc, gpio, clear, set); 129 } 130 131 static int gnr_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio) 132 { 133 struct gnr_gpio *priv = gpiochip_get_data(gc); 134 u32 dw; 135 136 dw = readl(gnr_gpio_get_padcfg_addr(priv, gpio)); 137 138 if (dw & GNR_CFG_DW_TXDIS) 139 return GPIO_LINE_DIRECTION_IN; 140 141 return GPIO_LINE_DIRECTION_OUT; 142 } 143 144 static int gnr_gpio_direction_input(struct gpio_chip *gc, unsigned int gpio) 145 { 146 return gnr_gpio_configure_line(gc, gpio, GNR_CFG_DW_RXDIS, 0); 147 } 148 149 static int gnr_gpio_direction_output(struct gpio_chip *gc, unsigned int gpio, int value) 150 { 151 u32 clear = GNR_CFG_DW_TXDIS; 152 u32 set = value ? GNR_CFG_DW_TXSTATE : 0; 153 154 return gnr_gpio_configure_line(gc, gpio, clear, set); 155 } 156 157 static const struct gpio_chip gnr_gpio_chip = { 158 .owner = THIS_MODULE, 159 .request = gnr_gpio_request, 160 .get = gnr_gpio_get, 161 .set = gnr_gpio_set, 162 .get_direction = gnr_gpio_get_direction, 163 .direction_input = gnr_gpio_direction_input, 164 .direction_output = gnr_gpio_direction_output, 165 }; 166 167 static void __iomem *gnr_gpio_get_reg_addr(const struct gnr_gpio *priv, 168 unsigned int base, 169 unsigned int gpio) 170 { 171 return priv->reg_base + base + gpio * sizeof(u32); 172 } 173 174 static void gnr_gpio_irq_ack(struct irq_data *d) 175 { 176 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 177 struct gnr_gpio *priv = gpiochip_get_data(gc); 178 irq_hw_number_t gpio = irqd_to_hwirq(d); 179 unsigned int reg_idx = gpio / GNR_PINS_PER_REG; 180 unsigned int bit_idx = gpio % GNR_PINS_PER_REG; 181 void __iomem *addr = gnr_gpio_get_reg_addr(priv, GNR_GPI_STATUS_OFFSET, reg_idx); 182 u32 reg; 183 184 guard(raw_spinlock_irqsave)(&priv->lock); 185 186 reg = readl(addr); 187 reg |= BIT(bit_idx); 188 writel(reg, addr); 189 } 190 191 static void gnr_gpio_irq_mask_unmask(struct gpio_chip *gc, unsigned long gpio, bool mask) 192 { 193 struct gnr_gpio *priv = gpiochip_get_data(gc); 194 unsigned int reg_idx = gpio / GNR_PINS_PER_REG; 195 unsigned int bit_idx = gpio % GNR_PINS_PER_REG; 196 void __iomem *addr = gnr_gpio_get_reg_addr(priv, GNR_GPI_ENABLE_OFFSET, reg_idx); 197 u32 reg; 198 199 guard(raw_spinlock_irqsave)(&priv->lock); 200 201 reg = readl(addr); 202 if (mask) 203 reg &= ~BIT(bit_idx); 204 else 205 reg |= BIT(bit_idx); 206 writel(reg, addr); 207 } 208 209 static void gnr_gpio_irq_mask(struct irq_data *d) 210 { 211 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 212 irq_hw_number_t hwirq = irqd_to_hwirq(d); 213 214 gnr_gpio_irq_mask_unmask(gc, hwirq, true); 215 gpiochip_disable_irq(gc, hwirq); 216 } 217 218 static void gnr_gpio_irq_unmask(struct irq_data *d) 219 { 220 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 221 irq_hw_number_t hwirq = irqd_to_hwirq(d); 222 223 gpiochip_enable_irq(gc, hwirq); 224 gnr_gpio_irq_mask_unmask(gc, hwirq, false); 225 } 226 227 static int gnr_gpio_irq_set_type(struct irq_data *d, unsigned int type) 228 { 229 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 230 struct gnr_gpio *priv = gpiochip_get_data(gc); 231 irq_hw_number_t hwirq = irqd_to_hwirq(d); 232 u32 reg; 233 u32 set; 234 235 /* Allow interrupts only if Interrupt Select field is non-zero */ 236 reg = readl(gnr_gpio_get_padcfg_addr(priv, hwirq)); 237 if (!(reg & GNR_CFG_DW_INTSEL_MASK)) { 238 dev_dbg(gc->parent, "GPIO %lu cannot be used as IRQ", hwirq); 239 return -EPERM; 240 } 241 242 /* Falling edge and level low triggers not supported by the GPIO controller */ 243 switch (type) { 244 case IRQ_TYPE_NONE: 245 set = GNR_CFG_DW_RX_DISABLE; 246 break; 247 case IRQ_TYPE_EDGE_RISING: 248 set = GNR_CFG_DW_RX_EDGE; 249 irq_set_handler_locked(d, handle_edge_irq); 250 break; 251 case IRQ_TYPE_LEVEL_HIGH: 252 set = GNR_CFG_DW_RX_LEVEL; 253 irq_set_handler_locked(d, handle_level_irq); 254 break; 255 default: 256 return -EINVAL; 257 } 258 259 return gnr_gpio_configure_line(gc, hwirq, GNR_CFG_DW_RX_MASK, set); 260 } 261 262 static const struct irq_chip gnr_gpio_irq_chip = { 263 .name = "gpio-graniterapids", 264 .irq_ack = gnr_gpio_irq_ack, 265 .irq_mask = gnr_gpio_irq_mask, 266 .irq_unmask = gnr_gpio_irq_unmask, 267 .irq_set_type = gnr_gpio_irq_set_type, 268 .flags = IRQCHIP_IMMUTABLE, 269 GPIOCHIP_IRQ_RESOURCE_HELPERS, 270 }; 271 272 static void gnr_gpio_init_pin_ro_bits(struct device *dev, 273 const void __iomem *cfg_lock_base, 274 unsigned long *ro_bitmap) 275 { 276 u32 tmp[GNR_NUM_REGS]; 277 278 memcpy_fromio(tmp, cfg_lock_base, sizeof(tmp)); 279 bitmap_from_arr32(ro_bitmap, tmp, GNR_NUM_PINS); 280 } 281 282 static irqreturn_t gnr_gpio_irq(int irq, void *data) 283 { 284 struct gnr_gpio *priv = data; 285 unsigned int handled = 0; 286 287 for (unsigned int i = 0; i < GNR_NUM_REGS; i++) { 288 const void __iomem *reg = priv->reg_base + i * sizeof(u32); 289 unsigned long pending; 290 unsigned long enabled; 291 unsigned int bit_idx; 292 293 scoped_guard(raw_spinlock, &priv->lock) { 294 pending = readl(reg + GNR_GPI_STATUS_OFFSET); 295 enabled = readl(reg + GNR_GPI_ENABLE_OFFSET); 296 } 297 298 /* Only enabled interrupts */ 299 pending &= enabled; 300 301 for_each_set_bit(bit_idx, &pending, GNR_PINS_PER_REG) { 302 unsigned int hwirq = i * GNR_PINS_PER_REG + bit_idx; 303 304 generic_handle_domain_irq(priv->gc.irq.domain, hwirq); 305 } 306 307 handled += pending ? 1 : 0; 308 309 } 310 return IRQ_RETVAL(handled); 311 } 312 313 static int gnr_gpio_probe(struct platform_device *pdev) 314 { 315 size_t num_backup_pins = IS_ENABLED(CONFIG_PM_SLEEP) ? GNR_NUM_PINS : 0; 316 struct device *dev = &pdev->dev; 317 struct gpio_irq_chip *girq; 318 struct gnr_gpio *priv; 319 void __iomem *regs; 320 int irq, ret; 321 u32 offset; 322 323 priv = devm_kzalloc(dev, struct_size(priv, pad_backup, num_backup_pins), GFP_KERNEL); 324 if (!priv) 325 return -ENOMEM; 326 327 raw_spin_lock_init(&priv->lock); 328 329 regs = devm_platform_ioremap_resource(pdev, 0); 330 if (IS_ERR(regs)) 331 return PTR_ERR(regs); 332 333 priv->reg_base = regs; 334 offset = readl(priv->reg_base + GNR_CFG_PADBAR); 335 priv->pad_base = priv->reg_base + offset; 336 337 irq = platform_get_irq(pdev, 0); 338 if (irq < 0) 339 return irq; 340 341 ret = devm_request_irq(dev, irq, gnr_gpio_irq, IRQF_SHARED | IRQF_NO_THREAD, 342 dev_name(dev), priv); 343 if (ret) 344 return dev_err_probe(dev, ret, "failed to request interrupt\n"); 345 346 gnr_gpio_init_pin_ro_bits(dev, priv->reg_base + GNR_CFG_LOCK_OFFSET, 347 priv->ro_bitmap); 348 349 priv->gc = gnr_gpio_chip; 350 priv->gc.label = dev_name(dev); 351 priv->gc.parent = dev; 352 priv->gc.ngpio = GNR_NUM_PINS; 353 priv->gc.base = -1; 354 355 girq = &priv->gc.irq; 356 gpio_irq_chip_set_chip(girq, &gnr_gpio_irq_chip); 357 girq->parent_handler = NULL; 358 girq->num_parents = 0; 359 girq->parents = NULL; 360 girq->default_type = IRQ_TYPE_NONE; 361 girq->handler = handle_bad_irq; 362 363 platform_set_drvdata(pdev, priv); 364 365 return devm_gpiochip_add_data(dev, &priv->gc, priv); 366 } 367 368 static int gnr_gpio_suspend(struct device *dev) 369 { 370 struct gnr_gpio *priv = dev_get_drvdata(dev); 371 unsigned int i; 372 373 guard(raw_spinlock_irqsave)(&priv->lock); 374 375 for_each_clear_bit(i, priv->ro_bitmap, priv->gc.ngpio) 376 priv->pad_backup[i] = readl(gnr_gpio_get_padcfg_addr(priv, i)); 377 378 return 0; 379 } 380 381 static int gnr_gpio_resume(struct device *dev) 382 { 383 struct gnr_gpio *priv = dev_get_drvdata(dev); 384 unsigned int i; 385 386 guard(raw_spinlock_irqsave)(&priv->lock); 387 388 for_each_clear_bit(i, priv->ro_bitmap, priv->gc.ngpio) 389 writel(priv->pad_backup[i], gnr_gpio_get_padcfg_addr(priv, i)); 390 391 return 0; 392 } 393 394 static DEFINE_SIMPLE_DEV_PM_OPS(gnr_gpio_pm_ops, gnr_gpio_suspend, gnr_gpio_resume); 395 396 static const struct acpi_device_id gnr_gpio_acpi_match[] = { 397 { "INTC1109" }, 398 {} 399 }; 400 MODULE_DEVICE_TABLE(acpi, gnr_gpio_acpi_match); 401 402 static struct platform_driver gnr_gpio_driver = { 403 .driver = { 404 .name = "gpio-graniterapids", 405 .pm = pm_sleep_ptr(&gnr_gpio_pm_ops), 406 .acpi_match_table = gnr_gpio_acpi_match, 407 }, 408 .probe = gnr_gpio_probe, 409 }; 410 module_platform_driver(gnr_gpio_driver); 411 412 MODULE_LICENSE("GPL"); 413 MODULE_AUTHOR("Aapo Vienamo <aapo.vienamo@linux.intel.com>"); 414 MODULE_DESCRIPTION("Intel Granite Rapids-D vGPIO driver"); 415