1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for Exar XR17V35X chip 4 * 5 * Copyright (C) 2015 Sudip Mukherjee <sudip.mukherjee@codethink.co.uk> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/device.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/idr.h> 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 19 #define EXAR_OFFSET_MPIOLVL_LO 0x90 20 #define EXAR_OFFSET_MPIOSEL_LO 0x93 21 #define EXAR_OFFSET_MPIOLVL_HI 0x96 22 #define EXAR_OFFSET_MPIOSEL_HI 0x99 23 24 /* 25 * The Device Configuration and UART Configuration Registers 26 * for each UART channel take 1KB of memory address space. 27 */ 28 #define EXAR_UART_CHANNEL_SIZE 0x400 29 30 #define DRIVER_NAME "gpio_exar" 31 32 static DEFINE_IDA(ida_index); 33 34 struct exar_gpio_chip { 35 struct gpio_chip gpio_chip; 36 struct regmap *regmap; 37 int index; 38 char name[20]; 39 unsigned int first_pin; 40 /* 41 * The offset to the cascaded device's (if existing) 42 * Device Configuration Registers. 43 */ 44 unsigned int cascaded_offset; 45 }; 46 47 static unsigned int 48 exar_offset_to_sel_addr(struct exar_gpio_chip *exar_gpio, unsigned int offset) 49 { 50 unsigned int pin = exar_gpio->first_pin + (offset % 16); 51 unsigned int cascaded = offset / 16; 52 unsigned int addr = pin / 8 ? EXAR_OFFSET_MPIOSEL_HI : EXAR_OFFSET_MPIOSEL_LO; 53 54 return addr + (cascaded ? exar_gpio->cascaded_offset : 0); 55 } 56 57 static unsigned int 58 exar_offset_to_lvl_addr(struct exar_gpio_chip *exar_gpio, unsigned int offset) 59 { 60 unsigned int pin = exar_gpio->first_pin + (offset % 16); 61 unsigned int cascaded = offset / 16; 62 unsigned int addr = pin / 8 ? EXAR_OFFSET_MPIOLVL_HI : EXAR_OFFSET_MPIOLVL_LO; 63 64 return addr + (cascaded ? exar_gpio->cascaded_offset : 0); 65 } 66 67 static unsigned int 68 exar_offset_to_bit(struct exar_gpio_chip *exar_gpio, unsigned int offset) 69 { 70 unsigned int pin = exar_gpio->first_pin + (offset % 16); 71 72 return pin % 8; 73 } 74 75 static int exar_get_direction(struct gpio_chip *chip, unsigned int offset) 76 { 77 struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip); 78 unsigned int addr = exar_offset_to_sel_addr(exar_gpio, offset); 79 unsigned int bit = exar_offset_to_bit(exar_gpio, offset); 80 81 if (regmap_test_bits(exar_gpio->regmap, addr, BIT(bit))) 82 return GPIO_LINE_DIRECTION_IN; 83 84 return GPIO_LINE_DIRECTION_OUT; 85 } 86 87 static int exar_get_value(struct gpio_chip *chip, unsigned int offset) 88 { 89 struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip); 90 unsigned int addr = exar_offset_to_lvl_addr(exar_gpio, offset); 91 unsigned int bit = exar_offset_to_bit(exar_gpio, offset); 92 93 return !!(regmap_test_bits(exar_gpio->regmap, addr, BIT(bit))); 94 } 95 96 static void exar_set_value(struct gpio_chip *chip, unsigned int offset, 97 int value) 98 { 99 struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip); 100 unsigned int addr = exar_offset_to_lvl_addr(exar_gpio, offset); 101 unsigned int bit = exar_offset_to_bit(exar_gpio, offset); 102 unsigned int bit_value = value ? BIT(bit) : 0; 103 104 /* 105 * regmap_write_bits() forces value to be written when an external 106 * pull up/down might otherwise indicate value was already set. 107 */ 108 regmap_write_bits(exar_gpio->regmap, addr, BIT(bit), bit_value); 109 } 110 111 static int exar_direction_output(struct gpio_chip *chip, unsigned int offset, 112 int value) 113 { 114 struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip); 115 unsigned int addr = exar_offset_to_sel_addr(exar_gpio, offset); 116 unsigned int bit = exar_offset_to_bit(exar_gpio, offset); 117 118 exar_set_value(chip, offset, value); 119 regmap_clear_bits(exar_gpio->regmap, addr, BIT(bit)); 120 121 return 0; 122 } 123 124 static int exar_direction_input(struct gpio_chip *chip, unsigned int offset) 125 { 126 struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip); 127 unsigned int addr = exar_offset_to_sel_addr(exar_gpio, offset); 128 unsigned int bit = exar_offset_to_bit(exar_gpio, offset); 129 130 regmap_set_bits(exar_gpio->regmap, addr, BIT(bit)); 131 132 return 0; 133 } 134 135 static void exar_devm_ida_free(void *data) 136 { 137 struct exar_gpio_chip *exar_gpio = data; 138 139 ida_free(&ida_index, exar_gpio->index); 140 } 141 142 static const struct regmap_config exar_regmap_config = { 143 .name = "exar-gpio", 144 .reg_bits = 16, 145 .val_bits = 8, 146 .io_port = true, 147 }; 148 149 static int gpio_exar_probe(struct platform_device *pdev) 150 { 151 struct device *dev = &pdev->dev; 152 struct pci_dev *pcidev = to_pci_dev(dev->parent); 153 struct exar_gpio_chip *exar_gpio; 154 u32 first_pin, ngpios; 155 void __iomem *p; 156 int index, ret; 157 158 /* 159 * The UART driver must have mapped region 0 prior to registering this 160 * device - use it. 161 */ 162 p = pcim_iomap_table(pcidev)[0]; 163 if (!p) 164 return -ENOMEM; 165 166 ret = device_property_read_u32(dev, "exar,first-pin", &first_pin); 167 if (ret) 168 return ret; 169 170 ret = device_property_read_u32(dev, "ngpios", &ngpios); 171 if (ret) 172 return ret; 173 174 exar_gpio = devm_kzalloc(dev, sizeof(*exar_gpio), GFP_KERNEL); 175 if (!exar_gpio) 176 return -ENOMEM; 177 178 /* 179 * If cascaded, secondary xr17v354 or xr17v358 have the same amount 180 * of MPIOs as their primaries and the last 4 bits of the primary's 181 * PCI Device ID is the number of its UART channels. 182 */ 183 if (pcidev->device & GENMASK(15, 12)) { 184 ngpios += ngpios; 185 exar_gpio->cascaded_offset = (pcidev->device & GENMASK(3, 0)) * 186 EXAR_UART_CHANNEL_SIZE; 187 } 188 189 /* 190 * We don't need to check the return values of mmio regmap operations (unless 191 * the regmap has a clock attached which is not the case here). 192 */ 193 exar_gpio->regmap = devm_regmap_init_mmio(dev, p, &exar_regmap_config); 194 if (IS_ERR(exar_gpio->regmap)) 195 return PTR_ERR(exar_gpio->regmap); 196 197 index = ida_alloc(&ida_index, GFP_KERNEL); 198 if (index < 0) 199 return index; 200 201 ret = devm_add_action_or_reset(dev, exar_devm_ida_free, exar_gpio); 202 if (ret) 203 return ret; 204 205 sprintf(exar_gpio->name, "exar_gpio%d", index); 206 exar_gpio->gpio_chip.label = exar_gpio->name; 207 exar_gpio->gpio_chip.parent = dev; 208 exar_gpio->gpio_chip.direction_output = exar_direction_output; 209 exar_gpio->gpio_chip.direction_input = exar_direction_input; 210 exar_gpio->gpio_chip.get_direction = exar_get_direction; 211 exar_gpio->gpio_chip.get = exar_get_value; 212 exar_gpio->gpio_chip.set = exar_set_value; 213 exar_gpio->gpio_chip.base = -1; 214 exar_gpio->gpio_chip.ngpio = ngpios; 215 exar_gpio->index = index; 216 exar_gpio->first_pin = first_pin; 217 218 ret = devm_gpiochip_add_data(dev, &exar_gpio->gpio_chip, exar_gpio); 219 if (ret) 220 return ret; 221 222 return 0; 223 } 224 225 static struct platform_driver gpio_exar_driver = { 226 .probe = gpio_exar_probe, 227 .driver = { 228 .name = DRIVER_NAME, 229 }, 230 }; 231 232 module_platform_driver(gpio_exar_driver); 233 234 MODULE_ALIAS("platform:" DRIVER_NAME); 235 MODULE_DESCRIPTION("Exar GPIO driver"); 236 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>"); 237 MODULE_LICENSE("GPL"); 238