1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Spreadtrum Communications Inc. 4 * Copyright (C) 2018 Linaro Ltd. 5 */ 6 7 #include <linux/bitops.h> 8 #include <linux/gpio/driver.h> 9 #include <linux/interrupt.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <linux/spinlock.h> 15 16 /* EIC registers definition */ 17 #define SPRD_EIC_DBNC_DATA 0x0 18 #define SPRD_EIC_DBNC_DMSK 0x4 19 #define SPRD_EIC_DBNC_IEV 0x14 20 #define SPRD_EIC_DBNC_IE 0x18 21 #define SPRD_EIC_DBNC_RIS 0x1c 22 #define SPRD_EIC_DBNC_MIS 0x20 23 #define SPRD_EIC_DBNC_IC 0x24 24 #define SPRD_EIC_DBNC_TRIG 0x28 25 #define SPRD_EIC_DBNC_CTRL0 0x40 26 27 #define SPRD_EIC_LATCH_INTEN 0x0 28 #define SPRD_EIC_LATCH_INTRAW 0x4 29 #define SPRD_EIC_LATCH_INTMSK 0x8 30 #define SPRD_EIC_LATCH_INTCLR 0xc 31 #define SPRD_EIC_LATCH_INTPOL 0x10 32 #define SPRD_EIC_LATCH_INTMODE 0x14 33 34 #define SPRD_EIC_ASYNC_INTIE 0x0 35 #define SPRD_EIC_ASYNC_INTRAW 0x4 36 #define SPRD_EIC_ASYNC_INTMSK 0x8 37 #define SPRD_EIC_ASYNC_INTCLR 0xc 38 #define SPRD_EIC_ASYNC_INTMODE 0x10 39 #define SPRD_EIC_ASYNC_INTBOTH 0x14 40 #define SPRD_EIC_ASYNC_INTPOL 0x18 41 #define SPRD_EIC_ASYNC_DATA 0x1c 42 43 #define SPRD_EIC_SYNC_INTIE 0x0 44 #define SPRD_EIC_SYNC_INTRAW 0x4 45 #define SPRD_EIC_SYNC_INTMSK 0x8 46 #define SPRD_EIC_SYNC_INTCLR 0xc 47 #define SPRD_EIC_SYNC_INTMODE 0x10 48 #define SPRD_EIC_SYNC_INTBOTH 0x14 49 #define SPRD_EIC_SYNC_INTPOL 0x18 50 #define SPRD_EIC_SYNC_DATA 0x1c 51 52 /* 53 * The digital-chip EIC controller can support maximum 3 banks, and each bank 54 * contains 8 EICs. 55 */ 56 #define SPRD_EIC_MAX_BANK 3 57 #define SPRD_EIC_PER_BANK_NR 8 58 #define SPRD_EIC_DATA_MASK GENMASK(7, 0) 59 #define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1)) 60 #define SPRD_EIC_DBNC_MASK GENMASK(11, 0) 61 62 /* 63 * The Spreadtrum EIC (external interrupt controller) can be used only in 64 * input mode to generate interrupts if detecting input signals. 65 * 66 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules: 67 * debounce EIC, latch EIC, async EIC and sync EIC, 68 * 69 * The debounce EIC is used to capture the input signals' stable status 70 * (millisecond resolution) and a single-trigger mechanism is introduced 71 * into this sub-module to enhance the input event detection reliability. 72 * The debounce range is from 1ms to 4s with a step size of 1ms. 73 * 74 * The latch EIC is used to latch some special power down signals and 75 * generate interrupts, since the latch EIC does not depend on the APB clock 76 * to capture signals. 77 * 78 * The async EIC uses a 32k clock to capture the short signals (microsecond 79 * resolution) to generate interrupts by level or edge trigger. 80 * 81 * The EIC-sync is similar with GPIO's input function, which is a synchronized 82 * signal input register. 83 */ 84 enum sprd_eic_type { 85 SPRD_EIC_DEBOUNCE, 86 SPRD_EIC_LATCH, 87 SPRD_EIC_ASYNC, 88 SPRD_EIC_SYNC, 89 SPRD_EIC_MAX, 90 }; 91 92 struct sprd_eic { 93 struct gpio_chip chip; 94 struct irq_chip intc; 95 void __iomem *base[SPRD_EIC_MAX_BANK]; 96 enum sprd_eic_type type; 97 spinlock_t lock; 98 int irq; 99 }; 100 101 struct sprd_eic_variant_data { 102 enum sprd_eic_type type; 103 u32 num_eics; 104 }; 105 106 static const char *sprd_eic_label_name[SPRD_EIC_MAX] = { 107 "eic-debounce", "eic-latch", "eic-async", 108 "eic-sync", 109 }; 110 111 static const struct sprd_eic_variant_data sc9860_eic_dbnc_data = { 112 .type = SPRD_EIC_DEBOUNCE, 113 .num_eics = 8, 114 }; 115 116 static const struct sprd_eic_variant_data sc9860_eic_latch_data = { 117 .type = SPRD_EIC_LATCH, 118 .num_eics = 8, 119 }; 120 121 static const struct sprd_eic_variant_data sc9860_eic_async_data = { 122 .type = SPRD_EIC_ASYNC, 123 .num_eics = 8, 124 }; 125 126 static const struct sprd_eic_variant_data sc9860_eic_sync_data = { 127 .type = SPRD_EIC_SYNC, 128 .num_eics = 8, 129 }; 130 131 static inline void __iomem *sprd_eic_offset_base(struct sprd_eic *sprd_eic, 132 unsigned int bank) 133 { 134 if (bank >= SPRD_EIC_MAX_BANK) 135 return NULL; 136 137 return sprd_eic->base[bank]; 138 } 139 140 static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset, 141 u16 reg, unsigned int val) 142 { 143 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 144 void __iomem *base = 145 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); 146 unsigned long flags; 147 u32 tmp; 148 149 spin_lock_irqsave(&sprd_eic->lock, flags); 150 tmp = readl_relaxed(base + reg); 151 152 if (val) 153 tmp |= BIT(SPRD_EIC_BIT(offset)); 154 else 155 tmp &= ~BIT(SPRD_EIC_BIT(offset)); 156 157 writel_relaxed(tmp, base + reg); 158 spin_unlock_irqrestore(&sprd_eic->lock, flags); 159 } 160 161 static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg) 162 { 163 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 164 void __iomem *base = 165 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); 166 167 return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset))); 168 } 169 170 static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset) 171 { 172 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1); 173 return 0; 174 } 175 176 static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset) 177 { 178 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0); 179 } 180 181 static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset) 182 { 183 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 184 185 switch (sprd_eic->type) { 186 case SPRD_EIC_DEBOUNCE: 187 return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA); 188 case SPRD_EIC_ASYNC: 189 return sprd_eic_read(chip, offset, SPRD_EIC_ASYNC_DATA); 190 case SPRD_EIC_SYNC: 191 return sprd_eic_read(chip, offset, SPRD_EIC_SYNC_DATA); 192 default: 193 return -ENOTSUPP; 194 } 195 } 196 197 static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset) 198 { 199 /* EICs are always input, nothing need to do here. */ 200 return 0; 201 } 202 203 static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value) 204 { 205 /* EICs are always input, nothing need to do here. */ 206 } 207 208 static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset, 209 unsigned int debounce) 210 { 211 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 212 void __iomem *base = 213 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); 214 u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4; 215 u32 value = readl_relaxed(base + reg) & ~SPRD_EIC_DBNC_MASK; 216 217 value |= (debounce / 1000) & SPRD_EIC_DBNC_MASK; 218 writel_relaxed(value, base + reg); 219 220 return 0; 221 } 222 223 static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset, 224 unsigned long config) 225 { 226 unsigned long param = pinconf_to_config_param(config); 227 u32 arg = pinconf_to_config_argument(config); 228 229 if (param == PIN_CONFIG_INPUT_DEBOUNCE) 230 return sprd_eic_set_debounce(chip, offset, arg); 231 232 return -ENOTSUPP; 233 } 234 235 static void sprd_eic_irq_mask(struct irq_data *data) 236 { 237 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 238 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 239 u32 offset = irqd_to_hwirq(data); 240 241 switch (sprd_eic->type) { 242 case SPRD_EIC_DEBOUNCE: 243 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0); 244 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0); 245 break; 246 case SPRD_EIC_LATCH: 247 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0); 248 break; 249 case SPRD_EIC_ASYNC: 250 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0); 251 break; 252 case SPRD_EIC_SYNC: 253 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0); 254 break; 255 default: 256 dev_err(chip->parent, "Unsupported EIC type.\n"); 257 } 258 } 259 260 static void sprd_eic_irq_unmask(struct irq_data *data) 261 { 262 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 263 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 264 u32 offset = irqd_to_hwirq(data); 265 266 switch (sprd_eic->type) { 267 case SPRD_EIC_DEBOUNCE: 268 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1); 269 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1); 270 break; 271 case SPRD_EIC_LATCH: 272 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1); 273 break; 274 case SPRD_EIC_ASYNC: 275 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1); 276 break; 277 case SPRD_EIC_SYNC: 278 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1); 279 break; 280 default: 281 dev_err(chip->parent, "Unsupported EIC type.\n"); 282 } 283 } 284 285 static void sprd_eic_irq_ack(struct irq_data *data) 286 { 287 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 288 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 289 u32 offset = irqd_to_hwirq(data); 290 291 switch (sprd_eic->type) { 292 case SPRD_EIC_DEBOUNCE: 293 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1); 294 break; 295 case SPRD_EIC_LATCH: 296 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1); 297 break; 298 case SPRD_EIC_ASYNC: 299 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); 300 break; 301 case SPRD_EIC_SYNC: 302 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); 303 break; 304 default: 305 dev_err(chip->parent, "Unsupported EIC type.\n"); 306 } 307 } 308 309 static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type) 310 { 311 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 312 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 313 u32 offset = irqd_to_hwirq(data); 314 int state; 315 316 switch (sprd_eic->type) { 317 case SPRD_EIC_DEBOUNCE: 318 switch (flow_type) { 319 case IRQ_TYPE_LEVEL_HIGH: 320 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1); 321 break; 322 case IRQ_TYPE_LEVEL_LOW: 323 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0); 324 break; 325 case IRQ_TYPE_EDGE_RISING: 326 case IRQ_TYPE_EDGE_FALLING: 327 case IRQ_TYPE_EDGE_BOTH: 328 state = sprd_eic_get(chip, offset); 329 if (state) 330 sprd_eic_update(chip, offset, 331 SPRD_EIC_DBNC_IEV, 0); 332 else 333 sprd_eic_update(chip, offset, 334 SPRD_EIC_DBNC_IEV, 1); 335 break; 336 default: 337 return -ENOTSUPP; 338 } 339 340 irq_set_handler_locked(data, handle_level_irq); 341 break; 342 case SPRD_EIC_LATCH: 343 switch (flow_type) { 344 case IRQ_TYPE_LEVEL_HIGH: 345 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0); 346 break; 347 case IRQ_TYPE_LEVEL_LOW: 348 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1); 349 break; 350 case IRQ_TYPE_EDGE_RISING: 351 case IRQ_TYPE_EDGE_FALLING: 352 case IRQ_TYPE_EDGE_BOTH: 353 state = sprd_eic_get(chip, offset); 354 if (state) 355 sprd_eic_update(chip, offset, 356 SPRD_EIC_LATCH_INTPOL, 0); 357 else 358 sprd_eic_update(chip, offset, 359 SPRD_EIC_LATCH_INTPOL, 1); 360 break; 361 default: 362 return -ENOTSUPP; 363 } 364 365 irq_set_handler_locked(data, handle_level_irq); 366 break; 367 case SPRD_EIC_ASYNC: 368 switch (flow_type) { 369 case IRQ_TYPE_EDGE_RISING: 370 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); 371 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); 372 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1); 373 irq_set_handler_locked(data, handle_edge_irq); 374 break; 375 case IRQ_TYPE_EDGE_FALLING: 376 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); 377 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); 378 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0); 379 irq_set_handler_locked(data, handle_edge_irq); 380 break; 381 case IRQ_TYPE_EDGE_BOTH: 382 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); 383 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1); 384 irq_set_handler_locked(data, handle_edge_irq); 385 break; 386 case IRQ_TYPE_LEVEL_HIGH: 387 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); 388 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1); 389 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1); 390 irq_set_handler_locked(data, handle_level_irq); 391 break; 392 case IRQ_TYPE_LEVEL_LOW: 393 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); 394 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1); 395 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0); 396 irq_set_handler_locked(data, handle_level_irq); 397 break; 398 default: 399 return -ENOTSUPP; 400 } 401 break; 402 case SPRD_EIC_SYNC: 403 switch (flow_type) { 404 case IRQ_TYPE_EDGE_RISING: 405 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); 406 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); 407 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1); 408 irq_set_handler_locked(data, handle_edge_irq); 409 break; 410 case IRQ_TYPE_EDGE_FALLING: 411 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); 412 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); 413 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0); 414 irq_set_handler_locked(data, handle_edge_irq); 415 break; 416 case IRQ_TYPE_EDGE_BOTH: 417 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1); 418 irq_set_handler_locked(data, handle_edge_irq); 419 break; 420 case IRQ_TYPE_LEVEL_HIGH: 421 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); 422 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1); 423 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1); 424 irq_set_handler_locked(data, handle_level_irq); 425 break; 426 case IRQ_TYPE_LEVEL_LOW: 427 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); 428 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1); 429 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0); 430 irq_set_handler_locked(data, handle_level_irq); 431 break; 432 default: 433 return -ENOTSUPP; 434 } 435 default: 436 dev_err(chip->parent, "Unsupported EIC type.\n"); 437 return -ENOTSUPP; 438 } 439 440 return 0; 441 } 442 443 static void sprd_eic_toggle_trigger(struct gpio_chip *chip, unsigned int irq, 444 unsigned int offset) 445 { 446 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 447 struct irq_data *data = irq_get_irq_data(irq); 448 u32 trigger = irqd_get_trigger_type(data); 449 int state, post_state; 450 451 /* 452 * The debounce EIC and latch EIC can only support level trigger, so we 453 * can toggle the level trigger to emulate the edge trigger. 454 */ 455 if ((sprd_eic->type != SPRD_EIC_DEBOUNCE && 456 sprd_eic->type != SPRD_EIC_LATCH) || 457 !(trigger & IRQ_TYPE_EDGE_BOTH)) 458 return; 459 460 sprd_eic_irq_mask(data); 461 state = sprd_eic_get(chip, offset); 462 463 retry: 464 switch (sprd_eic->type) { 465 case SPRD_EIC_DEBOUNCE: 466 if (state) 467 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0); 468 else 469 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1); 470 break; 471 case SPRD_EIC_LATCH: 472 if (state) 473 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0); 474 else 475 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1); 476 break; 477 default: 478 sprd_eic_irq_unmask(data); 479 return; 480 } 481 482 post_state = sprd_eic_get(chip, offset); 483 if (state != post_state) { 484 dev_warn(chip->parent, "EIC level was changed.\n"); 485 state = post_state; 486 goto retry; 487 } 488 489 sprd_eic_irq_unmask(data); 490 } 491 492 static int sprd_eic_match_chip_by_type(struct gpio_chip *chip, void *data) 493 { 494 enum sprd_eic_type type = *(enum sprd_eic_type *)data; 495 496 return !strcmp(chip->label, sprd_eic_label_name[type]); 497 } 498 499 static void sprd_eic_handle_one_type(struct gpio_chip *chip) 500 { 501 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 502 u32 bank, n, girq; 503 504 for (bank = 0; bank * SPRD_EIC_PER_BANK_NR < chip->ngpio; bank++) { 505 void __iomem *base = sprd_eic_offset_base(sprd_eic, bank); 506 unsigned long reg; 507 508 switch (sprd_eic->type) { 509 case SPRD_EIC_DEBOUNCE: 510 reg = readl_relaxed(base + SPRD_EIC_DBNC_MIS) & 511 SPRD_EIC_DATA_MASK; 512 break; 513 case SPRD_EIC_LATCH: 514 reg = readl_relaxed(base + SPRD_EIC_LATCH_INTMSK) & 515 SPRD_EIC_DATA_MASK; 516 break; 517 case SPRD_EIC_ASYNC: 518 reg = readl_relaxed(base + SPRD_EIC_ASYNC_INTMSK) & 519 SPRD_EIC_DATA_MASK; 520 break; 521 case SPRD_EIC_SYNC: 522 reg = readl_relaxed(base + SPRD_EIC_SYNC_INTMSK) & 523 SPRD_EIC_DATA_MASK; 524 break; 525 default: 526 dev_err(chip->parent, "Unsupported EIC type.\n"); 527 return; 528 } 529 530 for_each_set_bit(n, ®, SPRD_EIC_PER_BANK_NR) { 531 girq = irq_find_mapping(chip->irq.domain, 532 bank * SPRD_EIC_PER_BANK_NR + n); 533 534 generic_handle_irq(girq); 535 sprd_eic_toggle_trigger(chip, girq, n); 536 } 537 } 538 } 539 540 static void sprd_eic_irq_handler(struct irq_desc *desc) 541 { 542 struct irq_chip *ic = irq_desc_get_chip(desc); 543 struct gpio_chip *chip; 544 enum sprd_eic_type type; 545 546 chained_irq_enter(ic, desc); 547 548 /* 549 * Since the digital-chip EIC 4 sub-modules (debounce, latch, async 550 * and sync) share one same interrupt line, we should iterate each 551 * EIC module to check if there are EIC interrupts were triggered. 552 */ 553 for (type = SPRD_EIC_DEBOUNCE; type < SPRD_EIC_MAX; type++) { 554 chip = gpiochip_find(&type, sprd_eic_match_chip_by_type); 555 if (!chip) 556 continue; 557 558 sprd_eic_handle_one_type(chip); 559 } 560 561 chained_irq_exit(ic, desc); 562 } 563 564 static int sprd_eic_probe(struct platform_device *pdev) 565 { 566 const struct sprd_eic_variant_data *pdata; 567 struct gpio_irq_chip *irq; 568 struct sprd_eic *sprd_eic; 569 struct resource *res; 570 int ret, i; 571 572 pdata = of_device_get_match_data(&pdev->dev); 573 if (!pdata) { 574 dev_err(&pdev->dev, "No matching driver data found.\n"); 575 return -EINVAL; 576 } 577 578 sprd_eic = devm_kzalloc(&pdev->dev, sizeof(*sprd_eic), GFP_KERNEL); 579 if (!sprd_eic) 580 return -ENOMEM; 581 582 spin_lock_init(&sprd_eic->lock); 583 sprd_eic->type = pdata->type; 584 585 sprd_eic->irq = platform_get_irq(pdev, 0); 586 if (sprd_eic->irq < 0) { 587 dev_err(&pdev->dev, "Failed to get EIC interrupt.\n"); 588 return sprd_eic->irq; 589 } 590 591 for (i = 0; i < SPRD_EIC_MAX_BANK; i++) { 592 /* 593 * We can have maximum 3 banks EICs, and each EIC has 594 * its own base address. But some platform maybe only 595 * have one bank EIC, thus base[1] and base[2] can be 596 * optional. 597 */ 598 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 599 if (!res) 600 continue; 601 602 sprd_eic->base[i] = devm_ioremap_resource(&pdev->dev, res); 603 if (IS_ERR(sprd_eic->base[i])) 604 return PTR_ERR(sprd_eic->base[i]); 605 } 606 607 sprd_eic->chip.label = sprd_eic_label_name[sprd_eic->type]; 608 sprd_eic->chip.ngpio = pdata->num_eics; 609 sprd_eic->chip.base = -1; 610 sprd_eic->chip.parent = &pdev->dev; 611 sprd_eic->chip.of_node = pdev->dev.of_node; 612 sprd_eic->chip.direction_input = sprd_eic_direction_input; 613 switch (sprd_eic->type) { 614 case SPRD_EIC_DEBOUNCE: 615 sprd_eic->chip.request = sprd_eic_request; 616 sprd_eic->chip.free = sprd_eic_free; 617 sprd_eic->chip.set_config = sprd_eic_set_config; 618 sprd_eic->chip.set = sprd_eic_set; 619 /* fall-through */ 620 case SPRD_EIC_ASYNC: 621 /* fall-through */ 622 case SPRD_EIC_SYNC: 623 sprd_eic->chip.get = sprd_eic_get; 624 break; 625 case SPRD_EIC_LATCH: 626 /* fall-through */ 627 default: 628 break; 629 } 630 631 sprd_eic->intc.name = dev_name(&pdev->dev); 632 sprd_eic->intc.irq_ack = sprd_eic_irq_ack; 633 sprd_eic->intc.irq_mask = sprd_eic_irq_mask; 634 sprd_eic->intc.irq_unmask = sprd_eic_irq_unmask; 635 sprd_eic->intc.irq_set_type = sprd_eic_irq_set_type; 636 sprd_eic->intc.flags = IRQCHIP_SKIP_SET_WAKE; 637 638 irq = &sprd_eic->chip.irq; 639 irq->chip = &sprd_eic->intc; 640 irq->handler = handle_bad_irq; 641 irq->default_type = IRQ_TYPE_NONE; 642 irq->parent_handler = sprd_eic_irq_handler; 643 irq->parent_handler_data = sprd_eic; 644 irq->num_parents = 1; 645 irq->parents = &sprd_eic->irq; 646 647 ret = devm_gpiochip_add_data(&pdev->dev, &sprd_eic->chip, sprd_eic); 648 if (ret < 0) { 649 dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret); 650 return ret; 651 } 652 653 platform_set_drvdata(pdev, sprd_eic); 654 return 0; 655 } 656 657 static const struct of_device_id sprd_eic_of_match[] = { 658 { 659 .compatible = "sprd,sc9860-eic-debounce", 660 .data = &sc9860_eic_dbnc_data, 661 }, 662 { 663 .compatible = "sprd,sc9860-eic-latch", 664 .data = &sc9860_eic_latch_data, 665 }, 666 { 667 .compatible = "sprd,sc9860-eic-async", 668 .data = &sc9860_eic_async_data, 669 }, 670 { 671 .compatible = "sprd,sc9860-eic-sync", 672 .data = &sc9860_eic_sync_data, 673 }, 674 { 675 /* end of list */ 676 } 677 }; 678 MODULE_DEVICE_TABLE(of, sprd_eic_of_match); 679 680 static struct platform_driver sprd_eic_driver = { 681 .probe = sprd_eic_probe, 682 .driver = { 683 .name = "sprd-eic", 684 .of_match_table = sprd_eic_of_match, 685 }, 686 }; 687 688 module_platform_driver(sprd_eic_driver); 689 690 MODULE_DESCRIPTION("Spreadtrum EIC driver"); 691 MODULE_LICENSE("GPL v2"); 692