1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Spreadtrum Communications Inc. 4 * Copyright (C) 2018 Linaro Ltd. 5 */ 6 7 #include <linux/bitops.h> 8 #include <linux/gpio/driver.h> 9 #include <linux/interrupt.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/notifier.h> 13 #include <linux/platform_device.h> 14 #include <linux/property.h> 15 #include <linux/spinlock.h> 16 17 /* EIC registers definition */ 18 #define SPRD_EIC_DBNC_DATA 0x0 19 #define SPRD_EIC_DBNC_DMSK 0x4 20 #define SPRD_EIC_DBNC_IEV 0x14 21 #define SPRD_EIC_DBNC_IE 0x18 22 #define SPRD_EIC_DBNC_RIS 0x1c 23 #define SPRD_EIC_DBNC_MIS 0x20 24 #define SPRD_EIC_DBNC_IC 0x24 25 #define SPRD_EIC_DBNC_TRIG 0x28 26 #define SPRD_EIC_DBNC_CTRL0 0x40 27 28 #define SPRD_EIC_LATCH_INTEN 0x0 29 #define SPRD_EIC_LATCH_INTRAW 0x4 30 #define SPRD_EIC_LATCH_INTMSK 0x8 31 #define SPRD_EIC_LATCH_INTCLR 0xc 32 #define SPRD_EIC_LATCH_INTPOL 0x10 33 #define SPRD_EIC_LATCH_INTMODE 0x14 34 35 #define SPRD_EIC_ASYNC_INTIE 0x0 36 #define SPRD_EIC_ASYNC_INTRAW 0x4 37 #define SPRD_EIC_ASYNC_INTMSK 0x8 38 #define SPRD_EIC_ASYNC_INTCLR 0xc 39 #define SPRD_EIC_ASYNC_INTMODE 0x10 40 #define SPRD_EIC_ASYNC_INTBOTH 0x14 41 #define SPRD_EIC_ASYNC_INTPOL 0x18 42 #define SPRD_EIC_ASYNC_DATA 0x1c 43 44 #define SPRD_EIC_SYNC_INTIE 0x0 45 #define SPRD_EIC_SYNC_INTRAW 0x4 46 #define SPRD_EIC_SYNC_INTMSK 0x8 47 #define SPRD_EIC_SYNC_INTCLR 0xc 48 #define SPRD_EIC_SYNC_INTMODE 0x10 49 #define SPRD_EIC_SYNC_INTBOTH 0x14 50 #define SPRD_EIC_SYNC_INTPOL 0x18 51 #define SPRD_EIC_SYNC_DATA 0x1c 52 53 /* 54 * The digital-chip EIC controller can support maximum 3 banks, and each bank 55 * contains 8 EICs. 56 */ 57 #define SPRD_EIC_MAX_BANK 3 58 #define SPRD_EIC_PER_BANK_NR 8 59 #define SPRD_EIC_DATA_MASK GENMASK(7, 0) 60 #define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1)) 61 #define SPRD_EIC_DBNC_MASK GENMASK(11, 0) 62 63 /* 64 * The Spreadtrum EIC (external interrupt controller) can be used only in 65 * input mode to generate interrupts if detecting input signals. 66 * 67 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules: 68 * debounce EIC, latch EIC, async EIC and sync EIC, 69 * 70 * The debounce EIC is used to capture the input signals' stable status 71 * (millisecond resolution) and a single-trigger mechanism is introduced 72 * into this sub-module to enhance the input event detection reliability. 73 * The debounce range is from 1ms to 4s with a step size of 1ms. 74 * 75 * The latch EIC is used to latch some special power down signals and 76 * generate interrupts, since the latch EIC does not depend on the APB clock 77 * to capture signals. 78 * 79 * The async EIC uses a 32k clock to capture the short signals (microsecond 80 * resolution) to generate interrupts by level or edge trigger. 81 * 82 * The EIC-sync is similar with GPIO's input function, which is a synchronized 83 * signal input register. 84 */ 85 enum sprd_eic_type { 86 SPRD_EIC_DEBOUNCE, 87 SPRD_EIC_LATCH, 88 SPRD_EIC_ASYNC, 89 SPRD_EIC_SYNC, 90 SPRD_EIC_MAX, 91 }; 92 93 struct sprd_eic { 94 struct gpio_chip chip; 95 struct notifier_block irq_nb; 96 void __iomem *base[SPRD_EIC_MAX_BANK]; 97 enum sprd_eic_type type; 98 spinlock_t lock; 99 int irq; 100 }; 101 102 static ATOMIC_NOTIFIER_HEAD(sprd_eic_irq_notifier); 103 104 static struct sprd_eic *to_sprd_eic(struct notifier_block *nb) 105 { 106 return container_of(nb, struct sprd_eic, irq_nb); 107 } 108 109 struct sprd_eic_variant_data { 110 enum sprd_eic_type type; 111 }; 112 113 static const char *sprd_eic_label_name[SPRD_EIC_MAX] = { 114 "eic-debounce", "eic-latch", "eic-async", 115 "eic-sync", 116 }; 117 118 static const struct sprd_eic_variant_data sc9860_eic_dbnc_data = { 119 .type = SPRD_EIC_DEBOUNCE, 120 }; 121 122 static const struct sprd_eic_variant_data sc9860_eic_latch_data = { 123 .type = SPRD_EIC_LATCH, 124 }; 125 126 static const struct sprd_eic_variant_data sc9860_eic_async_data = { 127 .type = SPRD_EIC_ASYNC, 128 }; 129 130 static const struct sprd_eic_variant_data sc9860_eic_sync_data = { 131 .type = SPRD_EIC_SYNC, 132 }; 133 134 static inline void __iomem *sprd_eic_offset_base(struct sprd_eic *sprd_eic, 135 unsigned int bank) 136 { 137 if (bank >= SPRD_EIC_MAX_BANK) 138 return NULL; 139 140 return sprd_eic->base[bank]; 141 } 142 143 static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset, 144 u16 reg, unsigned int val) 145 { 146 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 147 void __iomem *base = 148 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); 149 unsigned long flags; 150 u32 tmp; 151 152 spin_lock_irqsave(&sprd_eic->lock, flags); 153 tmp = readl_relaxed(base + reg); 154 155 if (val) 156 tmp |= BIT(SPRD_EIC_BIT(offset)); 157 else 158 tmp &= ~BIT(SPRD_EIC_BIT(offset)); 159 160 writel_relaxed(tmp, base + reg); 161 spin_unlock_irqrestore(&sprd_eic->lock, flags); 162 } 163 164 static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg) 165 { 166 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 167 void __iomem *base = 168 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); 169 170 return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset))); 171 } 172 173 static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset) 174 { 175 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1); 176 return 0; 177 } 178 179 static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset) 180 { 181 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0); 182 } 183 184 static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset) 185 { 186 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 187 188 switch (sprd_eic->type) { 189 case SPRD_EIC_DEBOUNCE: 190 return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA); 191 case SPRD_EIC_ASYNC: 192 return sprd_eic_read(chip, offset, SPRD_EIC_ASYNC_DATA); 193 case SPRD_EIC_SYNC: 194 return sprd_eic_read(chip, offset, SPRD_EIC_SYNC_DATA); 195 default: 196 return -ENOTSUPP; 197 } 198 } 199 200 static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset) 201 { 202 /* EICs are always input, nothing need to do here. */ 203 return 0; 204 } 205 206 static int sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value) 207 { 208 /* EICs are always input, nothing need to do here. */ 209 return 0; 210 } 211 212 static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset, 213 unsigned int debounce) 214 { 215 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 216 void __iomem *base = 217 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); 218 u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4; 219 u32 value = readl_relaxed(base + reg) & ~SPRD_EIC_DBNC_MASK; 220 221 value |= (debounce / 1000) & SPRD_EIC_DBNC_MASK; 222 writel_relaxed(value, base + reg); 223 224 return 0; 225 } 226 227 static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset, 228 unsigned long config) 229 { 230 unsigned long param = pinconf_to_config_param(config); 231 u32 arg = pinconf_to_config_argument(config); 232 233 if (param == PIN_CONFIG_INPUT_DEBOUNCE) 234 return sprd_eic_set_debounce(chip, offset, arg); 235 236 return -ENOTSUPP; 237 } 238 239 static void sprd_eic_irq_mask(struct irq_data *data) 240 { 241 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 242 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 243 u32 offset = irqd_to_hwirq(data); 244 245 switch (sprd_eic->type) { 246 case SPRD_EIC_DEBOUNCE: 247 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0); 248 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0); 249 break; 250 case SPRD_EIC_LATCH: 251 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0); 252 break; 253 case SPRD_EIC_ASYNC: 254 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0); 255 break; 256 case SPRD_EIC_SYNC: 257 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0); 258 break; 259 default: 260 dev_err(chip->parent, "Unsupported EIC type.\n"); 261 } 262 263 gpiochip_disable_irq(chip, offset); 264 } 265 266 static void sprd_eic_irq_unmask(struct irq_data *data) 267 { 268 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 269 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 270 u32 offset = irqd_to_hwirq(data); 271 272 gpiochip_enable_irq(chip, offset); 273 274 switch (sprd_eic->type) { 275 case SPRD_EIC_DEBOUNCE: 276 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1); 277 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1); 278 break; 279 case SPRD_EIC_LATCH: 280 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1); 281 break; 282 case SPRD_EIC_ASYNC: 283 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1); 284 break; 285 case SPRD_EIC_SYNC: 286 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1); 287 break; 288 default: 289 dev_err(chip->parent, "Unsupported EIC type.\n"); 290 } 291 } 292 293 static void sprd_eic_irq_ack(struct irq_data *data) 294 { 295 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 296 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 297 u32 offset = irqd_to_hwirq(data); 298 299 switch (sprd_eic->type) { 300 case SPRD_EIC_DEBOUNCE: 301 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1); 302 break; 303 case SPRD_EIC_LATCH: 304 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1); 305 break; 306 case SPRD_EIC_ASYNC: 307 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); 308 break; 309 case SPRD_EIC_SYNC: 310 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); 311 break; 312 default: 313 dev_err(chip->parent, "Unsupported EIC type.\n"); 314 } 315 } 316 317 static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type) 318 { 319 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 320 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 321 u32 offset = irqd_to_hwirq(data); 322 int state; 323 324 switch (sprd_eic->type) { 325 case SPRD_EIC_DEBOUNCE: 326 switch (flow_type) { 327 case IRQ_TYPE_LEVEL_HIGH: 328 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1); 329 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1); 330 break; 331 case IRQ_TYPE_LEVEL_LOW: 332 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0); 333 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1); 334 break; 335 case IRQ_TYPE_EDGE_RISING: 336 case IRQ_TYPE_EDGE_FALLING: 337 case IRQ_TYPE_EDGE_BOTH: 338 state = sprd_eic_get(chip, offset); 339 if (state) { 340 sprd_eic_update(chip, offset, 341 SPRD_EIC_DBNC_IEV, 0); 342 sprd_eic_update(chip, offset, 343 SPRD_EIC_DBNC_IC, 1); 344 } else { 345 sprd_eic_update(chip, offset, 346 SPRD_EIC_DBNC_IEV, 1); 347 sprd_eic_update(chip, offset, 348 SPRD_EIC_DBNC_IC, 1); 349 } 350 break; 351 default: 352 return -ENOTSUPP; 353 } 354 355 irq_set_handler_locked(data, handle_level_irq); 356 break; 357 case SPRD_EIC_LATCH: 358 switch (flow_type) { 359 case IRQ_TYPE_LEVEL_HIGH: 360 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0); 361 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1); 362 break; 363 case IRQ_TYPE_LEVEL_LOW: 364 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1); 365 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1); 366 break; 367 case IRQ_TYPE_EDGE_RISING: 368 case IRQ_TYPE_EDGE_FALLING: 369 case IRQ_TYPE_EDGE_BOTH: 370 state = sprd_eic_get(chip, offset); 371 if (state) { 372 sprd_eic_update(chip, offset, 373 SPRD_EIC_LATCH_INTPOL, 0); 374 sprd_eic_update(chip, offset, 375 SPRD_EIC_LATCH_INTCLR, 1); 376 } else { 377 sprd_eic_update(chip, offset, 378 SPRD_EIC_LATCH_INTPOL, 1); 379 sprd_eic_update(chip, offset, 380 SPRD_EIC_LATCH_INTCLR, 1); 381 } 382 break; 383 default: 384 return -ENOTSUPP; 385 } 386 387 irq_set_handler_locked(data, handle_level_irq); 388 break; 389 case SPRD_EIC_ASYNC: 390 switch (flow_type) { 391 case IRQ_TYPE_EDGE_RISING: 392 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); 393 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); 394 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1); 395 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); 396 irq_set_handler_locked(data, handle_edge_irq); 397 break; 398 case IRQ_TYPE_EDGE_FALLING: 399 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); 400 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); 401 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0); 402 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); 403 irq_set_handler_locked(data, handle_edge_irq); 404 break; 405 case IRQ_TYPE_EDGE_BOTH: 406 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); 407 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1); 408 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); 409 irq_set_handler_locked(data, handle_edge_irq); 410 break; 411 case IRQ_TYPE_LEVEL_HIGH: 412 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); 413 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1); 414 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1); 415 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); 416 irq_set_handler_locked(data, handle_level_irq); 417 break; 418 case IRQ_TYPE_LEVEL_LOW: 419 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); 420 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1); 421 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0); 422 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); 423 irq_set_handler_locked(data, handle_level_irq); 424 break; 425 default: 426 return -ENOTSUPP; 427 } 428 break; 429 case SPRD_EIC_SYNC: 430 switch (flow_type) { 431 case IRQ_TYPE_EDGE_RISING: 432 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); 433 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); 434 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1); 435 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); 436 irq_set_handler_locked(data, handle_edge_irq); 437 break; 438 case IRQ_TYPE_EDGE_FALLING: 439 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); 440 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); 441 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0); 442 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); 443 irq_set_handler_locked(data, handle_edge_irq); 444 break; 445 case IRQ_TYPE_EDGE_BOTH: 446 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); 447 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1); 448 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); 449 irq_set_handler_locked(data, handle_edge_irq); 450 break; 451 case IRQ_TYPE_LEVEL_HIGH: 452 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); 453 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1); 454 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1); 455 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); 456 irq_set_handler_locked(data, handle_level_irq); 457 break; 458 case IRQ_TYPE_LEVEL_LOW: 459 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); 460 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1); 461 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0); 462 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); 463 irq_set_handler_locked(data, handle_level_irq); 464 break; 465 default: 466 return -ENOTSUPP; 467 } 468 break; 469 default: 470 dev_err(chip->parent, "Unsupported EIC type.\n"); 471 return -ENOTSUPP; 472 } 473 474 return 0; 475 } 476 477 static void sprd_eic_toggle_trigger(struct gpio_chip *chip, unsigned int irq, 478 unsigned int offset) 479 { 480 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 481 struct irq_data *data = irq_get_irq_data(irq); 482 u32 trigger = irqd_get_trigger_type(data); 483 int state, post_state; 484 485 /* 486 * The debounce EIC and latch EIC can only support level trigger, so we 487 * can toggle the level trigger to emulate the edge trigger. 488 */ 489 if ((sprd_eic->type != SPRD_EIC_DEBOUNCE && 490 sprd_eic->type != SPRD_EIC_LATCH) || 491 !(trigger & IRQ_TYPE_EDGE_BOTH)) 492 return; 493 494 sprd_eic_irq_mask(data); 495 state = sprd_eic_get(chip, offset); 496 497 retry: 498 switch (sprd_eic->type) { 499 case SPRD_EIC_DEBOUNCE: 500 if (state) 501 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0); 502 else 503 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1); 504 break; 505 case SPRD_EIC_LATCH: 506 if (state) 507 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0); 508 else 509 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1); 510 break; 511 default: 512 sprd_eic_irq_unmask(data); 513 return; 514 } 515 516 post_state = sprd_eic_get(chip, offset); 517 if (state != post_state) { 518 dev_warn(chip->parent, "EIC level was changed.\n"); 519 state = post_state; 520 goto retry; 521 } 522 523 sprd_eic_irq_unmask(data); 524 } 525 526 static void sprd_eic_handle_one_type(struct gpio_chip *chip) 527 { 528 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 529 u32 bank, n, girq; 530 531 for (bank = 0; bank * SPRD_EIC_PER_BANK_NR < chip->ngpio; bank++) { 532 void __iomem *base = sprd_eic_offset_base(sprd_eic, bank); 533 unsigned long reg; 534 535 switch (sprd_eic->type) { 536 case SPRD_EIC_DEBOUNCE: 537 reg = readl_relaxed(base + SPRD_EIC_DBNC_MIS) & 538 SPRD_EIC_DATA_MASK; 539 break; 540 case SPRD_EIC_LATCH: 541 reg = readl_relaxed(base + SPRD_EIC_LATCH_INTMSK) & 542 SPRD_EIC_DATA_MASK; 543 break; 544 case SPRD_EIC_ASYNC: 545 reg = readl_relaxed(base + SPRD_EIC_ASYNC_INTMSK) & 546 SPRD_EIC_DATA_MASK; 547 break; 548 case SPRD_EIC_SYNC: 549 reg = readl_relaxed(base + SPRD_EIC_SYNC_INTMSK) & 550 SPRD_EIC_DATA_MASK; 551 break; 552 default: 553 dev_err(chip->parent, "Unsupported EIC type.\n"); 554 return; 555 } 556 557 for_each_set_bit(n, ®, SPRD_EIC_PER_BANK_NR) { 558 u32 offset = bank * SPRD_EIC_PER_BANK_NR + n; 559 560 girq = irq_find_mapping(chip->irq.domain, offset); 561 562 generic_handle_irq(girq); 563 sprd_eic_toggle_trigger(chip, girq, offset); 564 } 565 } 566 } 567 568 static void sprd_eic_irq_handler(struct irq_desc *desc) 569 { 570 struct irq_chip *ic = irq_desc_get_chip(desc); 571 572 chained_irq_enter(ic, desc); 573 574 /* 575 * Since the digital-chip EIC 4 sub-modules (debounce, latch, async 576 * and sync) share one same interrupt line, we should notify all of 577 * them to let them check if there are EIC interrupts were triggered. 578 */ 579 atomic_notifier_call_chain(&sprd_eic_irq_notifier, 0, NULL); 580 581 chained_irq_exit(ic, desc); 582 } 583 584 static int sprd_eic_irq_notify(struct notifier_block *nb, unsigned long action, 585 void *data) 586 { 587 struct sprd_eic *sprd_eic = to_sprd_eic(nb); 588 589 sprd_eic_handle_one_type(&sprd_eic->chip); 590 591 return NOTIFY_OK; 592 } 593 594 static const struct irq_chip sprd_eic_irq = { 595 .name = "sprd-eic", 596 .irq_ack = sprd_eic_irq_ack, 597 .irq_mask = sprd_eic_irq_mask, 598 .irq_unmask = sprd_eic_irq_unmask, 599 .irq_set_type = sprd_eic_irq_set_type, 600 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, 601 GPIOCHIP_IRQ_RESOURCE_HELPERS, 602 }; 603 604 static void sprd_eic_unregister_notifier(void *data) 605 { 606 struct notifier_block *nb = data; 607 608 atomic_notifier_chain_unregister(&sprd_eic_irq_notifier, nb); 609 } 610 611 static int sprd_eic_probe(struct platform_device *pdev) 612 { 613 const struct sprd_eic_variant_data *pdata; 614 struct device *dev = &pdev->dev; 615 struct gpio_irq_chip *irq; 616 struct sprd_eic *sprd_eic; 617 struct resource *res; 618 u16 num_banks = 0; 619 int ret, i; 620 621 pdata = device_get_match_data(dev); 622 if (!pdata) { 623 dev_err(dev, "No matching driver data found.\n"); 624 return -EINVAL; 625 } 626 627 sprd_eic = devm_kzalloc(dev, sizeof(*sprd_eic), GFP_KERNEL); 628 if (!sprd_eic) 629 return -ENOMEM; 630 631 spin_lock_init(&sprd_eic->lock); 632 sprd_eic->type = pdata->type; 633 634 sprd_eic->irq = platform_get_irq(pdev, 0); 635 if (sprd_eic->irq < 0) 636 return sprd_eic->irq; 637 638 for (i = 0; i < SPRD_EIC_MAX_BANK; i++) { 639 /* 640 * We can have maximum 3 banks EICs, and each EIC has 641 * its own base address. But some platform maybe only 642 * have one bank EIC, thus base[1] and base[2] can be 643 * optional. 644 */ 645 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 646 if (!res) 647 break; 648 649 sprd_eic->base[i] = devm_ioremap_resource(dev, res); 650 if (IS_ERR(sprd_eic->base[i])) 651 return PTR_ERR(sprd_eic->base[i]); 652 653 num_banks++; 654 } 655 656 sprd_eic->chip.label = sprd_eic_label_name[sprd_eic->type]; 657 sprd_eic->chip.ngpio = num_banks * SPRD_EIC_PER_BANK_NR; 658 sprd_eic->chip.base = -1; 659 sprd_eic->chip.parent = dev; 660 sprd_eic->chip.direction_input = sprd_eic_direction_input; 661 switch (sprd_eic->type) { 662 case SPRD_EIC_DEBOUNCE: 663 sprd_eic->chip.request = sprd_eic_request; 664 sprd_eic->chip.free = sprd_eic_free; 665 sprd_eic->chip.set_config = sprd_eic_set_config; 666 sprd_eic->chip.set_rv = sprd_eic_set; 667 fallthrough; 668 case SPRD_EIC_ASYNC: 669 case SPRD_EIC_SYNC: 670 sprd_eic->chip.get = sprd_eic_get; 671 break; 672 case SPRD_EIC_LATCH: 673 default: 674 break; 675 } 676 677 irq = &sprd_eic->chip.irq; 678 gpio_irq_chip_set_chip(irq, &sprd_eic_irq); 679 irq->handler = handle_bad_irq; 680 irq->default_type = IRQ_TYPE_NONE; 681 irq->parent_handler = sprd_eic_irq_handler; 682 irq->parent_handler_data = sprd_eic; 683 irq->num_parents = 1; 684 irq->parents = &sprd_eic->irq; 685 686 ret = devm_gpiochip_add_data(dev, &sprd_eic->chip, sprd_eic); 687 if (ret < 0) { 688 dev_err(dev, "Could not register gpiochip %d.\n", ret); 689 return ret; 690 } 691 692 sprd_eic->irq_nb.notifier_call = sprd_eic_irq_notify; 693 ret = atomic_notifier_chain_register(&sprd_eic_irq_notifier, 694 &sprd_eic->irq_nb); 695 if (ret) 696 return dev_err_probe(dev, ret, 697 "Failed to register with the interrupt notifier"); 698 699 return devm_add_action_or_reset(dev, sprd_eic_unregister_notifier, 700 &sprd_eic->irq_nb); 701 } 702 703 static const struct of_device_id sprd_eic_of_match[] = { 704 { 705 .compatible = "sprd,sc9860-eic-debounce", 706 .data = &sc9860_eic_dbnc_data, 707 }, 708 { 709 .compatible = "sprd,sc9860-eic-latch", 710 .data = &sc9860_eic_latch_data, 711 }, 712 { 713 .compatible = "sprd,sc9860-eic-async", 714 .data = &sc9860_eic_async_data, 715 }, 716 { 717 .compatible = "sprd,sc9860-eic-sync", 718 .data = &sc9860_eic_sync_data, 719 }, 720 { 721 /* end of list */ 722 } 723 }; 724 MODULE_DEVICE_TABLE(of, sprd_eic_of_match); 725 726 static struct platform_driver sprd_eic_driver = { 727 .probe = sprd_eic_probe, 728 .driver = { 729 .name = "sprd-eic", 730 .of_match_table = sprd_eic_of_match, 731 }, 732 }; 733 734 module_platform_driver(sprd_eic_driver); 735 736 MODULE_DESCRIPTION("Spreadtrum EIC driver"); 737 MODULE_LICENSE("GPL v2"); 738