1 /* 2 * TI DaVinci GPIO Support 3 * 4 * Copyright (c) 2006-2007 David Brownell 5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 #include <linux/gpio.h> 13 #include <linux/errno.h> 14 #include <linux/kernel.h> 15 #include <linux/clk.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/irq.h> 19 #include <linux/platform_device.h> 20 #include <linux/platform_data/gpio-davinci.h> 21 22 struct davinci_gpio_regs { 23 u32 dir; 24 u32 out_data; 25 u32 set_data; 26 u32 clr_data; 27 u32 in_data; 28 u32 set_rising; 29 u32 clr_rising; 30 u32 set_falling; 31 u32 clr_falling; 32 u32 intstat; 33 }; 34 35 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ 36 37 #define chip2controller(chip) \ 38 container_of(chip, struct davinci_gpio_controller, chip) 39 40 static void __iomem *gpio_base; 41 42 static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio) 43 { 44 void __iomem *ptr; 45 46 if (gpio < 32 * 1) 47 ptr = gpio_base + 0x10; 48 else if (gpio < 32 * 2) 49 ptr = gpio_base + 0x38; 50 else if (gpio < 32 * 3) 51 ptr = gpio_base + 0x60; 52 else if (gpio < 32 * 4) 53 ptr = gpio_base + 0x88; 54 else if (gpio < 32 * 5) 55 ptr = gpio_base + 0xb0; 56 else 57 ptr = NULL; 58 return ptr; 59 } 60 61 static inline struct davinci_gpio_regs __iomem *irq2regs(int irq) 62 { 63 struct davinci_gpio_regs __iomem *g; 64 65 g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq); 66 67 return g; 68 } 69 70 static int davinci_gpio_irq_setup(struct platform_device *pdev); 71 72 /*--------------------------------------------------------------------------*/ 73 74 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ 75 static inline int __davinci_direction(struct gpio_chip *chip, 76 unsigned offset, bool out, int value) 77 { 78 struct davinci_gpio_controller *d = chip2controller(chip); 79 struct davinci_gpio_regs __iomem *g = d->regs; 80 unsigned long flags; 81 u32 temp; 82 u32 mask = 1 << offset; 83 84 spin_lock_irqsave(&d->lock, flags); 85 temp = __raw_readl(&g->dir); 86 if (out) { 87 temp &= ~mask; 88 __raw_writel(mask, value ? &g->set_data : &g->clr_data); 89 } else { 90 temp |= mask; 91 } 92 __raw_writel(temp, &g->dir); 93 spin_unlock_irqrestore(&d->lock, flags); 94 95 return 0; 96 } 97 98 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) 99 { 100 return __davinci_direction(chip, offset, false, 0); 101 } 102 103 static int 104 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) 105 { 106 return __davinci_direction(chip, offset, true, value); 107 } 108 109 /* 110 * Read the pin's value (works even if it's set up as output); 111 * returns zero/nonzero. 112 * 113 * Note that changes are synched to the GPIO clock, so reading values back 114 * right after you've set them may give old values. 115 */ 116 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) 117 { 118 struct davinci_gpio_controller *d = chip2controller(chip); 119 struct davinci_gpio_regs __iomem *g = d->regs; 120 121 return (1 << offset) & __raw_readl(&g->in_data); 122 } 123 124 /* 125 * Assuming the pin is muxed as a gpio output, set its output value. 126 */ 127 static void 128 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 129 { 130 struct davinci_gpio_controller *d = chip2controller(chip); 131 struct davinci_gpio_regs __iomem *g = d->regs; 132 133 __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); 134 } 135 136 static int davinci_gpio_probe(struct platform_device *pdev) 137 { 138 int i, base; 139 unsigned ngpio; 140 struct davinci_gpio_controller *chips; 141 struct davinci_gpio_platform_data *pdata; 142 struct davinci_gpio_regs __iomem *regs; 143 struct device *dev = &pdev->dev; 144 struct resource *res; 145 146 pdata = dev->platform_data; 147 if (!pdata) { 148 dev_err(dev, "No platform data found\n"); 149 return -EINVAL; 150 } 151 152 /* 153 * The gpio banks conceptually expose a segmented bitmap, 154 * and "ngpio" is one more than the largest zero-based 155 * bit index that's valid. 156 */ 157 ngpio = pdata->ngpio; 158 if (ngpio == 0) { 159 dev_err(dev, "How many GPIOs?\n"); 160 return -EINVAL; 161 } 162 163 if (WARN_ON(DAVINCI_N_GPIO < ngpio)) 164 ngpio = DAVINCI_N_GPIO; 165 166 chips = devm_kzalloc(dev, 167 ngpio * sizeof(struct davinci_gpio_controller), 168 GFP_KERNEL); 169 if (!chips) { 170 dev_err(dev, "Memory allocation failed\n"); 171 return -ENOMEM; 172 } 173 174 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 175 if (!res) { 176 dev_err(dev, "Invalid memory resource\n"); 177 return -EBUSY; 178 } 179 180 gpio_base = devm_ioremap_resource(dev, res); 181 if (IS_ERR(gpio_base)) 182 return PTR_ERR(gpio_base); 183 184 for (i = 0, base = 0; base < ngpio; i++, base += 32) { 185 chips[i].chip.label = "DaVinci"; 186 187 chips[i].chip.direction_input = davinci_direction_in; 188 chips[i].chip.get = davinci_gpio_get; 189 chips[i].chip.direction_output = davinci_direction_out; 190 chips[i].chip.set = davinci_gpio_set; 191 192 chips[i].chip.base = base; 193 chips[i].chip.ngpio = ngpio - base; 194 if (chips[i].chip.ngpio > 32) 195 chips[i].chip.ngpio = 32; 196 197 spin_lock_init(&chips[i].lock); 198 199 regs = gpio2regs(base); 200 chips[i].regs = regs; 201 chips[i].set_data = ®s->set_data; 202 chips[i].clr_data = ®s->clr_data; 203 chips[i].in_data = ®s->in_data; 204 205 gpiochip_add(&chips[i].chip); 206 } 207 208 platform_set_drvdata(pdev, chips); 209 davinci_gpio_irq_setup(pdev); 210 return 0; 211 } 212 213 /*--------------------------------------------------------------------------*/ 214 /* 215 * We expect irqs will normally be set up as input pins, but they can also be 216 * used as output pins ... which is convenient for testing. 217 * 218 * NOTE: The first few GPIOs also have direct INTC hookups in addition 219 * to their GPIOBNK0 irq, with a bit less overhead. 220 * 221 * All those INTC hookups (direct, plus several IRQ banks) can also 222 * serve as EDMA event triggers. 223 */ 224 225 static void gpio_irq_disable(struct irq_data *d) 226 { 227 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); 228 u32 mask = (u32) irq_data_get_irq_handler_data(d); 229 230 __raw_writel(mask, &g->clr_falling); 231 __raw_writel(mask, &g->clr_rising); 232 } 233 234 static void gpio_irq_enable(struct irq_data *d) 235 { 236 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); 237 u32 mask = (u32) irq_data_get_irq_handler_data(d); 238 unsigned status = irqd_get_trigger_type(d); 239 240 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; 241 if (!status) 242 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; 243 244 if (status & IRQ_TYPE_EDGE_FALLING) 245 __raw_writel(mask, &g->set_falling); 246 if (status & IRQ_TYPE_EDGE_RISING) 247 __raw_writel(mask, &g->set_rising); 248 } 249 250 static int gpio_irq_type(struct irq_data *d, unsigned trigger) 251 { 252 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 253 return -EINVAL; 254 255 return 0; 256 } 257 258 static struct irq_chip gpio_irqchip = { 259 .name = "GPIO", 260 .irq_enable = gpio_irq_enable, 261 .irq_disable = gpio_irq_disable, 262 .irq_set_type = gpio_irq_type, 263 .flags = IRQCHIP_SET_TYPE_MASKED, 264 }; 265 266 static void 267 gpio_irq_handler(unsigned irq, struct irq_desc *desc) 268 { 269 struct davinci_gpio_regs __iomem *g; 270 u32 mask = 0xffff; 271 struct davinci_gpio_controller *d; 272 273 d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc); 274 g = (struct davinci_gpio_regs __iomem *)d->regs; 275 276 /* we only care about one bank */ 277 if (irq & 1) 278 mask <<= 16; 279 280 /* temporarily mask (level sensitive) parent IRQ */ 281 desc->irq_data.chip->irq_mask(&desc->irq_data); 282 desc->irq_data.chip->irq_ack(&desc->irq_data); 283 while (1) { 284 u32 status; 285 int n; 286 int res; 287 288 /* ack any irqs */ 289 status = __raw_readl(&g->intstat) & mask; 290 if (!status) 291 break; 292 __raw_writel(status, &g->intstat); 293 294 /* now demux them to the right lowlevel handler */ 295 n = d->irq_base; 296 if (irq & 1) { 297 n += 16; 298 status >>= 16; 299 } 300 301 while (status) { 302 res = ffs(status); 303 n += res; 304 generic_handle_irq(n - 1); 305 status >>= res; 306 } 307 } 308 desc->irq_data.chip->irq_unmask(&desc->irq_data); 309 /* now it may re-trigger */ 310 } 311 312 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) 313 { 314 struct davinci_gpio_controller *d = chip2controller(chip); 315 316 if (d->irq_base >= 0) 317 return d->irq_base + offset; 318 else 319 return -ENODEV; 320 } 321 322 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) 323 { 324 struct davinci_gpio_controller *d = chip2controller(chip); 325 326 /* 327 * NOTE: we assume for now that only irqs in the first gpio_chip 328 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). 329 */ 330 if (offset < d->gpio_unbanked) 331 return d->gpio_irq + offset; 332 else 333 return -ENODEV; 334 } 335 336 static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) 337 { 338 struct davinci_gpio_controller *d; 339 struct davinci_gpio_regs __iomem *g; 340 u32 mask; 341 342 d = (struct davinci_gpio_controller *)data->handler_data; 343 g = (struct davinci_gpio_regs __iomem *)d->regs; 344 mask = __gpio_mask(data->irq - d->gpio_irq); 345 346 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 347 return -EINVAL; 348 349 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) 350 ? &g->set_falling : &g->clr_falling); 351 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) 352 ? &g->set_rising : &g->clr_rising); 353 354 return 0; 355 } 356 357 /* 358 * NOTE: for suspend/resume, probably best to make a platform_device with 359 * suspend_late/resume_resume calls hooking into results of the set_wake() 360 * calls ... so if no gpios are wakeup events the clock can be disabled, 361 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 362 * (dm6446) can be set appropriately for GPIOV33 pins. 363 */ 364 365 static int davinci_gpio_irq_setup(struct platform_device *pdev) 366 { 367 unsigned gpio, irq, bank; 368 struct clk *clk; 369 u32 binten = 0; 370 unsigned ngpio, bank_irq; 371 struct device *dev = &pdev->dev; 372 struct resource *res; 373 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); 374 struct davinci_gpio_platform_data *pdata = dev->platform_data; 375 struct davinci_gpio_regs __iomem *g; 376 377 ngpio = pdata->ngpio; 378 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 379 if (!res) { 380 dev_err(dev, "Invalid IRQ resource\n"); 381 return -EBUSY; 382 } 383 384 bank_irq = res->start; 385 386 if (!bank_irq) { 387 dev_err(dev, "Invalid IRQ resource\n"); 388 return -ENODEV; 389 } 390 391 clk = devm_clk_get(dev, "gpio"); 392 if (IS_ERR(clk)) { 393 printk(KERN_ERR "Error %ld getting gpio clock?\n", 394 PTR_ERR(clk)); 395 return PTR_ERR(clk); 396 } 397 clk_prepare_enable(clk); 398 399 /* 400 * Arrange gpio_to_irq() support, handling either direct IRQs or 401 * banked IRQs. Having GPIOs in the first GPIO bank use direct 402 * IRQs, while the others use banked IRQs, would need some setup 403 * tweaks to recognize hardware which can do that. 404 */ 405 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { 406 chips[bank].chip.to_irq = gpio_to_irq_banked; 407 chips[bank].irq_base = pdata->gpio_unbanked 408 ? -EINVAL 409 : (pdata->intc_irq_num + gpio); 410 } 411 412 /* 413 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO 414 * controller only handling trigger modes. We currently assume no 415 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. 416 */ 417 if (pdata->gpio_unbanked) { 418 static struct irq_chip_type gpio_unbanked; 419 420 /* pass "bank 0" GPIO IRQs to AINTC */ 421 chips[0].chip.to_irq = gpio_to_irq_unbanked; 422 chips[0].gpio_irq = bank_irq; 423 chips[0].gpio_unbanked = pdata->gpio_unbanked; 424 binten = BIT(0); 425 426 /* AINTC handles mask/unmask; GPIO handles triggering */ 427 irq = bank_irq; 428 gpio_unbanked = *container_of(irq_get_chip(irq), 429 struct irq_chip_type, chip); 430 gpio_unbanked.chip.name = "GPIO-AINTC"; 431 gpio_unbanked.chip.irq_set_type = gpio_irq_type_unbanked; 432 433 /* default trigger: both edges */ 434 g = gpio2regs(0); 435 __raw_writel(~0, &g->set_falling); 436 __raw_writel(~0, &g->set_rising); 437 438 /* set the direct IRQs up to use that irqchip */ 439 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) { 440 irq_set_chip(irq, &gpio_unbanked.chip); 441 irq_set_handler_data(irq, &chips[gpio / 32]); 442 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); 443 } 444 445 goto done; 446 } 447 448 /* 449 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we 450 * then chain through our own handler. 451 */ 452 for (gpio = 0, irq = gpio_to_irq(0), bank = 0; 453 gpio < ngpio; 454 bank++, bank_irq++) { 455 unsigned i; 456 457 /* disabled by default, enabled only as needed */ 458 g = gpio2regs(gpio); 459 __raw_writel(~0, &g->clr_falling); 460 __raw_writel(~0, &g->clr_rising); 461 462 /* set up all irqs in this bank */ 463 irq_set_chained_handler(bank_irq, gpio_irq_handler); 464 465 /* 466 * Each chip handles 32 gpios, and each irq bank consists of 16 467 * gpio irqs. Pass the irq bank's corresponding controller to 468 * the chained irq handler. 469 */ 470 irq_set_handler_data(bank_irq, &chips[gpio / 32]); 471 472 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { 473 irq_set_chip(irq, &gpio_irqchip); 474 irq_set_chip_data(irq, (__force void *)g); 475 irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); 476 irq_set_handler(irq, handle_simple_irq); 477 set_irq_flags(irq, IRQF_VALID); 478 } 479 480 binten |= BIT(bank); 481 } 482 483 done: 484 /* 485 * BINTEN -- per-bank interrupt enable. genirq would also let these 486 * bits be set/cleared dynamically. 487 */ 488 __raw_writel(binten, gpio_base + BINTEN); 489 490 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); 491 492 return 0; 493 } 494 495 static struct platform_driver davinci_gpio_driver = { 496 .probe = davinci_gpio_probe, 497 .driver = { 498 .name = "davinci_gpio", 499 .owner = THIS_MODULE, 500 }, 501 }; 502 503 /** 504 * GPIO driver registration needs to be done before machine_init functions 505 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall. 506 */ 507 static int __init davinci_gpio_drv_reg(void) 508 { 509 return platform_driver_register(&davinci_gpio_driver); 510 } 511 postcore_initcall(davinci_gpio_drv_reg); 512