1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * TI DaVinci GPIO Support 4 * 5 * Copyright (c) 2006-2007 David Brownell 6 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> 7 */ 8 9 #include <linux/gpio/driver.h> 10 #include <linux/errno.h> 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/err.h> 14 #include <linux/io.h> 15 #include <linux/irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/platform_device.h> 21 #include <linux/property.h> 22 #include <linux/irqchip/chained_irq.h> 23 #include <linux/spinlock.h> 24 #include <linux/pm_runtime.h> 25 26 #define MAX_REGS_BANKS 5 27 #define MAX_INT_PER_BANK 32 28 29 struct davinci_gpio_regs { 30 u32 dir; 31 u32 out_data; 32 u32 set_data; 33 u32 clr_data; 34 u32 in_data; 35 u32 set_rising; 36 u32 clr_rising; 37 u32 set_falling; 38 u32 clr_falling; 39 u32 intstat; 40 }; 41 42 typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq); 43 44 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ 45 46 static void __iomem *gpio_base; 47 static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0}; 48 49 struct davinci_gpio_irq_data { 50 void __iomem *regs; 51 struct davinci_gpio_controller *chip; 52 int bank_num; 53 }; 54 55 struct davinci_gpio_controller { 56 struct gpio_chip chip; 57 struct irq_domain *irq_domain; 58 /* Serialize access to GPIO registers */ 59 spinlock_t lock; 60 void __iomem *regs[MAX_REGS_BANKS]; 61 int gpio_unbanked; 62 int irqs[MAX_INT_PER_BANK]; 63 struct davinci_gpio_regs context[MAX_REGS_BANKS]; 64 u32 binten_context; 65 }; 66 67 static inline u32 __gpio_mask(unsigned gpio) 68 { 69 return 1 << (gpio % 32); 70 } 71 72 static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d) 73 { 74 struct davinci_gpio_regs __iomem *g; 75 76 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d); 77 78 return g; 79 } 80 81 static int davinci_gpio_irq_setup(struct platform_device *pdev); 82 83 /*--------------------------------------------------------------------------*/ 84 85 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ 86 static inline int __davinci_direction(struct gpio_chip *chip, 87 unsigned offset, bool out, int value) 88 { 89 struct davinci_gpio_controller *d = gpiochip_get_data(chip); 90 struct davinci_gpio_regs __iomem *g; 91 unsigned long flags; 92 u32 temp; 93 int bank = offset / 32; 94 u32 mask = __gpio_mask(offset); 95 96 g = d->regs[bank]; 97 spin_lock_irqsave(&d->lock, flags); 98 temp = readl_relaxed(&g->dir); 99 if (out) { 100 temp &= ~mask; 101 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); 102 } else { 103 temp |= mask; 104 } 105 writel_relaxed(temp, &g->dir); 106 spin_unlock_irqrestore(&d->lock, flags); 107 108 return 0; 109 } 110 111 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) 112 { 113 return __davinci_direction(chip, offset, false, 0); 114 } 115 116 static int 117 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) 118 { 119 return __davinci_direction(chip, offset, true, value); 120 } 121 122 /* 123 * Read the pin's value (works even if it's set up as output); 124 * returns zero/nonzero. 125 * 126 * Note that changes are synched to the GPIO clock, so reading values back 127 * right after you've set them may give old values. 128 */ 129 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) 130 { 131 struct davinci_gpio_controller *d = gpiochip_get_data(chip); 132 struct davinci_gpio_regs __iomem *g; 133 int bank = offset / 32; 134 135 g = d->regs[bank]; 136 137 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data)); 138 } 139 140 /* 141 * Assuming the pin is muxed as a gpio output, set its output value. 142 */ 143 static void 144 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 145 { 146 struct davinci_gpio_controller *d = gpiochip_get_data(chip); 147 struct davinci_gpio_regs __iomem *g; 148 int bank = offset / 32; 149 150 g = d->regs[bank]; 151 152 writel_relaxed(__gpio_mask(offset), 153 value ? &g->set_data : &g->clr_data); 154 } 155 156 static int davinci_gpio_probe(struct platform_device *pdev) 157 { 158 int bank, i, ret = 0; 159 unsigned int ngpio, nbank, nirq, gpio_unbanked; 160 struct davinci_gpio_controller *chips; 161 struct device *dev = &pdev->dev; 162 struct device_node *dn = dev_of_node(dev); 163 164 /* 165 * The gpio banks conceptually expose a segmented bitmap, 166 * and "ngpio" is one more than the largest zero-based 167 * bit index that's valid. 168 */ 169 ret = of_property_read_u32(dn, "ti,ngpio", &ngpio); 170 if (ret) 171 return dev_err_probe(dev, ret, "Failed to get the number of GPIOs\n"); 172 if (ngpio == 0) 173 return dev_err_probe(dev, -EINVAL, "How many GPIOs?\n"); 174 175 /* 176 * If there are unbanked interrupts then the number of 177 * interrupts is equal to number of gpios else all are banked so 178 * number of interrupts is equal to number of banks(each with 16 gpios) 179 */ 180 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", 181 &gpio_unbanked); 182 if (ret) 183 return dev_err_probe(dev, ret, "Failed to get the unbanked GPIOs property\n"); 184 185 if (gpio_unbanked) 186 nirq = gpio_unbanked; 187 else 188 nirq = DIV_ROUND_UP(ngpio, 16); 189 190 if (nirq > MAX_INT_PER_BANK) { 191 dev_err(dev, "Too many IRQs!\n"); 192 return -EINVAL; 193 } 194 195 chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL); 196 if (!chips) 197 return -ENOMEM; 198 199 gpio_base = devm_platform_ioremap_resource(pdev, 0); 200 if (IS_ERR(gpio_base)) 201 return PTR_ERR(gpio_base); 202 203 for (i = 0; i < nirq; i++) { 204 chips->irqs[i] = platform_get_irq(pdev, i); 205 if (chips->irqs[i] < 0) 206 return chips->irqs[i]; 207 } 208 209 chips->chip.label = dev_name(dev); 210 211 chips->chip.direction_input = davinci_direction_in; 212 chips->chip.get = davinci_gpio_get; 213 chips->chip.direction_output = davinci_direction_out; 214 chips->chip.set = davinci_gpio_set; 215 216 chips->chip.ngpio = ngpio; 217 chips->chip.base = -1; 218 219 #ifdef CONFIG_OF_GPIO 220 chips->chip.parent = dev; 221 chips->chip.request = gpiochip_generic_request; 222 chips->chip.free = gpiochip_generic_free; 223 #endif 224 spin_lock_init(&chips->lock); 225 226 chips->gpio_unbanked = gpio_unbanked; 227 228 nbank = DIV_ROUND_UP(ngpio, 32); 229 for (bank = 0; bank < nbank; bank++) 230 chips->regs[bank] = gpio_base + offset_array[bank]; 231 232 ret = devm_gpiochip_add_data(dev, &chips->chip, chips); 233 if (ret) 234 return ret; 235 236 platform_set_drvdata(pdev, chips); 237 ret = davinci_gpio_irq_setup(pdev); 238 if (ret) 239 return ret; 240 241 return 0; 242 } 243 244 /*--------------------------------------------------------------------------*/ 245 /* 246 * We expect irqs will normally be set up as input pins, but they can also be 247 * used as output pins ... which is convenient for testing. 248 * 249 * NOTE: The first few GPIOs also have direct INTC hookups in addition 250 * to their GPIOBNK0 irq, with a bit less overhead. 251 * 252 * All those INTC hookups (direct, plus several IRQ banks) can also 253 * serve as EDMA event triggers. 254 */ 255 256 static void gpio_irq_disable(struct irq_data *d) 257 { 258 struct davinci_gpio_regs __iomem *g = irq2regs(d); 259 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d); 260 261 writel_relaxed(mask, &g->clr_falling); 262 writel_relaxed(mask, &g->clr_rising); 263 } 264 265 static void gpio_irq_enable(struct irq_data *d) 266 { 267 struct davinci_gpio_regs __iomem *g = irq2regs(d); 268 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d); 269 unsigned status = irqd_get_trigger_type(d); 270 271 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; 272 if (!status) 273 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; 274 275 if (status & IRQ_TYPE_EDGE_FALLING) 276 writel_relaxed(mask, &g->set_falling); 277 if (status & IRQ_TYPE_EDGE_RISING) 278 writel_relaxed(mask, &g->set_rising); 279 } 280 281 static int gpio_irq_type(struct irq_data *d, unsigned trigger) 282 { 283 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 284 return -EINVAL; 285 286 return 0; 287 } 288 289 static struct irq_chip gpio_irqchip = { 290 .name = "GPIO", 291 .irq_enable = gpio_irq_enable, 292 .irq_disable = gpio_irq_disable, 293 .irq_set_type = gpio_irq_type, 294 .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_SKIP_SET_WAKE, 295 }; 296 297 static void gpio_irq_handler(struct irq_desc *desc) 298 { 299 struct davinci_gpio_regs __iomem *g; 300 u32 mask = 0xffff; 301 int bank_num; 302 struct davinci_gpio_controller *d; 303 struct davinci_gpio_irq_data *irqdata; 304 305 irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc); 306 bank_num = irqdata->bank_num; 307 g = irqdata->regs; 308 d = irqdata->chip; 309 310 /* we only care about one bank */ 311 if ((bank_num % 2) == 1) 312 mask <<= 16; 313 314 /* temporarily mask (level sensitive) parent IRQ */ 315 chained_irq_enter(irq_desc_get_chip(desc), desc); 316 while (1) { 317 u32 status; 318 int bit; 319 irq_hw_number_t hw_irq; 320 321 /* ack any irqs */ 322 status = readl_relaxed(&g->intstat) & mask; 323 if (!status) 324 break; 325 writel_relaxed(status, &g->intstat); 326 327 /* now demux them to the right lowlevel handler */ 328 329 while (status) { 330 bit = __ffs(status); 331 status &= ~BIT(bit); 332 /* Max number of gpios per controller is 144 so 333 * hw_irq will be in [0..143] 334 */ 335 hw_irq = (bank_num / 2) * 32 + bit; 336 337 generic_handle_domain_irq(d->irq_domain, hw_irq); 338 } 339 } 340 chained_irq_exit(irq_desc_get_chip(desc), desc); 341 /* now it may re-trigger */ 342 } 343 344 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) 345 { 346 struct davinci_gpio_controller *d = gpiochip_get_data(chip); 347 348 if (d->irq_domain) 349 return irq_create_mapping(d->irq_domain, offset); 350 else 351 return -ENXIO; 352 } 353 354 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) 355 { 356 struct davinci_gpio_controller *d = gpiochip_get_data(chip); 357 358 /* 359 * NOTE: we assume for now that only irqs in the first gpio_chip 360 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). 361 */ 362 if (offset < d->gpio_unbanked) 363 return d->irqs[offset]; 364 else 365 return -ENODEV; 366 } 367 368 static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) 369 { 370 struct davinci_gpio_controller *d; 371 struct davinci_gpio_regs __iomem *g; 372 u32 mask, i; 373 374 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data); 375 g = (struct davinci_gpio_regs __iomem *)d->regs[0]; 376 for (i = 0; i < MAX_INT_PER_BANK; i++) 377 if (data->irq == d->irqs[i]) 378 break; 379 380 if (i == MAX_INT_PER_BANK) 381 return -EINVAL; 382 383 mask = __gpio_mask(i); 384 385 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 386 return -EINVAL; 387 388 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) 389 ? &g->set_falling : &g->clr_falling); 390 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING) 391 ? &g->set_rising : &g->clr_rising); 392 393 return 0; 394 } 395 396 static int 397 davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, 398 irq_hw_number_t hw) 399 { 400 struct davinci_gpio_controller *chips = 401 (struct davinci_gpio_controller *)d->host_data; 402 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32]; 403 404 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, 405 "davinci_gpio"); 406 irq_set_irq_type(irq, IRQ_TYPE_NONE); 407 irq_set_chip_data(irq, (__force void *)g); 408 irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw)); 409 410 return 0; 411 } 412 413 static const struct irq_domain_ops davinci_gpio_irq_ops = { 414 .map = davinci_gpio_irq_map, 415 .xlate = irq_domain_xlate_onetwocell, 416 }; 417 418 static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq) 419 { 420 static struct irq_chip_type gpio_unbanked; 421 422 gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq)); 423 424 return &gpio_unbanked.chip; 425 }; 426 427 static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq) 428 { 429 static struct irq_chip gpio_unbanked; 430 431 gpio_unbanked = *irq_get_chip(irq); 432 return &gpio_unbanked; 433 }; 434 435 static const struct of_device_id davinci_gpio_ids[]; 436 437 /* 438 * NOTE: for suspend/resume, probably best to make a platform_device with 439 * suspend_late/resume_resume calls hooking into results of the set_wake() 440 * calls ... so if no gpios are wakeup events the clock can be disabled, 441 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 442 * (dm6446) can be set appropriately for GPIOV33 pins. 443 */ 444 445 static int davinci_gpio_irq_setup(struct platform_device *pdev) 446 { 447 unsigned gpio, bank; 448 int irq; 449 struct clk *clk; 450 u32 binten = 0; 451 unsigned ngpio; 452 struct device *dev = &pdev->dev; 453 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); 454 struct davinci_gpio_regs __iomem *g; 455 struct irq_domain *irq_domain = NULL; 456 struct irq_chip *irq_chip; 457 struct davinci_gpio_irq_data *irqdata; 458 gpio_get_irq_chip_cb_t gpio_get_irq_chip; 459 460 /* 461 * Use davinci_gpio_get_irq_chip by default to handle non DT cases 462 */ 463 gpio_get_irq_chip = davinci_gpio_get_irq_chip; 464 if (dev->of_node) 465 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)device_get_match_data(dev); 466 467 ngpio = chips->chip.ngpio; 468 469 clk = devm_clk_get_enabled(dev, "gpio"); 470 if (IS_ERR(clk)) { 471 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk)); 472 return PTR_ERR(clk); 473 } 474 475 if (chips->gpio_unbanked) { 476 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0); 477 if (irq < 0) { 478 dev_err(dev, "Couldn't allocate IRQ numbers\n"); 479 return irq; 480 } 481 482 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0, 483 &davinci_gpio_irq_ops, 484 chips); 485 if (!irq_domain) { 486 dev_err(dev, "Couldn't register an IRQ domain\n"); 487 return -ENODEV; 488 } 489 } 490 491 /* 492 * Arrange gpiod_to_irq() support, handling either direct IRQs or 493 * banked IRQs. Having GPIOs in the first GPIO bank use direct 494 * IRQs, while the others use banked IRQs, would need some setup 495 * tweaks to recognize hardware which can do that. 496 */ 497 chips->chip.to_irq = gpio_to_irq_banked; 498 chips->irq_domain = irq_domain; 499 500 /* 501 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO 502 * controller only handling trigger modes. We currently assume no 503 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. 504 */ 505 if (chips->gpio_unbanked) { 506 /* pass "bank 0" GPIO IRQs to AINTC */ 507 chips->chip.to_irq = gpio_to_irq_unbanked; 508 509 binten = GENMASK(chips->gpio_unbanked / 16, 0); 510 511 /* AINTC handles mask/unmask; GPIO handles triggering */ 512 irq = chips->irqs[0]; 513 irq_chip = gpio_get_irq_chip(irq); 514 irq_chip->name = "GPIO-AINTC"; 515 irq_chip->irq_set_type = gpio_irq_type_unbanked; 516 517 /* default trigger: both edges */ 518 g = chips->regs[0]; 519 writel_relaxed(~0, &g->set_falling); 520 writel_relaxed(~0, &g->set_rising); 521 522 /* set the direct IRQs up to use that irqchip */ 523 for (gpio = 0; gpio < chips->gpio_unbanked; gpio++) { 524 irq_set_chip(chips->irqs[gpio], irq_chip); 525 irq_set_handler_data(chips->irqs[gpio], chips); 526 irq_set_status_flags(chips->irqs[gpio], 527 IRQ_TYPE_EDGE_BOTH); 528 } 529 530 goto done; 531 } 532 533 /* 534 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we 535 * then chain through our own handler. 536 */ 537 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) { 538 /* disabled by default, enabled only as needed 539 * There are register sets for 32 GPIOs. 2 banks of 16 540 * GPIOs are covered by each set of registers hence divide by 2 541 */ 542 g = chips->regs[bank / 2]; 543 writel_relaxed(~0, &g->clr_falling); 544 writel_relaxed(~0, &g->clr_rising); 545 546 /* 547 * Each chip handles 32 gpios, and each irq bank consists of 16 548 * gpio irqs. Pass the irq bank's corresponding controller to 549 * the chained irq handler. 550 */ 551 irqdata = devm_kzalloc(&pdev->dev, 552 sizeof(struct 553 davinci_gpio_irq_data), 554 GFP_KERNEL); 555 if (!irqdata) 556 return -ENOMEM; 557 558 irqdata->regs = g; 559 irqdata->bank_num = bank; 560 irqdata->chip = chips; 561 562 irq_set_chained_handler_and_data(chips->irqs[bank], 563 gpio_irq_handler, irqdata); 564 565 binten |= BIT(bank); 566 } 567 568 done: 569 /* 570 * BINTEN -- per-bank interrupt enable. genirq would also let these 571 * bits be set/cleared dynamically. 572 */ 573 writel_relaxed(binten, gpio_base + BINTEN); 574 575 return 0; 576 } 577 578 static void davinci_gpio_save_context(struct davinci_gpio_controller *chips, 579 u32 nbank) 580 { 581 struct davinci_gpio_regs __iomem *g; 582 struct davinci_gpio_regs *context; 583 u32 bank; 584 void __iomem *base; 585 586 base = chips->regs[0] - offset_array[0]; 587 chips->binten_context = readl_relaxed(base + BINTEN); 588 589 for (bank = 0; bank < nbank; bank++) { 590 g = chips->regs[bank]; 591 context = &chips->context[bank]; 592 context->dir = readl_relaxed(&g->dir); 593 context->set_data = readl_relaxed(&g->set_data); 594 context->set_rising = readl_relaxed(&g->set_rising); 595 context->set_falling = readl_relaxed(&g->set_falling); 596 } 597 598 /* Clear all interrupt status registers */ 599 writel_relaxed(GENMASK(31, 0), &g->intstat); 600 } 601 602 static void davinci_gpio_restore_context(struct davinci_gpio_controller *chips, 603 u32 nbank) 604 { 605 struct davinci_gpio_regs __iomem *g; 606 struct davinci_gpio_regs *context; 607 u32 bank; 608 void __iomem *base; 609 610 base = chips->regs[0] - offset_array[0]; 611 612 if (readl_relaxed(base + BINTEN) != chips->binten_context) 613 writel_relaxed(chips->binten_context, base + BINTEN); 614 615 for (bank = 0; bank < nbank; bank++) { 616 g = chips->regs[bank]; 617 context = &chips->context[bank]; 618 if (readl_relaxed(&g->dir) != context->dir) 619 writel_relaxed(context->dir, &g->dir); 620 if (readl_relaxed(&g->set_data) != context->set_data) 621 writel_relaxed(context->set_data, &g->set_data); 622 if (readl_relaxed(&g->set_rising) != context->set_rising) 623 writel_relaxed(context->set_rising, &g->set_rising); 624 if (readl_relaxed(&g->set_falling) != context->set_falling) 625 writel_relaxed(context->set_falling, &g->set_falling); 626 } 627 } 628 629 static int davinci_gpio_suspend(struct device *dev) 630 { 631 struct davinci_gpio_controller *chips = dev_get_drvdata(dev); 632 u32 nbank = DIV_ROUND_UP(chips->chip.ngpio, 32); 633 634 davinci_gpio_save_context(chips, nbank); 635 636 return 0; 637 } 638 639 static int davinci_gpio_resume(struct device *dev) 640 { 641 struct davinci_gpio_controller *chips = dev_get_drvdata(dev); 642 u32 nbank = DIV_ROUND_UP(chips->chip.ngpio, 32); 643 644 davinci_gpio_restore_context(chips, nbank); 645 646 return 0; 647 } 648 649 static DEFINE_SIMPLE_DEV_PM_OPS(davinci_gpio_dev_pm_ops, davinci_gpio_suspend, 650 davinci_gpio_resume); 651 652 static const struct of_device_id davinci_gpio_ids[] = { 653 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip}, 654 { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip}, 655 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip}, 656 { /* sentinel */ }, 657 }; 658 MODULE_DEVICE_TABLE(of, davinci_gpio_ids); 659 660 static struct platform_driver davinci_gpio_driver = { 661 .probe = davinci_gpio_probe, 662 .driver = { 663 .name = "davinci_gpio", 664 .pm = pm_sleep_ptr(&davinci_gpio_dev_pm_ops), 665 .of_match_table = of_match_ptr(davinci_gpio_ids), 666 }, 667 }; 668 669 /* 670 * GPIO driver registration needs to be done before machine_init functions 671 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall. 672 */ 673 static int __init davinci_gpio_drv_reg(void) 674 { 675 return platform_driver_register(&davinci_gpio_driver); 676 } 677 postcore_initcall(davinci_gpio_drv_reg); 678 679 static void __exit davinci_gpio_exit(void) 680 { 681 platform_driver_unregister(&davinci_gpio_driver); 682 } 683 module_exit(davinci_gpio_exit); 684 685 MODULE_AUTHOR("Jan Kotas <jank@cadence.com>"); 686 MODULE_DESCRIPTION("DAVINCI GPIO driver"); 687 MODULE_LICENSE("GPL"); 688 MODULE_ALIAS("platform:gpio-davinci"); 689