1 /* 2 * TI DaVinci GPIO Support 3 * 4 * Copyright (c) 2006-2007 David Brownell 5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 #include <linux/gpio.h> 13 #include <linux/errno.h> 14 #include <linux/kernel.h> 15 #include <linux/clk.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/irq.h> 19 #include <linux/irqdomain.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/platform_device.h> 24 #include <linux/platform_data/gpio-davinci.h> 25 #include <linux/irqchip/chained_irq.h> 26 27 struct davinci_gpio_regs { 28 u32 dir; 29 u32 out_data; 30 u32 set_data; 31 u32 clr_data; 32 u32 in_data; 33 u32 set_rising; 34 u32 clr_rising; 35 u32 set_falling; 36 u32 clr_falling; 37 u32 intstat; 38 }; 39 40 typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq); 41 42 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ 43 44 static void __iomem *gpio_base; 45 46 static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio) 47 { 48 void __iomem *ptr; 49 50 if (gpio < 32 * 1) 51 ptr = gpio_base + 0x10; 52 else if (gpio < 32 * 2) 53 ptr = gpio_base + 0x38; 54 else if (gpio < 32 * 3) 55 ptr = gpio_base + 0x60; 56 else if (gpio < 32 * 4) 57 ptr = gpio_base + 0x88; 58 else if (gpio < 32 * 5) 59 ptr = gpio_base + 0xb0; 60 else 61 ptr = NULL; 62 return ptr; 63 } 64 65 static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d) 66 { 67 struct davinci_gpio_regs __iomem *g; 68 69 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d); 70 71 return g; 72 } 73 74 static int davinci_gpio_irq_setup(struct platform_device *pdev); 75 76 /*--------------------------------------------------------------------------*/ 77 78 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ 79 static inline int __davinci_direction(struct gpio_chip *chip, 80 unsigned offset, bool out, int value) 81 { 82 struct davinci_gpio_controller *d = gpiochip_get_data(chip); 83 struct davinci_gpio_regs __iomem *g = d->regs; 84 unsigned long flags; 85 u32 temp; 86 u32 mask = 1 << offset; 87 88 spin_lock_irqsave(&d->lock, flags); 89 temp = readl_relaxed(&g->dir); 90 if (out) { 91 temp &= ~mask; 92 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); 93 } else { 94 temp |= mask; 95 } 96 writel_relaxed(temp, &g->dir); 97 spin_unlock_irqrestore(&d->lock, flags); 98 99 return 0; 100 } 101 102 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) 103 { 104 return __davinci_direction(chip, offset, false, 0); 105 } 106 107 static int 108 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) 109 { 110 return __davinci_direction(chip, offset, true, value); 111 } 112 113 /* 114 * Read the pin's value (works even if it's set up as output); 115 * returns zero/nonzero. 116 * 117 * Note that changes are synched to the GPIO clock, so reading values back 118 * right after you've set them may give old values. 119 */ 120 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) 121 { 122 struct davinci_gpio_controller *d = gpiochip_get_data(chip); 123 struct davinci_gpio_regs __iomem *g = d->regs; 124 125 return !!((1 << offset) & readl_relaxed(&g->in_data)); 126 } 127 128 /* 129 * Assuming the pin is muxed as a gpio output, set its output value. 130 */ 131 static void 132 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 133 { 134 struct davinci_gpio_controller *d = gpiochip_get_data(chip); 135 struct davinci_gpio_regs __iomem *g = d->regs; 136 137 writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data); 138 } 139 140 static struct davinci_gpio_platform_data * 141 davinci_gpio_get_pdata(struct platform_device *pdev) 142 { 143 struct device_node *dn = pdev->dev.of_node; 144 struct davinci_gpio_platform_data *pdata; 145 int ret; 146 u32 val; 147 148 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) 149 return dev_get_platdata(&pdev->dev); 150 151 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 152 if (!pdata) 153 return NULL; 154 155 ret = of_property_read_u32(dn, "ti,ngpio", &val); 156 if (ret) 157 goto of_err; 158 159 pdata->ngpio = val; 160 161 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val); 162 if (ret) 163 goto of_err; 164 165 pdata->gpio_unbanked = val; 166 167 return pdata; 168 169 of_err: 170 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret); 171 return NULL; 172 } 173 174 #ifdef CONFIG_OF_GPIO 175 static int davinci_gpio_of_xlate(struct gpio_chip *gc, 176 const struct of_phandle_args *gpiospec, 177 u32 *flags) 178 { 179 struct davinci_gpio_controller *chips = dev_get_drvdata(gc->parent); 180 struct davinci_gpio_platform_data *pdata = dev_get_platdata(gc->parent); 181 182 if (gpiospec->args[0] > pdata->ngpio) 183 return -EINVAL; 184 185 if (gc != &chips[gpiospec->args[0] / 32].chip) 186 return -EINVAL; 187 188 if (flags) 189 *flags = gpiospec->args[1]; 190 191 return gpiospec->args[0] % 32; 192 } 193 #endif 194 195 static int davinci_gpio_probe(struct platform_device *pdev) 196 { 197 int i, base; 198 unsigned ngpio; 199 struct davinci_gpio_controller *chips; 200 struct davinci_gpio_platform_data *pdata; 201 struct davinci_gpio_regs __iomem *regs; 202 struct device *dev = &pdev->dev; 203 struct resource *res; 204 205 pdata = davinci_gpio_get_pdata(pdev); 206 if (!pdata) { 207 dev_err(dev, "No platform data found\n"); 208 return -EINVAL; 209 } 210 211 dev->platform_data = pdata; 212 213 /* 214 * The gpio banks conceptually expose a segmented bitmap, 215 * and "ngpio" is one more than the largest zero-based 216 * bit index that's valid. 217 */ 218 ngpio = pdata->ngpio; 219 if (ngpio == 0) { 220 dev_err(dev, "How many GPIOs?\n"); 221 return -EINVAL; 222 } 223 224 if (WARN_ON(ARCH_NR_GPIOS < ngpio)) 225 ngpio = ARCH_NR_GPIOS; 226 227 chips = devm_kzalloc(dev, 228 ngpio * sizeof(struct davinci_gpio_controller), 229 GFP_KERNEL); 230 if (!chips) 231 return -ENOMEM; 232 233 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 234 gpio_base = devm_ioremap_resource(dev, res); 235 if (IS_ERR(gpio_base)) 236 return PTR_ERR(gpio_base); 237 238 for (i = 0, base = 0; base < ngpio; i++, base += 32) { 239 chips[i].chip.label = "DaVinci"; 240 241 chips[i].chip.direction_input = davinci_direction_in; 242 chips[i].chip.get = davinci_gpio_get; 243 chips[i].chip.direction_output = davinci_direction_out; 244 chips[i].chip.set = davinci_gpio_set; 245 246 chips[i].chip.base = base; 247 chips[i].chip.ngpio = ngpio - base; 248 if (chips[i].chip.ngpio > 32) 249 chips[i].chip.ngpio = 32; 250 251 #ifdef CONFIG_OF_GPIO 252 chips[i].chip.of_gpio_n_cells = 2; 253 chips[i].chip.of_xlate = davinci_gpio_of_xlate; 254 chips[i].chip.parent = dev; 255 chips[i].chip.of_node = dev->of_node; 256 #endif 257 spin_lock_init(&chips[i].lock); 258 259 regs = gpio2regs(base); 260 chips[i].regs = regs; 261 chips[i].set_data = ®s->set_data; 262 chips[i].clr_data = ®s->clr_data; 263 chips[i].in_data = ®s->in_data; 264 265 gpiochip_add_data(&chips[i].chip, &chips[i]); 266 } 267 268 platform_set_drvdata(pdev, chips); 269 davinci_gpio_irq_setup(pdev); 270 return 0; 271 } 272 273 /*--------------------------------------------------------------------------*/ 274 /* 275 * We expect irqs will normally be set up as input pins, but they can also be 276 * used as output pins ... which is convenient for testing. 277 * 278 * NOTE: The first few GPIOs also have direct INTC hookups in addition 279 * to their GPIOBNK0 irq, with a bit less overhead. 280 * 281 * All those INTC hookups (direct, plus several IRQ banks) can also 282 * serve as EDMA event triggers. 283 */ 284 285 static void gpio_irq_disable(struct irq_data *d) 286 { 287 struct davinci_gpio_regs __iomem *g = irq2regs(d); 288 u32 mask = (u32) irq_data_get_irq_handler_data(d); 289 290 writel_relaxed(mask, &g->clr_falling); 291 writel_relaxed(mask, &g->clr_rising); 292 } 293 294 static void gpio_irq_enable(struct irq_data *d) 295 { 296 struct davinci_gpio_regs __iomem *g = irq2regs(d); 297 u32 mask = (u32) irq_data_get_irq_handler_data(d); 298 unsigned status = irqd_get_trigger_type(d); 299 300 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; 301 if (!status) 302 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; 303 304 if (status & IRQ_TYPE_EDGE_FALLING) 305 writel_relaxed(mask, &g->set_falling); 306 if (status & IRQ_TYPE_EDGE_RISING) 307 writel_relaxed(mask, &g->set_rising); 308 } 309 310 static int gpio_irq_type(struct irq_data *d, unsigned trigger) 311 { 312 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 313 return -EINVAL; 314 315 return 0; 316 } 317 318 static struct irq_chip gpio_irqchip = { 319 .name = "GPIO", 320 .irq_enable = gpio_irq_enable, 321 .irq_disable = gpio_irq_disable, 322 .irq_set_type = gpio_irq_type, 323 .flags = IRQCHIP_SET_TYPE_MASKED, 324 }; 325 326 static void gpio_irq_handler(struct irq_desc *desc) 327 { 328 unsigned int irq = irq_desc_get_irq(desc); 329 struct davinci_gpio_regs __iomem *g; 330 u32 mask = 0xffff; 331 struct davinci_gpio_controller *d; 332 333 d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc); 334 g = (struct davinci_gpio_regs __iomem *)d->regs; 335 336 /* we only care about one bank */ 337 if (irq & 1) 338 mask <<= 16; 339 340 /* temporarily mask (level sensitive) parent IRQ */ 341 chained_irq_enter(irq_desc_get_chip(desc), desc); 342 while (1) { 343 u32 status; 344 int bit; 345 346 /* ack any irqs */ 347 status = readl_relaxed(&g->intstat) & mask; 348 if (!status) 349 break; 350 writel_relaxed(status, &g->intstat); 351 352 /* now demux them to the right lowlevel handler */ 353 354 while (status) { 355 bit = __ffs(status); 356 status &= ~BIT(bit); 357 generic_handle_irq( 358 irq_find_mapping(d->irq_domain, 359 d->chip.base + bit)); 360 } 361 } 362 chained_irq_exit(irq_desc_get_chip(desc), desc); 363 /* now it may re-trigger */ 364 } 365 366 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) 367 { 368 struct davinci_gpio_controller *d = gpiochip_get_data(chip); 369 370 if (d->irq_domain) 371 return irq_create_mapping(d->irq_domain, d->chip.base + offset); 372 else 373 return -ENXIO; 374 } 375 376 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) 377 { 378 struct davinci_gpio_controller *d = gpiochip_get_data(chip); 379 380 /* 381 * NOTE: we assume for now that only irqs in the first gpio_chip 382 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). 383 */ 384 if (offset < d->gpio_unbanked) 385 return d->gpio_irq + offset; 386 else 387 return -ENODEV; 388 } 389 390 static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) 391 { 392 struct davinci_gpio_controller *d; 393 struct davinci_gpio_regs __iomem *g; 394 u32 mask; 395 396 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data); 397 g = (struct davinci_gpio_regs __iomem *)d->regs; 398 mask = __gpio_mask(data->irq - d->gpio_irq); 399 400 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 401 return -EINVAL; 402 403 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) 404 ? &g->set_falling : &g->clr_falling); 405 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING) 406 ? &g->set_rising : &g->clr_rising); 407 408 return 0; 409 } 410 411 static int 412 davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, 413 irq_hw_number_t hw) 414 { 415 struct davinci_gpio_regs __iomem *g = gpio2regs(hw); 416 417 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, 418 "davinci_gpio"); 419 irq_set_irq_type(irq, IRQ_TYPE_NONE); 420 irq_set_chip_data(irq, (__force void *)g); 421 irq_set_handler_data(irq, (void *)__gpio_mask(hw)); 422 423 return 0; 424 } 425 426 static const struct irq_domain_ops davinci_gpio_irq_ops = { 427 .map = davinci_gpio_irq_map, 428 .xlate = irq_domain_xlate_onetwocell, 429 }; 430 431 static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq) 432 { 433 static struct irq_chip_type gpio_unbanked; 434 435 gpio_unbanked = *container_of(irq_get_chip(irq), 436 struct irq_chip_type, chip); 437 438 return &gpio_unbanked.chip; 439 }; 440 441 static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq) 442 { 443 static struct irq_chip gpio_unbanked; 444 445 gpio_unbanked = *irq_get_chip(irq); 446 return &gpio_unbanked; 447 }; 448 449 static const struct of_device_id davinci_gpio_ids[]; 450 451 /* 452 * NOTE: for suspend/resume, probably best to make a platform_device with 453 * suspend_late/resume_resume calls hooking into results of the set_wake() 454 * calls ... so if no gpios are wakeup events the clock can be disabled, 455 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 456 * (dm6446) can be set appropriately for GPIOV33 pins. 457 */ 458 459 static int davinci_gpio_irq_setup(struct platform_device *pdev) 460 { 461 unsigned gpio, bank; 462 int irq; 463 struct clk *clk; 464 u32 binten = 0; 465 unsigned ngpio, bank_irq; 466 struct device *dev = &pdev->dev; 467 struct resource *res; 468 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); 469 struct davinci_gpio_platform_data *pdata = dev->platform_data; 470 struct davinci_gpio_regs __iomem *g; 471 struct irq_domain *irq_domain = NULL; 472 const struct of_device_id *match; 473 struct irq_chip *irq_chip; 474 gpio_get_irq_chip_cb_t gpio_get_irq_chip; 475 476 /* 477 * Use davinci_gpio_get_irq_chip by default to handle non DT cases 478 */ 479 gpio_get_irq_chip = davinci_gpio_get_irq_chip; 480 match = of_match_device(of_match_ptr(davinci_gpio_ids), 481 dev); 482 if (match) 483 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data; 484 485 ngpio = pdata->ngpio; 486 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 487 if (!res) { 488 dev_err(dev, "Invalid IRQ resource\n"); 489 return -EBUSY; 490 } 491 492 bank_irq = res->start; 493 494 if (!bank_irq) { 495 dev_err(dev, "Invalid IRQ resource\n"); 496 return -ENODEV; 497 } 498 499 clk = devm_clk_get(dev, "gpio"); 500 if (IS_ERR(clk)) { 501 printk(KERN_ERR "Error %ld getting gpio clock?\n", 502 PTR_ERR(clk)); 503 return PTR_ERR(clk); 504 } 505 clk_prepare_enable(clk); 506 507 if (!pdata->gpio_unbanked) { 508 irq = irq_alloc_descs(-1, 0, ngpio, 0); 509 if (irq < 0) { 510 dev_err(dev, "Couldn't allocate IRQ numbers\n"); 511 return irq; 512 } 513 514 irq_domain = irq_domain_add_legacy(NULL, ngpio, irq, 0, 515 &davinci_gpio_irq_ops, 516 chips); 517 if (!irq_domain) { 518 dev_err(dev, "Couldn't register an IRQ domain\n"); 519 return -ENODEV; 520 } 521 } 522 523 /* 524 * Arrange gpio_to_irq() support, handling either direct IRQs or 525 * banked IRQs. Having GPIOs in the first GPIO bank use direct 526 * IRQs, while the others use banked IRQs, would need some setup 527 * tweaks to recognize hardware which can do that. 528 */ 529 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { 530 chips[bank].chip.to_irq = gpio_to_irq_banked; 531 chips[bank].irq_domain = irq_domain; 532 } 533 534 /* 535 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO 536 * controller only handling trigger modes. We currently assume no 537 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. 538 */ 539 if (pdata->gpio_unbanked) { 540 /* pass "bank 0" GPIO IRQs to AINTC */ 541 chips[0].chip.to_irq = gpio_to_irq_unbanked; 542 chips[0].gpio_irq = bank_irq; 543 chips[0].gpio_unbanked = pdata->gpio_unbanked; 544 binten = GENMASK(pdata->gpio_unbanked / 16, 0); 545 546 /* AINTC handles mask/unmask; GPIO handles triggering */ 547 irq = bank_irq; 548 irq_chip = gpio_get_irq_chip(irq); 549 irq_chip->name = "GPIO-AINTC"; 550 irq_chip->irq_set_type = gpio_irq_type_unbanked; 551 552 /* default trigger: both edges */ 553 g = gpio2regs(0); 554 writel_relaxed(~0, &g->set_falling); 555 writel_relaxed(~0, &g->set_rising); 556 557 /* set the direct IRQs up to use that irqchip */ 558 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) { 559 irq_set_chip(irq, irq_chip); 560 irq_set_handler_data(irq, &chips[gpio / 32]); 561 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); 562 } 563 564 goto done; 565 } 566 567 /* 568 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we 569 * then chain through our own handler. 570 */ 571 for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) { 572 /* disabled by default, enabled only as needed */ 573 g = gpio2regs(gpio); 574 writel_relaxed(~0, &g->clr_falling); 575 writel_relaxed(~0, &g->clr_rising); 576 577 /* 578 * Each chip handles 32 gpios, and each irq bank consists of 16 579 * gpio irqs. Pass the irq bank's corresponding controller to 580 * the chained irq handler. 581 */ 582 irq_set_chained_handler_and_data(bank_irq, gpio_irq_handler, 583 &chips[gpio / 32]); 584 585 binten |= BIT(bank); 586 } 587 588 done: 589 /* 590 * BINTEN -- per-bank interrupt enable. genirq would also let these 591 * bits be set/cleared dynamically. 592 */ 593 writel_relaxed(binten, gpio_base + BINTEN); 594 595 return 0; 596 } 597 598 #if IS_ENABLED(CONFIG_OF) 599 static const struct of_device_id davinci_gpio_ids[] = { 600 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip}, 601 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip}, 602 { /* sentinel */ }, 603 }; 604 MODULE_DEVICE_TABLE(of, davinci_gpio_ids); 605 #endif 606 607 static struct platform_driver davinci_gpio_driver = { 608 .probe = davinci_gpio_probe, 609 .driver = { 610 .name = "davinci_gpio", 611 .of_match_table = of_match_ptr(davinci_gpio_ids), 612 }, 613 }; 614 615 /** 616 * GPIO driver registration needs to be done before machine_init functions 617 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall. 618 */ 619 static int __init davinci_gpio_drv_reg(void) 620 { 621 return platform_driver_register(&davinci_gpio_driver); 622 } 623 postcore_initcall(davinci_gpio_drv_reg); 624