1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * TI DaVinci GPIO Support 4 * 5 * Copyright (c) 2006-2007 David Brownell 6 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> 7 */ 8 9 #include <linux/gpio/driver.h> 10 #include <linux/errno.h> 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/err.h> 14 #include <linux/io.h> 15 #include <linux/irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/module.h> 18 #include <linux/pinctrl/consumer.h> 19 #include <linux/platform_device.h> 20 #include <linux/property.h> 21 #include <linux/irqchip/chained_irq.h> 22 #include <linux/spinlock.h> 23 #include <linux/pm_runtime.h> 24 25 #define MAX_REGS_BANKS 5 26 #define MAX_INT_PER_BANK 32 27 28 struct davinci_gpio_regs { 29 u32 dir; 30 u32 out_data; 31 u32 set_data; 32 u32 clr_data; 33 u32 in_data; 34 u32 set_rising; 35 u32 clr_rising; 36 u32 set_falling; 37 u32 clr_falling; 38 u32 intstat; 39 }; 40 41 typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq); 42 43 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ 44 45 static void __iomem *gpio_base; 46 static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0}; 47 48 struct davinci_gpio_irq_data { 49 void __iomem *regs; 50 struct davinci_gpio_controller *chip; 51 int bank_num; 52 }; 53 54 struct davinci_gpio_controller { 55 struct gpio_chip chip; 56 struct irq_domain *irq_domain; 57 /* Serialize access to GPIO registers */ 58 spinlock_t lock; 59 void __iomem *regs[MAX_REGS_BANKS]; 60 int gpio_unbanked; 61 int irqs[MAX_INT_PER_BANK]; 62 struct davinci_gpio_regs context[MAX_REGS_BANKS]; 63 u32 binten_context; 64 }; 65 66 static inline u32 __gpio_mask(unsigned gpio) 67 { 68 return 1 << (gpio % 32); 69 } 70 71 static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d) 72 { 73 struct davinci_gpio_regs __iomem *g; 74 75 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d); 76 77 return g; 78 } 79 80 static int davinci_gpio_irq_setup(struct platform_device *pdev); 81 82 /*--------------------------------------------------------------------------*/ 83 84 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ 85 static inline int __davinci_direction(struct gpio_chip *chip, 86 unsigned offset, bool out, int value) 87 { 88 struct davinci_gpio_controller *d = gpiochip_get_data(chip); 89 struct davinci_gpio_regs __iomem *g; 90 unsigned long flags; 91 u32 temp; 92 int bank = offset / 32; 93 u32 mask = __gpio_mask(offset); 94 95 g = d->regs[bank]; 96 spin_lock_irqsave(&d->lock, flags); 97 temp = readl_relaxed(&g->dir); 98 if (out) { 99 temp &= ~mask; 100 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); 101 } else { 102 temp |= mask; 103 } 104 writel_relaxed(temp, &g->dir); 105 spin_unlock_irqrestore(&d->lock, flags); 106 107 return 0; 108 } 109 110 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) 111 { 112 return __davinci_direction(chip, offset, false, 0); 113 } 114 115 static int 116 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) 117 { 118 return __davinci_direction(chip, offset, true, value); 119 } 120 121 /* 122 * Read the pin's value (works even if it's set up as output); 123 * returns zero/nonzero. 124 * 125 * Note that changes are synched to the GPIO clock, so reading values back 126 * right after you've set them may give old values. 127 */ 128 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) 129 { 130 struct davinci_gpio_controller *d = gpiochip_get_data(chip); 131 struct davinci_gpio_regs __iomem *g; 132 int bank = offset / 32; 133 134 g = d->regs[bank]; 135 136 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data)); 137 } 138 139 /* 140 * Assuming the pin is muxed as a gpio output, set its output value. 141 */ 142 static void 143 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 144 { 145 struct davinci_gpio_controller *d = gpiochip_get_data(chip); 146 struct davinci_gpio_regs __iomem *g; 147 int bank = offset / 32; 148 149 g = d->regs[bank]; 150 151 writel_relaxed(__gpio_mask(offset), 152 value ? &g->set_data : &g->clr_data); 153 } 154 155 static int davinci_gpio_probe(struct platform_device *pdev) 156 { 157 int bank, i, ret = 0; 158 unsigned int ngpio, nbank, nirq, gpio_unbanked; 159 struct davinci_gpio_controller *chips; 160 struct device *dev = &pdev->dev; 161 162 /* 163 * The gpio banks conceptually expose a segmented bitmap, 164 * and "ngpio" is one more than the largest zero-based 165 * bit index that's valid. 166 */ 167 ret = device_property_read_u32(dev, "ti,ngpio", &ngpio); 168 if (ret) 169 return dev_err_probe(dev, ret, "Failed to get the number of GPIOs\n"); 170 if (ngpio == 0) 171 return dev_err_probe(dev, -EINVAL, "How many GPIOs?\n"); 172 173 /* 174 * If there are unbanked interrupts then the number of 175 * interrupts is equal to number of gpios else all are banked so 176 * number of interrupts is equal to number of banks(each with 16 gpios) 177 */ 178 ret = device_property_read_u32(dev, "ti,davinci-gpio-unbanked", 179 &gpio_unbanked); 180 if (ret) 181 return dev_err_probe(dev, ret, "Failed to get the unbanked GPIOs property\n"); 182 183 if (gpio_unbanked) 184 nirq = gpio_unbanked; 185 else 186 nirq = DIV_ROUND_UP(ngpio, 16); 187 188 if (nirq > MAX_INT_PER_BANK) { 189 dev_err(dev, "Too many IRQs!\n"); 190 return -EINVAL; 191 } 192 193 chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL); 194 if (!chips) 195 return -ENOMEM; 196 197 gpio_base = devm_platform_ioremap_resource(pdev, 0); 198 if (IS_ERR(gpio_base)) 199 return PTR_ERR(gpio_base); 200 201 for (i = 0; i < nirq; i++) { 202 chips->irqs[i] = platform_get_irq(pdev, i); 203 if (chips->irqs[i] < 0) 204 return chips->irqs[i]; 205 } 206 207 chips->chip.label = dev_name(dev); 208 209 chips->chip.direction_input = davinci_direction_in; 210 chips->chip.get = davinci_gpio_get; 211 chips->chip.direction_output = davinci_direction_out; 212 chips->chip.set = davinci_gpio_set; 213 214 chips->chip.ngpio = ngpio; 215 chips->chip.base = -1; 216 217 #ifdef CONFIG_OF_GPIO 218 chips->chip.parent = dev; 219 chips->chip.request = gpiochip_generic_request; 220 chips->chip.free = gpiochip_generic_free; 221 #endif 222 spin_lock_init(&chips->lock); 223 224 chips->gpio_unbanked = gpio_unbanked; 225 226 nbank = DIV_ROUND_UP(ngpio, 32); 227 for (bank = 0; bank < nbank; bank++) 228 chips->regs[bank] = gpio_base + offset_array[bank]; 229 230 ret = devm_gpiochip_add_data(dev, &chips->chip, chips); 231 if (ret) 232 return ret; 233 234 platform_set_drvdata(pdev, chips); 235 ret = davinci_gpio_irq_setup(pdev); 236 if (ret) 237 return ret; 238 239 return 0; 240 } 241 242 /*--------------------------------------------------------------------------*/ 243 /* 244 * We expect irqs will normally be set up as input pins, but they can also be 245 * used as output pins ... which is convenient for testing. 246 * 247 * NOTE: The first few GPIOs also have direct INTC hookups in addition 248 * to their GPIOBNK0 irq, with a bit less overhead. 249 * 250 * All those INTC hookups (direct, plus several IRQ banks) can also 251 * serve as EDMA event triggers. 252 */ 253 254 static void gpio_irq_mask(struct irq_data *d) 255 { 256 struct davinci_gpio_regs __iomem *g = irq2regs(d); 257 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d); 258 259 writel_relaxed(mask, &g->clr_falling); 260 writel_relaxed(mask, &g->clr_rising); 261 } 262 263 static void gpio_irq_unmask(struct irq_data *d) 264 { 265 struct davinci_gpio_regs __iomem *g = irq2regs(d); 266 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d); 267 unsigned status = irqd_get_trigger_type(d); 268 269 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; 270 if (!status) 271 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; 272 273 if (status & IRQ_TYPE_EDGE_FALLING) 274 writel_relaxed(mask, &g->set_falling); 275 if (status & IRQ_TYPE_EDGE_RISING) 276 writel_relaxed(mask, &g->set_rising); 277 } 278 279 static int gpio_irq_type(struct irq_data *d, unsigned trigger) 280 { 281 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 282 return -EINVAL; 283 284 return 0; 285 } 286 287 static struct irq_chip gpio_irqchip = { 288 .name = "GPIO", 289 .irq_unmask = gpio_irq_unmask, 290 .irq_mask = gpio_irq_mask, 291 .irq_set_type = gpio_irq_type, 292 .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_SKIP_SET_WAKE, 293 }; 294 295 static void gpio_irq_handler(struct irq_desc *desc) 296 { 297 struct davinci_gpio_regs __iomem *g; 298 u32 mask = 0xffff; 299 int bank_num; 300 struct davinci_gpio_controller *d; 301 struct davinci_gpio_irq_data *irqdata; 302 303 irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc); 304 bank_num = irqdata->bank_num; 305 g = irqdata->regs; 306 d = irqdata->chip; 307 308 /* we only care about one bank */ 309 if ((bank_num % 2) == 1) 310 mask <<= 16; 311 312 /* temporarily mask (level sensitive) parent IRQ */ 313 chained_irq_enter(irq_desc_get_chip(desc), desc); 314 while (1) { 315 u32 status; 316 int bit; 317 irq_hw_number_t hw_irq; 318 319 /* ack any irqs */ 320 status = readl_relaxed(&g->intstat) & mask; 321 if (!status) 322 break; 323 writel_relaxed(status, &g->intstat); 324 325 /* now demux them to the right lowlevel handler */ 326 327 while (status) { 328 bit = __ffs(status); 329 status &= ~BIT(bit); 330 /* Max number of gpios per controller is 144 so 331 * hw_irq will be in [0..143] 332 */ 333 hw_irq = (bank_num / 2) * 32 + bit; 334 335 generic_handle_domain_irq(d->irq_domain, hw_irq); 336 } 337 } 338 chained_irq_exit(irq_desc_get_chip(desc), desc); 339 /* now it may re-trigger */ 340 } 341 342 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) 343 { 344 struct davinci_gpio_controller *d = gpiochip_get_data(chip); 345 346 if (d->irq_domain) 347 return irq_create_mapping(d->irq_domain, offset); 348 else 349 return -ENXIO; 350 } 351 352 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) 353 { 354 struct davinci_gpio_controller *d = gpiochip_get_data(chip); 355 356 /* 357 * NOTE: we assume for now that only irqs in the first gpio_chip 358 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). 359 */ 360 if (offset < d->gpio_unbanked) 361 return d->irqs[offset]; 362 else 363 return -ENODEV; 364 } 365 366 static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) 367 { 368 struct davinci_gpio_controller *d; 369 struct davinci_gpio_regs __iomem *g; 370 u32 mask, i; 371 372 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data); 373 g = (struct davinci_gpio_regs __iomem *)d->regs[0]; 374 for (i = 0; i < MAX_INT_PER_BANK; i++) 375 if (data->irq == d->irqs[i]) 376 break; 377 378 if (i == MAX_INT_PER_BANK) 379 return -EINVAL; 380 381 mask = __gpio_mask(i); 382 383 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 384 return -EINVAL; 385 386 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) 387 ? &g->set_falling : &g->clr_falling); 388 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING) 389 ? &g->set_rising : &g->clr_rising); 390 391 return 0; 392 } 393 394 static int 395 davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, 396 irq_hw_number_t hw) 397 { 398 struct davinci_gpio_controller *chips = 399 (struct davinci_gpio_controller *)d->host_data; 400 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32]; 401 402 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, 403 "davinci_gpio"); 404 irq_set_irq_type(irq, IRQ_TYPE_NONE); 405 irq_set_chip_data(irq, (__force void *)g); 406 irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw)); 407 408 return 0; 409 } 410 411 static const struct irq_domain_ops davinci_gpio_irq_ops = { 412 .map = davinci_gpio_irq_map, 413 .xlate = irq_domain_xlate_onetwocell, 414 }; 415 416 static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq) 417 { 418 static struct irq_chip_type gpio_unbanked; 419 420 gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq)); 421 422 return &gpio_unbanked.chip; 423 }; 424 425 static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq) 426 { 427 static struct irq_chip gpio_unbanked; 428 429 gpio_unbanked = *irq_get_chip(irq); 430 return &gpio_unbanked; 431 }; 432 433 static const struct of_device_id davinci_gpio_ids[]; 434 435 /* 436 * NOTE: for suspend/resume, probably best to make a platform_device with 437 * suspend_late/resume_resume calls hooking into results of the set_wake() 438 * calls ... so if no gpios are wakeup events the clock can be disabled, 439 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 440 * (dm6446) can be set appropriately for GPIOV33 pins. 441 */ 442 443 static int davinci_gpio_irq_setup(struct platform_device *pdev) 444 { 445 unsigned gpio, bank; 446 int irq; 447 struct clk *clk; 448 u32 binten = 0; 449 unsigned ngpio; 450 struct device *dev = &pdev->dev; 451 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); 452 struct davinci_gpio_regs __iomem *g; 453 struct irq_domain *irq_domain = NULL; 454 struct irq_chip *irq_chip; 455 struct davinci_gpio_irq_data *irqdata; 456 gpio_get_irq_chip_cb_t gpio_get_irq_chip; 457 458 /* 459 * Use davinci_gpio_get_irq_chip by default to handle non DT cases 460 */ 461 gpio_get_irq_chip = davinci_gpio_get_irq_chip; 462 if (dev->of_node) 463 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)device_get_match_data(dev); 464 465 ngpio = chips->chip.ngpio; 466 467 clk = devm_clk_get_enabled(dev, "gpio"); 468 if (IS_ERR(clk)) { 469 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk)); 470 return PTR_ERR(clk); 471 } 472 473 if (!chips->gpio_unbanked) { 474 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0); 475 if (irq < 0) { 476 dev_err(dev, "Couldn't allocate IRQ numbers\n"); 477 return irq; 478 } 479 480 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0, 481 &davinci_gpio_irq_ops, 482 chips); 483 if (!irq_domain) { 484 dev_err(dev, "Couldn't register an IRQ domain\n"); 485 return -ENODEV; 486 } 487 } 488 489 /* 490 * Arrange gpiod_to_irq() support, handling either direct IRQs or 491 * banked IRQs. Having GPIOs in the first GPIO bank use direct 492 * IRQs, while the others use banked IRQs, would need some setup 493 * tweaks to recognize hardware which can do that. 494 */ 495 chips->chip.to_irq = gpio_to_irq_banked; 496 chips->irq_domain = irq_domain; 497 498 /* 499 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO 500 * controller only handling trigger modes. We currently assume no 501 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. 502 */ 503 if (chips->gpio_unbanked) { 504 /* pass "bank 0" GPIO IRQs to AINTC */ 505 chips->chip.to_irq = gpio_to_irq_unbanked; 506 507 binten = GENMASK(chips->gpio_unbanked / 16, 0); 508 509 /* AINTC handles mask/unmask; GPIO handles triggering */ 510 irq = chips->irqs[0]; 511 irq_chip = gpio_get_irq_chip(irq); 512 irq_chip->name = "GPIO-AINTC"; 513 irq_chip->irq_set_type = gpio_irq_type_unbanked; 514 515 /* default trigger: both edges */ 516 g = chips->regs[0]; 517 writel_relaxed(~0, &g->set_falling); 518 writel_relaxed(~0, &g->set_rising); 519 520 /* set the direct IRQs up to use that irqchip */ 521 for (gpio = 0; gpio < chips->gpio_unbanked; gpio++) { 522 irq_set_chip(chips->irqs[gpio], irq_chip); 523 irq_set_handler_data(chips->irqs[gpio], chips); 524 irq_set_status_flags(chips->irqs[gpio], 525 IRQ_TYPE_EDGE_BOTH); 526 } 527 528 goto done; 529 } 530 531 /* 532 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we 533 * then chain through our own handler. 534 */ 535 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) { 536 /* disabled by default, enabled only as needed 537 * There are register sets for 32 GPIOs. 2 banks of 16 538 * GPIOs are covered by each set of registers hence divide by 2 539 */ 540 g = chips->regs[bank / 2]; 541 writel_relaxed(~0, &g->clr_falling); 542 writel_relaxed(~0, &g->clr_rising); 543 544 /* 545 * Each chip handles 32 gpios, and each irq bank consists of 16 546 * gpio irqs. Pass the irq bank's corresponding controller to 547 * the chained irq handler. 548 */ 549 irqdata = devm_kzalloc(&pdev->dev, 550 sizeof(struct 551 davinci_gpio_irq_data), 552 GFP_KERNEL); 553 if (!irqdata) 554 return -ENOMEM; 555 556 irqdata->regs = g; 557 irqdata->bank_num = bank; 558 irqdata->chip = chips; 559 560 irq_set_chained_handler_and_data(chips->irqs[bank], 561 gpio_irq_handler, irqdata); 562 563 binten |= BIT(bank); 564 } 565 566 done: 567 /* 568 * BINTEN -- per-bank interrupt enable. genirq would also let these 569 * bits be set/cleared dynamically. 570 */ 571 writel_relaxed(binten, gpio_base + BINTEN); 572 573 return 0; 574 } 575 576 static void davinci_gpio_save_context(struct davinci_gpio_controller *chips, 577 u32 nbank) 578 { 579 struct davinci_gpio_regs __iomem *g; 580 struct davinci_gpio_regs *context; 581 u32 bank; 582 void __iomem *base; 583 584 base = chips->regs[0] - offset_array[0]; 585 chips->binten_context = readl_relaxed(base + BINTEN); 586 587 for (bank = 0; bank < nbank; bank++) { 588 g = chips->regs[bank]; 589 context = &chips->context[bank]; 590 context->dir = readl_relaxed(&g->dir); 591 context->set_data = readl_relaxed(&g->set_data); 592 context->set_rising = readl_relaxed(&g->set_rising); 593 context->set_falling = readl_relaxed(&g->set_falling); 594 } 595 596 /* Clear all interrupt status registers */ 597 writel_relaxed(GENMASK(31, 0), &g->intstat); 598 } 599 600 static void davinci_gpio_restore_context(struct davinci_gpio_controller *chips, 601 u32 nbank) 602 { 603 struct davinci_gpio_regs __iomem *g; 604 struct davinci_gpio_regs *context; 605 u32 bank; 606 void __iomem *base; 607 608 base = chips->regs[0] - offset_array[0]; 609 610 if (readl_relaxed(base + BINTEN) != chips->binten_context) 611 writel_relaxed(chips->binten_context, base + BINTEN); 612 613 for (bank = 0; bank < nbank; bank++) { 614 g = chips->regs[bank]; 615 context = &chips->context[bank]; 616 if (readl_relaxed(&g->dir) != context->dir) 617 writel_relaxed(context->dir, &g->dir); 618 if (readl_relaxed(&g->set_data) != context->set_data) 619 writel_relaxed(context->set_data, &g->set_data); 620 if (readl_relaxed(&g->set_rising) != context->set_rising) 621 writel_relaxed(context->set_rising, &g->set_rising); 622 if (readl_relaxed(&g->set_falling) != context->set_falling) 623 writel_relaxed(context->set_falling, &g->set_falling); 624 } 625 } 626 627 static int davinci_gpio_suspend(struct device *dev) 628 { 629 struct davinci_gpio_controller *chips = dev_get_drvdata(dev); 630 u32 nbank = DIV_ROUND_UP(chips->chip.ngpio, 32); 631 632 davinci_gpio_save_context(chips, nbank); 633 634 return 0; 635 } 636 637 static int davinci_gpio_resume(struct device *dev) 638 { 639 struct davinci_gpio_controller *chips = dev_get_drvdata(dev); 640 u32 nbank = DIV_ROUND_UP(chips->chip.ngpio, 32); 641 642 davinci_gpio_restore_context(chips, nbank); 643 644 return 0; 645 } 646 647 static DEFINE_SIMPLE_DEV_PM_OPS(davinci_gpio_dev_pm_ops, davinci_gpio_suspend, 648 davinci_gpio_resume); 649 650 static const struct of_device_id davinci_gpio_ids[] = { 651 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip}, 652 { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip}, 653 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip}, 654 { /* sentinel */ }, 655 }; 656 MODULE_DEVICE_TABLE(of, davinci_gpio_ids); 657 658 static struct platform_driver davinci_gpio_driver = { 659 .probe = davinci_gpio_probe, 660 .driver = { 661 .name = "davinci_gpio", 662 .pm = pm_sleep_ptr(&davinci_gpio_dev_pm_ops), 663 .of_match_table = davinci_gpio_ids, 664 }, 665 }; 666 667 /* 668 * GPIO driver registration needs to be done before machine_init functions 669 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall. 670 */ 671 static int __init davinci_gpio_drv_reg(void) 672 { 673 return platform_driver_register(&davinci_gpio_driver); 674 } 675 postcore_initcall(davinci_gpio_drv_reg); 676 677 static void __exit davinci_gpio_exit(void) 678 { 679 platform_driver_unregister(&davinci_gpio_driver); 680 } 681 module_exit(davinci_gpio_exit); 682 683 MODULE_AUTHOR("Jan Kotas <jank@cadence.com>"); 684 MODULE_DESCRIPTION("DAVINCI GPIO driver"); 685 MODULE_LICENSE("GPL"); 686 MODULE_ALIAS("platform:gpio-davinci"); 687