xref: /linux/drivers/gpio/gpio-crystalcove.c (revision 7a9b709e7cc5ce1ffb84ce07bf6d157e1de758df) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Intel Crystal Cove GPIO Driver
4  *
5  * Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
6  *
7  * Author: Yang, Bin <bin.yang@intel.com>
8  */
9 
10 #include <linux/bitops.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/interrupt.h>
13 #include <linux/mfd/intel_soc_pmic.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17 #include <linux/seq_file.h>
18 #include <linux/string_choices.h>
19 #include <linux/types.h>
20 
21 #define CRYSTALCOVE_GPIO_NUM	16
22 #define CRYSTALCOVE_VGPIO_NUM	95
23 
24 #define UPDATE_IRQ_TYPE		BIT(0)
25 #define UPDATE_IRQ_MASK		BIT(1)
26 
27 #define GPIO0IRQ		0x0b
28 #define GPIO1IRQ		0x0c
29 #define MGPIO0IRQS0		0x19
30 #define MGPIO1IRQS0		0x1a
31 #define MGPIO0IRQSX		0x1b
32 #define MGPIO1IRQSX		0x1c
33 #define GPIO0P0CTLO		0x2b
34 #define GPIO0P0CTLI		0x33
35 #define GPIO1P0CTLO		0x3b
36 #define GPIO1P0CTLI		0x43
37 #define GPIOPANELCTL		0x52
38 
39 #define CTLI_INTCNT_DIS		(0)
40 #define CTLI_INTCNT_NE		(1 << 1)
41 #define CTLI_INTCNT_PE		(2 << 1)
42 #define CTLI_INTCNT_BE		(3 << 1)
43 
44 #define CTLO_DIR_IN		(0)
45 #define CTLO_DIR_OUT		(1 << 5)
46 
47 #define CTLO_DRV_CMOS		(0)
48 #define CTLO_DRV_OD		(1 << 4)
49 
50 #define CTLO_DRV_REN		(1 << 3)
51 
52 #define CTLO_RVAL_2KDW		(0)
53 #define CTLO_RVAL_2KUP		(1 << 1)
54 #define CTLO_RVAL_50KDW		(2 << 1)
55 #define CTLO_RVAL_50KUP		(3 << 1)
56 
57 #define CTLO_INPUT_SET	(CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
58 #define CTLO_OUTPUT_SET	(CTLO_DIR_OUT | CTLO_INPUT_SET)
59 
60 enum ctrl_register {
61 	CTRL_IN,
62 	CTRL_OUT,
63 };
64 
65 /**
66  * struct crystalcove_gpio - Crystal Cove GPIO controller
67  * @buslock: for bus lock/sync and unlock.
68  * @chip: the abstract gpio_chip structure.
69  * @regmap: the regmap from the parent device.
70  * @update: pending IRQ setting update, to be written to the chip upon unlock.
71  * @intcnt_value: the Interrupt Detect value to be written.
72  * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
73  */
74 struct crystalcove_gpio {
75 	struct mutex buslock; /* irq_bus_lock */
76 	struct gpio_chip chip;
77 	struct regmap *regmap;
78 	int update;
79 	int intcnt_value;
80 	bool set_irq_mask;
81 };
82 
83 static inline int to_reg(int gpio, enum ctrl_register reg_type)
84 {
85 	int reg;
86 
87 	if (gpio >= CRYSTALCOVE_GPIO_NUM) {
88 		/*
89 		 * Virtual GPIO called from ACPI, for now we only support
90 		 * the panel ctl.
91 		 */
92 		switch (gpio) {
93 		case 0x5e:
94 			return GPIOPANELCTL;
95 		default:
96 			return -ENOTSUPP;
97 		}
98 	}
99 
100 	if (reg_type == CTRL_IN) {
101 		if (gpio < 8)
102 			reg = GPIO0P0CTLI;
103 		else
104 			reg = GPIO1P0CTLI;
105 	} else {
106 		if (gpio < 8)
107 			reg = GPIO0P0CTLO;
108 		else
109 			reg = GPIO1P0CTLO;
110 	}
111 
112 	return reg + gpio % 8;
113 }
114 
115 static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg, int gpio)
116 {
117 	u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
118 	int mask = BIT(gpio % 8);
119 
120 	if (cg->set_irq_mask)
121 		regmap_update_bits(cg->regmap, mirqs0, mask, mask);
122 	else
123 		regmap_update_bits(cg->regmap, mirqs0, mask, 0);
124 }
125 
126 static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
127 {
128 	int reg = to_reg(gpio, CTRL_IN);
129 
130 	regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
131 }
132 
133 static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
134 {
135 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
136 	int reg = to_reg(gpio, CTRL_OUT);
137 
138 	if (reg < 0)
139 		return 0;
140 
141 	return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);
142 }
143 
144 static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, int value)
145 {
146 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
147 	int reg = to_reg(gpio, CTRL_OUT);
148 
149 	if (reg < 0)
150 		return 0;
151 
152 	return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value);
153 }
154 
155 static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
156 {
157 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
158 	unsigned int val;
159 	int ret, reg = to_reg(gpio, CTRL_IN);
160 
161 	if (reg < 0)
162 		return 0;
163 
164 	ret = regmap_read(cg->regmap, reg, &val);
165 	if (ret)
166 		return ret;
167 
168 	return val & 0x1;
169 }
170 
171 static int crystalcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
172 {
173 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
174 	int reg = to_reg(gpio, CTRL_OUT);
175 
176 	if (reg < 0)
177 		return 0;
178 
179 	if (value)
180 		return regmap_update_bits(cg->regmap, reg, 1, 1);
181 
182 	return regmap_update_bits(cg->regmap, reg, 1, 0);
183 }
184 
185 static int crystalcove_irq_type(struct irq_data *data, unsigned int type)
186 {
187 	struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
188 	irq_hw_number_t hwirq = irqd_to_hwirq(data);
189 
190 	if (hwirq >= CRYSTALCOVE_GPIO_NUM)
191 		return 0;
192 
193 	switch (type) {
194 	case IRQ_TYPE_NONE:
195 		cg->intcnt_value = CTLI_INTCNT_DIS;
196 		break;
197 	case IRQ_TYPE_EDGE_BOTH:
198 		cg->intcnt_value = CTLI_INTCNT_BE;
199 		break;
200 	case IRQ_TYPE_EDGE_RISING:
201 		cg->intcnt_value = CTLI_INTCNT_PE;
202 		break;
203 	case IRQ_TYPE_EDGE_FALLING:
204 		cg->intcnt_value = CTLI_INTCNT_NE;
205 		break;
206 	default:
207 		return -EINVAL;
208 	}
209 
210 	cg->update |= UPDATE_IRQ_TYPE;
211 
212 	return 0;
213 }
214 
215 static void crystalcove_bus_lock(struct irq_data *data)
216 {
217 	struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
218 
219 	mutex_lock(&cg->buslock);
220 }
221 
222 static void crystalcove_bus_sync_unlock(struct irq_data *data)
223 {
224 	struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
225 	irq_hw_number_t hwirq = irqd_to_hwirq(data);
226 
227 	if (cg->update & UPDATE_IRQ_TYPE)
228 		crystalcove_update_irq_ctrl(cg, hwirq);
229 	if (cg->update & UPDATE_IRQ_MASK)
230 		crystalcove_update_irq_mask(cg, hwirq);
231 	cg->update = 0;
232 
233 	mutex_unlock(&cg->buslock);
234 }
235 
236 static void crystalcove_irq_unmask(struct irq_data *data)
237 {
238 	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
239 	struct crystalcove_gpio *cg = gpiochip_get_data(gc);
240 	irq_hw_number_t hwirq = irqd_to_hwirq(data);
241 
242 	if (hwirq >= CRYSTALCOVE_GPIO_NUM)
243 		return;
244 
245 	gpiochip_enable_irq(gc, hwirq);
246 
247 	cg->set_irq_mask = false;
248 	cg->update |= UPDATE_IRQ_MASK;
249 }
250 
251 static void crystalcove_irq_mask(struct irq_data *data)
252 {
253 	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
254 	struct crystalcove_gpio *cg = gpiochip_get_data(gc);
255 	irq_hw_number_t hwirq = irqd_to_hwirq(data);
256 
257 	if (hwirq >= CRYSTALCOVE_GPIO_NUM)
258 		return;
259 
260 	cg->set_irq_mask = true;
261 	cg->update |= UPDATE_IRQ_MASK;
262 
263 	gpiochip_disable_irq(gc, hwirq);
264 }
265 
266 static const struct irq_chip crystalcove_irqchip = {
267 	.name			= "Crystal Cove",
268 	.irq_mask		= crystalcove_irq_mask,
269 	.irq_unmask		= crystalcove_irq_unmask,
270 	.irq_set_type		= crystalcove_irq_type,
271 	.irq_bus_lock		= crystalcove_bus_lock,
272 	.irq_bus_sync_unlock	= crystalcove_bus_sync_unlock,
273 	.flags			= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
274 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
275 };
276 
277 static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
278 {
279 	struct crystalcove_gpio *cg = data;
280 	unsigned long pending;
281 	unsigned int p0, p1;
282 	int gpio;
283 	unsigned int virq;
284 
285 	if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||
286 	    regmap_read(cg->regmap, GPIO1IRQ, &p1))
287 		return IRQ_NONE;
288 
289 	regmap_write(cg->regmap, GPIO0IRQ, p0);
290 	regmap_write(cg->regmap, GPIO1IRQ, p1);
291 
292 	pending = p0 | p1 << 8;
293 
294 	for_each_set_bit(gpio, &pending, CRYSTALCOVE_GPIO_NUM) {
295 		virq = irq_find_mapping(cg->chip.irq.domain, gpio);
296 		handle_nested_irq(virq);
297 	}
298 
299 	return IRQ_HANDLED;
300 }
301 
302 static void crystalcove_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
303 {
304 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
305 	int gpio, offset;
306 	unsigned int ctlo, ctli, mirqs0, mirqsx, irq;
307 
308 	for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
309 		regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
310 		regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
311 		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
312 			    &mirqs0);
313 		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
314 			    &mirqsx);
315 		regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
316 			    &irq);
317 
318 		offset = gpio % 8;
319 		seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
320 			   gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
321 			   str_hi_lo(ctli & 0x1),
322 			   ctli & CTLI_INTCNT_NE ? "fall" : "    ",
323 			   ctli & CTLI_INTCNT_PE ? "rise" : "    ",
324 			   ctlo,
325 			   mirqs0 & BIT(offset) ? "s0 mask  " : "s0 unmask",
326 			   mirqsx & BIT(offset) ? "sx mask  " : "sx unmask",
327 			   irq & BIT(offset) ? "pending" : "       ");
328 	}
329 }
330 
331 static int crystalcove_gpio_probe(struct platform_device *pdev)
332 {
333 	int irq = platform_get_irq(pdev, 0);
334 	struct crystalcove_gpio *cg;
335 	int retval;
336 	struct device *dev = pdev->dev.parent;
337 	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
338 	struct gpio_irq_chip *girq;
339 
340 	if (irq < 0)
341 		return irq;
342 
343 	cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
344 	if (!cg)
345 		return -ENOMEM;
346 
347 	mutex_init(&cg->buslock);
348 	cg->chip.label = KBUILD_MODNAME;
349 	cg->chip.direction_input = crystalcove_gpio_dir_in;
350 	cg->chip.direction_output = crystalcove_gpio_dir_out;
351 	cg->chip.get = crystalcove_gpio_get;
352 	cg->chip.set_rv = crystalcove_gpio_set;
353 	cg->chip.base = -1;
354 	cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;
355 	cg->chip.can_sleep = true;
356 	cg->chip.parent = dev;
357 	cg->chip.dbg_show = crystalcove_gpio_dbg_show;
358 	cg->regmap = pmic->regmap;
359 
360 	girq = &cg->chip.irq;
361 	gpio_irq_chip_set_chip(girq, &crystalcove_irqchip);
362 	/* This will let us handle the parent IRQ in the driver */
363 	girq->parent_handler = NULL;
364 	girq->num_parents = 0;
365 	girq->parents = NULL;
366 	girq->default_type = IRQ_TYPE_NONE;
367 	girq->handler = handle_simple_irq;
368 	girq->threaded = true;
369 
370 	retval = devm_request_threaded_irq(&pdev->dev, irq, NULL,
371 					   crystalcove_gpio_irq_handler,
372 					   IRQF_ONESHOT, KBUILD_MODNAME, cg);
373 	if (retval) {
374 		dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
375 		return retval;
376 	}
377 
378 	retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg);
379 	if (retval)
380 		return retval;
381 
382 	/* Distuingish IRQ domain from others sharing (MFD) the same fwnode */
383 	irq_domain_update_bus_token(cg->chip.irq.domain, DOMAIN_BUS_WIRED);
384 
385 	return 0;
386 }
387 
388 static struct platform_driver crystalcove_gpio_driver = {
389 	.probe = crystalcove_gpio_probe,
390 	.driver = {
391 		.name = "crystal_cove_gpio",
392 	},
393 };
394 module_platform_driver(crystalcove_gpio_driver);
395 
396 MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
397 MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver");
398 MODULE_LICENSE("GPL v2");
399