1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (C) 2015-2017 Broadcom 3 4 #include <linux/bitops.h> 5 #include <linux/gpio/driver.h> 6 #include <linux/of.h> 7 #include <linux/module.h> 8 #include <linux/irqdomain.h> 9 #include <linux/irqchip/chained_irq.h> 10 #include <linux/interrupt.h> 11 #include <linux/platform_device.h> 12 13 enum gio_reg_index { 14 GIO_REG_ODEN = 0, 15 GIO_REG_DATA, 16 GIO_REG_IODIR, 17 GIO_REG_EC, 18 GIO_REG_EI, 19 GIO_REG_MASK, 20 GIO_REG_LEVEL, 21 GIO_REG_STAT, 22 NUMBER_OF_GIO_REGISTERS 23 }; 24 25 #define GIO_BANK_SIZE (NUMBER_OF_GIO_REGISTERS * sizeof(u32)) 26 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) 27 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) 28 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) 29 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) 30 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) 31 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) 32 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) 33 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) 34 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT) 35 36 struct brcmstb_gpio_bank { 37 struct list_head node; 38 int id; 39 struct gpio_chip gc; 40 struct brcmstb_gpio_priv *parent_priv; 41 u32 width; 42 u32 wake_active; 43 u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */ 44 }; 45 46 struct brcmstb_gpio_priv { 47 struct list_head bank_list; 48 void __iomem *reg_base; 49 struct platform_device *pdev; 50 struct irq_domain *irq_domain; 51 struct irq_chip irq_chip; 52 int parent_irq; 53 int gpio_base; 54 int num_gpios; 55 int parent_wake_irq; 56 }; 57 58 #define MAX_GPIO_PER_BANK 32 59 #define GPIO_BANK(gpio) ((gpio) >> 5) 60 /* assumes MAX_GPIO_PER_BANK is a multiple of 2 */ 61 #define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1)) 62 63 static inline struct brcmstb_gpio_priv * 64 brcmstb_gpio_gc_to_priv(struct gpio_chip *gc) 65 { 66 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 67 return bank->parent_priv; 68 } 69 70 static unsigned long 71 __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank) 72 { 73 void __iomem *reg_base = bank->parent_priv->reg_base; 74 75 return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) & 76 bank->gc.read_reg(reg_base + GIO_MASK(bank->id)); 77 } 78 79 static unsigned long 80 brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank) 81 { 82 unsigned long status; 83 unsigned long flags; 84 85 raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags); 86 status = __brcmstb_gpio_get_active_irqs(bank); 87 raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); 88 89 return status; 90 } 91 92 static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq, 93 struct brcmstb_gpio_bank *bank) 94 { 95 return hwirq - (bank->gc.base - bank->parent_priv->gpio_base); 96 } 97 98 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, 99 unsigned int hwirq, bool enable) 100 { 101 struct gpio_chip *gc = &bank->gc; 102 struct brcmstb_gpio_priv *priv = bank->parent_priv; 103 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank)); 104 u32 imask; 105 unsigned long flags; 106 107 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 108 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id)); 109 if (enable) 110 imask |= mask; 111 else 112 imask &= ~mask; 113 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask); 114 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 115 } 116 117 static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 118 { 119 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc); 120 /* gc_offset is relative to this gpio_chip; want real offset */ 121 int hwirq = offset + (gc->base - priv->gpio_base); 122 123 if (hwirq >= priv->num_gpios) 124 return -ENXIO; 125 return irq_create_mapping(priv->irq_domain, hwirq); 126 } 127 128 /* -------------------- IRQ chip functions -------------------- */ 129 130 static void brcmstb_gpio_irq_mask(struct irq_data *d) 131 { 132 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 133 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 134 135 brcmstb_gpio_set_imask(bank, d->hwirq, false); 136 } 137 138 static void brcmstb_gpio_irq_unmask(struct irq_data *d) 139 { 140 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 141 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 142 143 brcmstb_gpio_set_imask(bank, d->hwirq, true); 144 } 145 146 static void brcmstb_gpio_irq_ack(struct irq_data *d) 147 { 148 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 149 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 150 struct brcmstb_gpio_priv *priv = bank->parent_priv; 151 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); 152 153 gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask); 154 } 155 156 static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type) 157 { 158 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 159 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 160 struct brcmstb_gpio_priv *priv = bank->parent_priv; 161 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); 162 u32 edge_insensitive, iedge_insensitive; 163 u32 edge_config, iedge_config; 164 u32 level, ilevel; 165 unsigned long flags; 166 167 switch (type) { 168 case IRQ_TYPE_LEVEL_LOW: 169 level = mask; 170 edge_config = 0; 171 edge_insensitive = 0; 172 break; 173 case IRQ_TYPE_LEVEL_HIGH: 174 level = mask; 175 edge_config = mask; 176 edge_insensitive = 0; 177 break; 178 case IRQ_TYPE_EDGE_FALLING: 179 level = 0; 180 edge_config = 0; 181 edge_insensitive = 0; 182 break; 183 case IRQ_TYPE_EDGE_RISING: 184 level = 0; 185 edge_config = mask; 186 edge_insensitive = 0; 187 break; 188 case IRQ_TYPE_EDGE_BOTH: 189 level = 0; 190 edge_config = 0; /* don't care, but want known value */ 191 edge_insensitive = mask; 192 break; 193 default: 194 return -EINVAL; 195 } 196 197 raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags); 198 199 iedge_config = bank->gc.read_reg(priv->reg_base + 200 GIO_EC(bank->id)) & ~mask; 201 iedge_insensitive = bank->gc.read_reg(priv->reg_base + 202 GIO_EI(bank->id)) & ~mask; 203 ilevel = bank->gc.read_reg(priv->reg_base + 204 GIO_LEVEL(bank->id)) & ~mask; 205 206 bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id), 207 iedge_config | edge_config); 208 bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id), 209 iedge_insensitive | edge_insensitive); 210 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id), 211 ilevel | level); 212 213 raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); 214 return 0; 215 } 216 217 static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv, 218 unsigned int enable) 219 { 220 int ret = 0; 221 222 if (enable) 223 ret = enable_irq_wake(priv->parent_wake_irq); 224 else 225 ret = disable_irq_wake(priv->parent_wake_irq); 226 if (ret) 227 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n", 228 enable ? "enable" : "disable"); 229 return ret; 230 } 231 232 static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) 233 { 234 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 235 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 236 struct brcmstb_gpio_priv *priv = bank->parent_priv; 237 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); 238 239 /* 240 * Do not do anything specific for now, suspend/resume callbacks will 241 * configure the interrupt mask appropriately 242 */ 243 if (enable) 244 bank->wake_active |= mask; 245 else 246 bank->wake_active &= ~mask; 247 248 return brcmstb_gpio_priv_set_wake(priv, enable); 249 } 250 251 static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data) 252 { 253 struct brcmstb_gpio_priv *priv = data; 254 255 if (!priv || irq != priv->parent_wake_irq) 256 return IRQ_NONE; 257 258 /* Nothing to do */ 259 return IRQ_HANDLED; 260 } 261 262 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank) 263 { 264 struct brcmstb_gpio_priv *priv = bank->parent_priv; 265 struct irq_domain *domain = priv->irq_domain; 266 int hwbase = bank->gc.base - priv->gpio_base; 267 unsigned long status; 268 269 while ((status = brcmstb_gpio_get_active_irqs(bank))) { 270 unsigned int offset; 271 272 for_each_set_bit(offset, &status, 32) { 273 if (offset >= bank->width) 274 dev_warn(&priv->pdev->dev, 275 "IRQ for invalid GPIO (bank=%d, offset=%d)\n", 276 bank->id, offset); 277 generic_handle_domain_irq(domain, hwbase + offset); 278 } 279 } 280 } 281 282 /* Each UPG GIO block has one IRQ for all banks */ 283 static void brcmstb_gpio_irq_handler(struct irq_desc *desc) 284 { 285 struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc); 286 struct irq_chip *chip = irq_desc_get_chip(desc); 287 struct brcmstb_gpio_bank *bank; 288 289 /* Interrupts weren't properly cleared during probe */ 290 BUG_ON(!priv || !chip); 291 292 chained_irq_enter(chip, desc); 293 list_for_each_entry(bank, &priv->bank_list, node) 294 brcmstb_gpio_irq_bank_handler(bank); 295 chained_irq_exit(chip, desc); 296 } 297 298 static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank( 299 struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq) 300 { 301 struct brcmstb_gpio_bank *bank; 302 int i = 0; 303 304 /* banks are in descending order */ 305 list_for_each_entry_reverse(bank, &priv->bank_list, node) { 306 i += bank->gc.ngpio; 307 if (hwirq < i) 308 return bank; 309 } 310 return NULL; 311 } 312 313 /* 314 * This lock class tells lockdep that GPIO irqs are in a different 315 * category than their parents, so it won't report false recursion. 316 */ 317 static struct lock_class_key brcmstb_gpio_irq_lock_class; 318 static struct lock_class_key brcmstb_gpio_irq_request_class; 319 320 321 static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq, 322 irq_hw_number_t hwirq) 323 { 324 struct brcmstb_gpio_priv *priv = d->host_data; 325 struct brcmstb_gpio_bank *bank = 326 brcmstb_gpio_hwirq_to_bank(priv, hwirq); 327 struct platform_device *pdev = priv->pdev; 328 int ret; 329 330 if (!bank) 331 return -EINVAL; 332 333 dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n", 334 irq, (int)hwirq, bank->id); 335 ret = irq_set_chip_data(irq, &bank->gc); 336 if (ret < 0) 337 return ret; 338 irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class, 339 &brcmstb_gpio_irq_request_class); 340 irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq); 341 irq_set_noprobe(irq); 342 return 0; 343 } 344 345 static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq) 346 { 347 irq_set_chip_and_handler(irq, NULL, NULL); 348 irq_set_chip_data(irq, NULL); 349 } 350 351 static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = { 352 .map = brcmstb_gpio_irq_map, 353 .unmap = brcmstb_gpio_irq_unmap, 354 .xlate = irq_domain_xlate_twocell, 355 }; 356 357 /* Make sure that the number of banks matches up between properties */ 358 static int brcmstb_gpio_sanity_check_banks(struct device *dev, 359 struct device_node *np, struct resource *res) 360 { 361 int res_num_banks = resource_size(res) / GIO_BANK_SIZE; 362 int num_banks = 363 of_property_count_u32_elems(np, "brcm,gpio-bank-widths"); 364 365 if (res_num_banks != num_banks) { 366 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n", 367 res_num_banks, num_banks); 368 return -EINVAL; 369 } else { 370 return 0; 371 } 372 } 373 374 static void brcmstb_gpio_remove(struct platform_device *pdev) 375 { 376 struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev); 377 struct brcmstb_gpio_bank *bank; 378 int offset, virq; 379 380 if (priv->parent_irq > 0) 381 irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL); 382 383 /* Remove all IRQ mappings and delete the domain */ 384 if (priv->irq_domain) { 385 for (offset = 0; offset < priv->num_gpios; offset++) { 386 virq = irq_find_mapping(priv->irq_domain, offset); 387 irq_dispose_mapping(virq); 388 } 389 irq_domain_remove(priv->irq_domain); 390 } 391 392 /* 393 * You can lose return values below, but we report all errors, and it's 394 * more important to actually perform all of the steps. 395 */ 396 list_for_each_entry(bank, &priv->bank_list, node) 397 gpiochip_remove(&bank->gc); 398 } 399 400 static int brcmstb_gpio_of_xlate(struct gpio_chip *gc, 401 const struct of_phandle_args *gpiospec, u32 *flags) 402 { 403 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc); 404 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 405 int offset; 406 407 if (gc->of_gpio_n_cells != 2) { 408 WARN_ON(1); 409 return -EINVAL; 410 } 411 412 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells)) 413 return -EINVAL; 414 415 offset = gpiospec->args[0] - (gc->base - priv->gpio_base); 416 if (offset >= gc->ngpio || offset < 0) 417 return -EINVAL; 418 419 if (unlikely(offset >= bank->width)) { 420 dev_warn_ratelimited(&priv->pdev->dev, 421 "Received request for invalid GPIO offset %d\n", 422 gpiospec->args[0]); 423 } 424 425 if (flags) 426 *flags = gpiospec->args[1]; 427 428 return offset; 429 } 430 431 /* priv->parent_irq and priv->num_gpios must be set before calling */ 432 static int brcmstb_gpio_irq_setup(struct platform_device *pdev, 433 struct brcmstb_gpio_priv *priv) 434 { 435 struct device *dev = &pdev->dev; 436 struct device_node *np = dev->of_node; 437 int err; 438 439 priv->irq_domain = 440 irq_domain_add_linear(np, priv->num_gpios, 441 &brcmstb_gpio_irq_domain_ops, 442 priv); 443 if (!priv->irq_domain) { 444 dev_err(dev, "Couldn't allocate IRQ domain\n"); 445 return -ENXIO; 446 } 447 448 if (of_property_read_bool(np, "wakeup-source")) { 449 priv->parent_wake_irq = platform_get_irq(pdev, 1); 450 if (priv->parent_wake_irq < 0) { 451 priv->parent_wake_irq = 0; 452 dev_warn(dev, 453 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep"); 454 } else { 455 /* 456 * Set wakeup capability so we can process boot-time 457 * "wakeups" (e.g., from S5 cold boot) 458 */ 459 device_set_wakeup_capable(dev, true); 460 device_wakeup_enable(dev); 461 err = devm_request_irq(dev, priv->parent_wake_irq, 462 brcmstb_gpio_wake_irq_handler, 463 IRQF_SHARED, 464 "brcmstb-gpio-wake", priv); 465 466 if (err < 0) { 467 dev_err(dev, "Couldn't request wake IRQ"); 468 goto out_free_domain; 469 } 470 } 471 } 472 473 priv->irq_chip.name = dev_name(dev); 474 priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask; 475 priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask; 476 priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask; 477 priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack; 478 priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type; 479 480 if (priv->parent_wake_irq) 481 priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake; 482 483 irq_set_chained_handler_and_data(priv->parent_irq, 484 brcmstb_gpio_irq_handler, priv); 485 irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY); 486 487 return 0; 488 489 out_free_domain: 490 irq_domain_remove(priv->irq_domain); 491 492 return err; 493 } 494 495 static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv, 496 struct brcmstb_gpio_bank *bank) 497 { 498 struct gpio_chip *gc = &bank->gc; 499 unsigned int i; 500 501 for (i = 0; i < GIO_REG_STAT; i++) 502 bank->saved_regs[i] = gc->read_reg(priv->reg_base + 503 GIO_BANK_OFF(bank->id, i)); 504 } 505 506 static void brcmstb_gpio_quiesce(struct device *dev, bool save) 507 { 508 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev); 509 struct brcmstb_gpio_bank *bank; 510 struct gpio_chip *gc; 511 u32 imask; 512 513 /* disable non-wake interrupt */ 514 if (priv->parent_irq >= 0) 515 disable_irq(priv->parent_irq); 516 517 list_for_each_entry(bank, &priv->bank_list, node) { 518 gc = &bank->gc; 519 520 if (save) 521 brcmstb_gpio_bank_save(priv, bank); 522 523 /* Unmask GPIOs which have been flagged as wake-up sources */ 524 if (priv->parent_wake_irq) 525 imask = bank->wake_active; 526 else 527 imask = 0; 528 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), 529 imask); 530 } 531 } 532 533 static void brcmstb_gpio_shutdown(struct platform_device *pdev) 534 { 535 /* Enable GPIO for S5 cold boot */ 536 brcmstb_gpio_quiesce(&pdev->dev, false); 537 } 538 539 #ifdef CONFIG_PM_SLEEP 540 static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv, 541 struct brcmstb_gpio_bank *bank) 542 { 543 struct gpio_chip *gc = &bank->gc; 544 unsigned int i; 545 546 for (i = 0; i < GIO_REG_STAT; i++) 547 gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i), 548 bank->saved_regs[i]); 549 } 550 551 static int brcmstb_gpio_suspend(struct device *dev) 552 { 553 brcmstb_gpio_quiesce(dev, true); 554 return 0; 555 } 556 557 static int brcmstb_gpio_resume(struct device *dev) 558 { 559 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev); 560 struct brcmstb_gpio_bank *bank; 561 bool need_wakeup_event = false; 562 563 list_for_each_entry(bank, &priv->bank_list, node) { 564 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank); 565 brcmstb_gpio_bank_restore(priv, bank); 566 } 567 568 if (priv->parent_wake_irq && need_wakeup_event) 569 pm_wakeup_event(dev, 0); 570 571 /* enable non-wake interrupt */ 572 if (priv->parent_irq >= 0) 573 enable_irq(priv->parent_irq); 574 575 return 0; 576 } 577 578 #else 579 #define brcmstb_gpio_suspend NULL 580 #define brcmstb_gpio_resume NULL 581 #endif /* CONFIG_PM_SLEEP */ 582 583 static const struct dev_pm_ops brcmstb_gpio_pm_ops = { 584 .suspend_noirq = brcmstb_gpio_suspend, 585 .resume_noirq = brcmstb_gpio_resume, 586 }; 587 588 static int brcmstb_gpio_probe(struct platform_device *pdev) 589 { 590 struct device *dev = &pdev->dev; 591 struct device_node *np = dev->of_node; 592 void __iomem *reg_base; 593 struct brcmstb_gpio_priv *priv; 594 struct resource *res; 595 struct property *prop; 596 const __be32 *p; 597 u32 bank_width; 598 int num_banks = 0; 599 int err; 600 static int gpio_base; 601 unsigned long flags = 0; 602 bool need_wakeup_event = false; 603 604 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 605 if (!priv) 606 return -ENOMEM; 607 platform_set_drvdata(pdev, priv); 608 INIT_LIST_HEAD(&priv->bank_list); 609 610 reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 611 if (IS_ERR(reg_base)) 612 return PTR_ERR(reg_base); 613 614 priv->gpio_base = gpio_base; 615 priv->reg_base = reg_base; 616 priv->pdev = pdev; 617 618 if (of_property_read_bool(np, "interrupt-controller")) { 619 priv->parent_irq = platform_get_irq(pdev, 0); 620 if (priv->parent_irq <= 0) 621 return -ENOENT; 622 } else { 623 priv->parent_irq = -ENOENT; 624 } 625 626 if (brcmstb_gpio_sanity_check_banks(dev, np, res)) 627 return -EINVAL; 628 629 /* 630 * MIPS endianness is configured by boot strap, which also reverses all 631 * bus endianness (i.e., big-endian CPU + big endian bus ==> native 632 * endian I/O). 633 * 634 * Other architectures (e.g., ARM) either do not support big endian, or 635 * else leave I/O in little endian mode. 636 */ 637 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN) 638 flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER; 639 #endif 640 641 of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p, 642 bank_width) { 643 struct brcmstb_gpio_bank *bank; 644 struct gpio_chip *gc; 645 646 /* 647 * If bank_width is 0, then there is an empty bank in the 648 * register block. Special handling for this case. 649 */ 650 if (bank_width == 0) { 651 dev_dbg(dev, "Width 0 found: Empty bank @ %d\n", 652 num_banks); 653 num_banks++; 654 gpio_base += MAX_GPIO_PER_BANK; 655 continue; 656 } 657 658 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); 659 if (!bank) { 660 err = -ENOMEM; 661 goto fail; 662 } 663 664 bank->parent_priv = priv; 665 bank->id = num_banks; 666 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) { 667 dev_err(dev, "Invalid bank width %d\n", bank_width); 668 err = -EINVAL; 669 goto fail; 670 } else { 671 bank->width = bank_width; 672 } 673 674 /* 675 * Regs are 4 bytes wide, have data reg, no set/clear regs, 676 * and direction bits have 0 = output and 1 = input 677 */ 678 gc = &bank->gc; 679 err = bgpio_init(gc, dev, 4, 680 reg_base + GIO_DATA(bank->id), 681 NULL, NULL, NULL, 682 reg_base + GIO_IODIR(bank->id), flags); 683 if (err) { 684 dev_err(dev, "bgpio_init() failed\n"); 685 goto fail; 686 } 687 688 gc->owner = THIS_MODULE; 689 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np); 690 if (!gc->label) { 691 err = -ENOMEM; 692 goto fail; 693 } 694 gc->base = gpio_base; 695 gc->of_gpio_n_cells = 2; 696 gc->of_xlate = brcmstb_gpio_of_xlate; 697 /* not all ngpio lines are valid, will use bank width later */ 698 gc->ngpio = MAX_GPIO_PER_BANK; 699 gc->offset = bank->id * MAX_GPIO_PER_BANK; 700 if (priv->parent_irq > 0) 701 gc->to_irq = brcmstb_gpio_to_irq; 702 703 /* 704 * Mask all interrupts by default, since wakeup interrupts may 705 * be retained from S5 cold boot 706 */ 707 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank); 708 gc->write_reg(reg_base + GIO_MASK(bank->id), 0); 709 710 err = gpiochip_add_data(gc, bank); 711 if (err) { 712 dev_err(dev, "Could not add gpiochip for bank %d\n", 713 bank->id); 714 goto fail; 715 } 716 gpio_base += gc->ngpio; 717 718 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id, 719 gc->base, gc->ngpio, bank->width); 720 721 /* Everything looks good, so add bank to list */ 722 list_add(&bank->node, &priv->bank_list); 723 724 num_banks++; 725 } 726 727 priv->num_gpios = gpio_base - priv->gpio_base; 728 if (priv->parent_irq > 0) { 729 err = brcmstb_gpio_irq_setup(pdev, priv); 730 if (err) 731 goto fail; 732 } 733 734 if (priv->parent_wake_irq && need_wakeup_event) 735 pm_wakeup_event(dev, 0); 736 737 return 0; 738 739 fail: 740 (void) brcmstb_gpio_remove(pdev); 741 return err; 742 } 743 744 static const struct of_device_id brcmstb_gpio_of_match[] = { 745 { .compatible = "brcm,brcmstb-gpio" }, 746 {}, 747 }; 748 749 MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match); 750 751 static struct platform_driver brcmstb_gpio_driver = { 752 .driver = { 753 .name = "brcmstb-gpio", 754 .of_match_table = brcmstb_gpio_of_match, 755 .pm = &brcmstb_gpio_pm_ops, 756 }, 757 .probe = brcmstb_gpio_probe, 758 .remove_new = brcmstb_gpio_remove, 759 .shutdown = brcmstb_gpio_shutdown, 760 }; 761 module_platform_driver(brcmstb_gpio_driver); 762 763 MODULE_AUTHOR("Gregory Fong"); 764 MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO"); 765 MODULE_LICENSE("GPL v2"); 766