1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (C) 2015-2017 Broadcom 3 4 #include <linux/bitops.h> 5 #include <linux/gpio/driver.h> 6 #include <linux/gpio/generic.h> 7 #include <linux/of.h> 8 #include <linux/module.h> 9 #include <linux/irqdomain.h> 10 #include <linux/irqchip/chained_irq.h> 11 #include <linux/interrupt.h> 12 #include <linux/platform_device.h> 13 #include <linux/string_choices.h> 14 15 enum gio_reg_index { 16 GIO_REG_ODEN = 0, 17 GIO_REG_DATA, 18 GIO_REG_IODIR, 19 GIO_REG_EC, 20 GIO_REG_EI, 21 GIO_REG_MASK, 22 GIO_REG_LEVEL, 23 GIO_REG_STAT, 24 NUMBER_OF_GIO_REGISTERS 25 }; 26 27 #define GIO_BANK_SIZE (NUMBER_OF_GIO_REGISTERS * sizeof(u32)) 28 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) 29 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) 30 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) 31 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) 32 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) 33 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) 34 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) 35 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) 36 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT) 37 38 struct brcmstb_gpio_bank { 39 struct list_head node; 40 int id; 41 struct gpio_generic_chip chip; 42 struct brcmstb_gpio_priv *parent_priv; 43 u32 width; 44 u32 wake_active; 45 u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */ 46 }; 47 48 struct brcmstb_gpio_priv { 49 struct list_head bank_list; 50 void __iomem *reg_base; 51 struct platform_device *pdev; 52 struct irq_domain *irq_domain; 53 struct irq_chip irq_chip; 54 int parent_irq; 55 int num_gpios; 56 int parent_wake_irq; 57 }; 58 59 #define MAX_GPIO_PER_BANK 32 60 #define GPIO_BANK(gpio) ((gpio) >> 5) 61 /* assumes MAX_GPIO_PER_BANK is a multiple of 2 */ 62 #define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1)) 63 64 static inline struct brcmstb_gpio_priv * 65 brcmstb_gpio_gc_to_priv(struct gpio_chip *gc) 66 { 67 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 68 return bank->parent_priv; 69 } 70 71 static unsigned long 72 __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank) 73 { 74 void __iomem *reg_base = bank->parent_priv->reg_base; 75 76 return gpio_generic_read_reg(&bank->chip, reg_base + GIO_STAT(bank->id)) & 77 gpio_generic_read_reg(&bank->chip, reg_base + GIO_MASK(bank->id)); 78 } 79 80 static unsigned long 81 brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank) 82 { 83 unsigned long status; 84 85 guard(gpio_generic_lock_irqsave)(&bank->chip); 86 87 status = __brcmstb_gpio_get_active_irqs(bank); 88 89 return status; 90 } 91 92 static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq, 93 struct brcmstb_gpio_bank *bank) 94 { 95 return hwirq - bank->chip.gc.offset; 96 } 97 98 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, 99 unsigned int hwirq, bool enable) 100 { 101 struct brcmstb_gpio_priv *priv = bank->parent_priv; 102 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank)); 103 u32 imask; 104 105 guard(gpio_generic_lock_irqsave)(&bank->chip); 106 107 imask = gpio_generic_read_reg(&bank->chip, 108 priv->reg_base + GIO_MASK(bank->id)); 109 if (enable) 110 imask |= mask; 111 else 112 imask &= ~mask; 113 gpio_generic_write_reg(&bank->chip, 114 priv->reg_base + GIO_MASK(bank->id), imask); 115 } 116 117 static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 118 { 119 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc); 120 /* gc_offset is relative to this gpio_chip; want real offset */ 121 int hwirq = offset + gc->offset; 122 123 if (hwirq >= priv->num_gpios) 124 return -ENXIO; 125 return irq_create_mapping(priv->irq_domain, hwirq); 126 } 127 128 /* -------------------- IRQ chip functions -------------------- */ 129 130 static void brcmstb_gpio_irq_mask(struct irq_data *d) 131 { 132 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 133 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 134 135 brcmstb_gpio_set_imask(bank, d->hwirq, false); 136 } 137 138 static void brcmstb_gpio_irq_unmask(struct irq_data *d) 139 { 140 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 141 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 142 143 brcmstb_gpio_set_imask(bank, d->hwirq, true); 144 } 145 146 static void brcmstb_gpio_irq_ack(struct irq_data *d) 147 { 148 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 149 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 150 struct brcmstb_gpio_priv *priv = bank->parent_priv; 151 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); 152 153 gpio_generic_write_reg(&bank->chip, 154 priv->reg_base + GIO_STAT(bank->id), mask); 155 } 156 157 static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type) 158 { 159 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 160 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 161 struct brcmstb_gpio_priv *priv = bank->parent_priv; 162 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); 163 u32 edge_insensitive, iedge_insensitive; 164 u32 edge_config, iedge_config; 165 u32 level, ilevel; 166 167 switch (type) { 168 case IRQ_TYPE_LEVEL_LOW: 169 level = mask; 170 edge_config = 0; 171 edge_insensitive = 0; 172 break; 173 case IRQ_TYPE_LEVEL_HIGH: 174 level = mask; 175 edge_config = mask; 176 edge_insensitive = 0; 177 break; 178 case IRQ_TYPE_EDGE_FALLING: 179 level = 0; 180 edge_config = 0; 181 edge_insensitive = 0; 182 break; 183 case IRQ_TYPE_EDGE_RISING: 184 level = 0; 185 edge_config = mask; 186 edge_insensitive = 0; 187 break; 188 case IRQ_TYPE_EDGE_BOTH: 189 level = 0; 190 edge_config = 0; /* don't care, but want known value */ 191 edge_insensitive = mask; 192 break; 193 default: 194 return -EINVAL; 195 } 196 197 guard(gpio_generic_lock_irqsave)(&bank->chip); 198 199 iedge_config = gpio_generic_read_reg(&bank->chip, 200 priv->reg_base + GIO_EC(bank->id)) & ~mask; 201 iedge_insensitive = gpio_generic_read_reg(&bank->chip, 202 priv->reg_base + GIO_EI(bank->id)) & ~mask; 203 ilevel = gpio_generic_read_reg(&bank->chip, 204 priv->reg_base + GIO_LEVEL(bank->id)) & ~mask; 205 206 gpio_generic_write_reg(&bank->chip, 207 priv->reg_base + GIO_EC(bank->id), 208 iedge_config | edge_config); 209 gpio_generic_write_reg(&bank->chip, 210 priv->reg_base + GIO_EI(bank->id), 211 iedge_insensitive | edge_insensitive); 212 gpio_generic_write_reg(&bank->chip, 213 priv->reg_base + GIO_LEVEL(bank->id), 214 ilevel | level); 215 216 return 0; 217 } 218 219 static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv, 220 unsigned int enable) 221 { 222 int ret = 0; 223 224 if (enable) 225 ret = enable_irq_wake(priv->parent_wake_irq); 226 else 227 ret = disable_irq_wake(priv->parent_wake_irq); 228 if (ret) 229 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n", 230 str_enable_disable(enable)); 231 return ret; 232 } 233 234 static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) 235 { 236 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 237 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 238 struct brcmstb_gpio_priv *priv = bank->parent_priv; 239 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); 240 241 /* 242 * Do not do anything specific for now, suspend/resume callbacks will 243 * configure the interrupt mask appropriately 244 */ 245 if (enable) 246 bank->wake_active |= mask; 247 else 248 bank->wake_active &= ~mask; 249 250 return brcmstb_gpio_priv_set_wake(priv, enable); 251 } 252 253 static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data) 254 { 255 struct brcmstb_gpio_priv *priv = data; 256 257 if (!priv || irq != priv->parent_wake_irq) 258 return IRQ_NONE; 259 260 /* Nothing to do */ 261 return IRQ_HANDLED; 262 } 263 264 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank) 265 { 266 struct brcmstb_gpio_priv *priv = bank->parent_priv; 267 struct irq_domain *domain = priv->irq_domain; 268 int hwbase = bank->chip.gc.offset; 269 unsigned long status; 270 271 while ((status = brcmstb_gpio_get_active_irqs(bank))) { 272 unsigned int offset; 273 274 for_each_set_bit(offset, &status, 32) { 275 if (offset >= bank->width) 276 dev_warn(&priv->pdev->dev, 277 "IRQ for invalid GPIO (bank=%d, offset=%d)\n", 278 bank->id, offset); 279 generic_handle_domain_irq(domain, hwbase + offset); 280 } 281 } 282 } 283 284 /* Each UPG GIO block has one IRQ for all banks */ 285 static void brcmstb_gpio_irq_handler(struct irq_desc *desc) 286 { 287 struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc); 288 struct irq_chip *chip = irq_desc_get_chip(desc); 289 struct brcmstb_gpio_bank *bank; 290 291 /* Interrupts weren't properly cleared during probe */ 292 BUG_ON(!priv || !chip); 293 294 chained_irq_enter(chip, desc); 295 list_for_each_entry(bank, &priv->bank_list, node) 296 brcmstb_gpio_irq_bank_handler(bank); 297 chained_irq_exit(chip, desc); 298 } 299 300 static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank( 301 struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq) 302 { 303 struct brcmstb_gpio_bank *bank; 304 int i = 0; 305 306 /* banks are in descending order */ 307 list_for_each_entry_reverse(bank, &priv->bank_list, node) { 308 i += bank->chip.gc.ngpio; 309 if (hwirq < i) 310 return bank; 311 } 312 return NULL; 313 } 314 315 /* 316 * This lock class tells lockdep that GPIO irqs are in a different 317 * category than their parents, so it won't report false recursion. 318 */ 319 static struct lock_class_key brcmstb_gpio_irq_lock_class; 320 static struct lock_class_key brcmstb_gpio_irq_request_class; 321 322 323 static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq, 324 irq_hw_number_t hwirq) 325 { 326 struct brcmstb_gpio_priv *priv = d->host_data; 327 struct brcmstb_gpio_bank *bank = 328 brcmstb_gpio_hwirq_to_bank(priv, hwirq); 329 struct platform_device *pdev = priv->pdev; 330 int ret; 331 332 if (!bank) 333 return -EINVAL; 334 335 dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n", 336 irq, (int)hwirq, bank->id); 337 ret = irq_set_chip_data(irq, &bank->chip.gc); 338 if (ret < 0) 339 return ret; 340 irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class, 341 &brcmstb_gpio_irq_request_class); 342 irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq); 343 irq_set_noprobe(irq); 344 return 0; 345 } 346 347 static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq) 348 { 349 irq_set_chip_and_handler(irq, NULL, NULL); 350 irq_set_chip_data(irq, NULL); 351 } 352 353 static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = { 354 .map = brcmstb_gpio_irq_map, 355 .unmap = brcmstb_gpio_irq_unmap, 356 .xlate = irq_domain_xlate_twocell, 357 }; 358 359 /* Make sure that the number of banks matches up between properties */ 360 static int brcmstb_gpio_sanity_check_banks(struct device *dev, 361 struct device_node *np, struct resource *res) 362 { 363 int res_num_banks = resource_size(res) / GIO_BANK_SIZE; 364 int num_banks = 365 of_property_count_u32_elems(np, "brcm,gpio-bank-widths"); 366 367 if (res_num_banks != num_banks) { 368 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n", 369 res_num_banks, num_banks); 370 return -EINVAL; 371 } else { 372 return 0; 373 } 374 } 375 376 static void brcmstb_gpio_remove(struct platform_device *pdev) 377 { 378 struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev); 379 struct brcmstb_gpio_bank *bank; 380 int offset, virq; 381 382 if (priv->parent_irq > 0) 383 irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL); 384 385 /* Remove all IRQ mappings and delete the domain */ 386 if (priv->irq_domain) { 387 for (offset = 0; offset < priv->num_gpios; offset++) { 388 virq = irq_find_mapping(priv->irq_domain, offset); 389 irq_dispose_mapping(virq); 390 } 391 irq_domain_remove(priv->irq_domain); 392 } 393 394 /* 395 * You can lose return values below, but we report all errors, and it's 396 * more important to actually perform all of the steps. 397 */ 398 list_for_each_entry(bank, &priv->bank_list, node) 399 gpiochip_remove(&bank->chip.gc); 400 } 401 402 static int brcmstb_gpio_of_xlate(struct gpio_chip *gc, 403 const struct of_phandle_args *gpiospec, u32 *flags) 404 { 405 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc); 406 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 407 int offset; 408 409 if (gc->of_gpio_n_cells != 2) { 410 WARN_ON(1); 411 return -EINVAL; 412 } 413 414 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells)) 415 return -EINVAL; 416 417 offset = gpiospec->args[0] - bank->chip.gc.offset; 418 if (offset >= gc->ngpio || offset < 0) 419 return -EINVAL; 420 421 if (unlikely(offset >= bank->width)) { 422 dev_warn_ratelimited(&priv->pdev->dev, 423 "Received request for invalid GPIO offset %d\n", 424 gpiospec->args[0]); 425 } 426 427 if (flags) 428 *flags = gpiospec->args[1]; 429 430 return offset; 431 } 432 433 /* priv->parent_irq and priv->num_gpios must be set before calling */ 434 static int brcmstb_gpio_irq_setup(struct platform_device *pdev, 435 struct brcmstb_gpio_priv *priv) 436 { 437 struct device *dev = &pdev->dev; 438 struct device_node *np = dev->of_node; 439 int err; 440 441 priv->irq_domain = irq_domain_create_linear(dev_fwnode(dev), priv->num_gpios, 442 &brcmstb_gpio_irq_domain_ops, priv); 443 if (!priv->irq_domain) { 444 dev_err(dev, "Couldn't allocate IRQ domain\n"); 445 return -ENXIO; 446 } 447 448 if (of_property_read_bool(np, "wakeup-source")) { 449 priv->parent_wake_irq = platform_get_irq(pdev, 1); 450 if (priv->parent_wake_irq < 0) { 451 priv->parent_wake_irq = 0; 452 dev_warn(dev, 453 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep"); 454 } else { 455 /* 456 * Set wakeup capability so we can process boot-time 457 * "wakeups" (e.g., from S5 cold boot) 458 */ 459 device_set_wakeup_capable(dev, true); 460 device_wakeup_enable(dev); 461 err = devm_request_irq(dev, priv->parent_wake_irq, 462 brcmstb_gpio_wake_irq_handler, 463 IRQF_SHARED, 464 "brcmstb-gpio-wake", priv); 465 466 if (err < 0) { 467 dev_err(dev, "Couldn't request wake IRQ"); 468 goto out_free_domain; 469 } 470 } 471 } 472 473 priv->irq_chip.name = dev_name(dev); 474 priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask; 475 priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask; 476 priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask; 477 priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack; 478 priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type; 479 480 if (priv->parent_wake_irq) 481 priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake; 482 483 irq_set_chained_handler_and_data(priv->parent_irq, 484 brcmstb_gpio_irq_handler, priv); 485 irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY); 486 487 return 0; 488 489 out_free_domain: 490 irq_domain_remove(priv->irq_domain); 491 492 return err; 493 } 494 495 static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv, 496 struct brcmstb_gpio_bank *bank) 497 { 498 unsigned int i; 499 500 for (i = 0; i < GIO_REG_STAT; i++) 501 bank->saved_regs[i] = gpio_generic_read_reg(&bank->chip, 502 priv->reg_base + GIO_BANK_OFF(bank->id, i)); 503 } 504 505 static void brcmstb_gpio_quiesce(struct device *dev, bool save) 506 { 507 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev); 508 struct brcmstb_gpio_bank *bank; 509 u32 imask; 510 511 /* disable non-wake interrupt */ 512 if (priv->parent_irq >= 0) 513 disable_irq(priv->parent_irq); 514 515 list_for_each_entry(bank, &priv->bank_list, node) { 516 if (save) 517 brcmstb_gpio_bank_save(priv, bank); 518 519 /* Unmask GPIOs which have been flagged as wake-up sources */ 520 if (priv->parent_wake_irq) 521 imask = bank->wake_active; 522 else 523 imask = 0; 524 gpio_generic_write_reg(&bank->chip, 525 priv->reg_base + GIO_MASK(bank->id), 526 imask); 527 } 528 } 529 530 static void brcmstb_gpio_shutdown(struct platform_device *pdev) 531 { 532 /* Enable GPIO for S5 cold boot */ 533 brcmstb_gpio_quiesce(&pdev->dev, false); 534 } 535 536 static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv, 537 struct brcmstb_gpio_bank *bank) 538 { 539 unsigned int i; 540 541 for (i = 0; i < GIO_REG_STAT; i++) 542 gpio_generic_write_reg(&bank->chip, 543 priv->reg_base + GIO_BANK_OFF(bank->id, i), 544 bank->saved_regs[i]); 545 } 546 547 static int brcmstb_gpio_suspend(struct device *dev) 548 { 549 brcmstb_gpio_quiesce(dev, true); 550 return 0; 551 } 552 553 static int brcmstb_gpio_resume(struct device *dev) 554 { 555 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev); 556 struct brcmstb_gpio_bank *bank; 557 bool need_wakeup_event = false; 558 559 list_for_each_entry(bank, &priv->bank_list, node) { 560 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank); 561 brcmstb_gpio_bank_restore(priv, bank); 562 } 563 564 if (priv->parent_wake_irq && need_wakeup_event) 565 pm_wakeup_event(dev, 0); 566 567 /* enable non-wake interrupt */ 568 if (priv->parent_irq >= 0) 569 enable_irq(priv->parent_irq); 570 571 return 0; 572 } 573 574 static const struct dev_pm_ops brcmstb_gpio_pm_ops = { 575 .suspend_noirq = pm_sleep_ptr(brcmstb_gpio_suspend), 576 .resume_noirq = pm_sleep_ptr(brcmstb_gpio_resume), 577 }; 578 579 static int brcmstb_gpio_probe(struct platform_device *pdev) 580 { 581 struct gpio_generic_chip_config config; 582 struct device *dev = &pdev->dev; 583 struct device_node *np = dev->of_node; 584 void __iomem *reg_base; 585 struct brcmstb_gpio_priv *priv; 586 struct resource *res; 587 u32 bank_width; 588 int num_banks = 0; 589 int num_gpios = 0; 590 int err; 591 unsigned long flags = 0; 592 bool need_wakeup_event = false; 593 594 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 595 if (!priv) 596 return -ENOMEM; 597 platform_set_drvdata(pdev, priv); 598 INIT_LIST_HEAD(&priv->bank_list); 599 600 reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 601 if (IS_ERR(reg_base)) 602 return PTR_ERR(reg_base); 603 604 priv->reg_base = reg_base; 605 priv->pdev = pdev; 606 607 if (of_property_read_bool(np, "interrupt-controller")) { 608 priv->parent_irq = platform_get_irq(pdev, 0); 609 if (priv->parent_irq <= 0) 610 return -ENOENT; 611 } else { 612 priv->parent_irq = -ENOENT; 613 } 614 615 if (brcmstb_gpio_sanity_check_banks(dev, np, res)) 616 return -EINVAL; 617 618 /* 619 * MIPS endianness is configured by boot strap, which also reverses all 620 * bus endianness (i.e., big-endian CPU + big endian bus ==> native 621 * endian I/O). 622 * 623 * Other architectures (e.g., ARM) either do not support big endian, or 624 * else leave I/O in little endian mode. 625 */ 626 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN) 627 flags = GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER; 628 #endif 629 630 of_property_for_each_u32(np, "brcm,gpio-bank-widths", bank_width) { 631 struct brcmstb_gpio_bank *bank; 632 struct gpio_chip *gc; 633 634 /* 635 * If bank_width is 0, then there is an empty bank in the 636 * register block. Special handling for this case. 637 */ 638 if (bank_width == 0) { 639 dev_dbg(dev, "Width 0 found: Empty bank @ %d\n", 640 num_banks); 641 num_banks++; 642 num_gpios += MAX_GPIO_PER_BANK; 643 continue; 644 } 645 646 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); 647 if (!bank) { 648 err = -ENOMEM; 649 goto fail; 650 } 651 652 bank->parent_priv = priv; 653 bank->id = num_banks; 654 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) { 655 dev_err(dev, "Invalid bank width %d\n", bank_width); 656 err = -EINVAL; 657 goto fail; 658 } else { 659 bank->width = bank_width; 660 } 661 662 gc = &bank->chip.gc; 663 664 /* 665 * Regs are 4 bytes wide, have data reg, no set/clear regs, 666 * and direction bits have 0 = output and 1 = input 667 */ 668 669 config = (struct gpio_generic_chip_config) { 670 .dev = dev, 671 .sz = 4, 672 .dat = reg_base + GIO_DATA(bank->id), 673 .dirin = reg_base + GIO_IODIR(bank->id), 674 .flags = flags, 675 }; 676 677 err = gpio_generic_chip_init(&bank->chip, &config); 678 if (err) { 679 dev_err(dev, "failed to initialize generic GPIO chip\n"); 680 goto fail; 681 } 682 683 gc->owner = THIS_MODULE; 684 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np); 685 if (!gc->label) { 686 err = -ENOMEM; 687 goto fail; 688 } 689 gc->of_gpio_n_cells = 2; 690 gc->of_xlate = brcmstb_gpio_of_xlate; 691 /* not all ngpio lines are valid, will use bank width later */ 692 gc->ngpio = MAX_GPIO_PER_BANK; 693 gc->offset = bank->id * MAX_GPIO_PER_BANK; 694 gc->request = gpiochip_generic_request; 695 gc->free = gpiochip_generic_free; 696 if (priv->parent_irq > 0) 697 gc->to_irq = brcmstb_gpio_to_irq; 698 699 /* 700 * Mask all interrupts by default, since wakeup interrupts may 701 * be retained from S5 cold boot 702 */ 703 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank); 704 gpio_generic_write_reg(&bank->chip, 705 reg_base + GIO_MASK(bank->id), 0); 706 707 err = gpiochip_add_data(gc, bank); 708 if (err) { 709 dev_err(dev, "Could not add gpiochip for bank %d\n", 710 bank->id); 711 goto fail; 712 } 713 num_gpios += gc->ngpio; 714 715 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id, 716 gc->base, gc->ngpio, bank->width); 717 718 /* Everything looks good, so add bank to list */ 719 list_add(&bank->node, &priv->bank_list); 720 721 num_banks++; 722 } 723 724 priv->num_gpios = num_gpios; 725 if (priv->parent_irq > 0) { 726 err = brcmstb_gpio_irq_setup(pdev, priv); 727 if (err) 728 goto fail; 729 } 730 731 if (priv->parent_wake_irq && need_wakeup_event) 732 pm_wakeup_event(dev, 0); 733 734 return 0; 735 736 fail: 737 (void) brcmstb_gpio_remove(pdev); 738 return err; 739 } 740 741 static const struct of_device_id brcmstb_gpio_of_match[] = { 742 { .compatible = "brcm,brcmstb-gpio" }, 743 {}, 744 }; 745 746 MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match); 747 748 static struct platform_driver brcmstb_gpio_driver = { 749 .driver = { 750 .name = "brcmstb-gpio", 751 .of_match_table = brcmstb_gpio_of_match, 752 .pm = pm_sleep_ptr(&brcmstb_gpio_pm_ops), 753 }, 754 .probe = brcmstb_gpio_probe, 755 .remove = brcmstb_gpio_remove, 756 .shutdown = brcmstb_gpio_shutdown, 757 }; 758 module_platform_driver(brcmstb_gpio_driver); 759 760 MODULE_AUTHOR("Gregory Fong"); 761 MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO"); 762 MODULE_LICENSE("GPL v2"); 763