1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (C) 2015-2017, 2026 Broadcom 3 4 #include <linux/bitops.h> 5 #include <linux/gpio/driver.h> 6 #include <linux/gpio/generic.h> 7 #include <linux/of.h> 8 #include <linux/module.h> 9 #include <linux/irqdomain.h> 10 #include <linux/irqchip/chained_irq.h> 11 #include <linux/interrupt.h> 12 #include <linux/platform_device.h> 13 #include <linux/string_choices.h> 14 15 enum gio_reg_index { 16 GIO_REG_ODEN = 0, 17 GIO_REG_DATA, 18 GIO_REG_IODIR, 19 GIO_REG_EC, 20 GIO_REG_EI, 21 GIO_REG_MASK, 22 GIO_REG_LEVEL, 23 GIO_REG_STAT, 24 NUMBER_OF_GIO_REGISTERS 25 }; 26 27 #define GIO_BANK_SIZE (NUMBER_OF_GIO_REGISTERS * sizeof(u32)) 28 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) 29 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) 30 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) 31 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) 32 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) 33 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) 34 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) 35 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) 36 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT) 37 38 struct brcmstb_gpio_bank { 39 struct list_head node; 40 int id; 41 struct gpio_generic_chip chip; 42 struct brcmstb_gpio_priv *parent_priv; 43 u32 width; 44 u32 wake_active; 45 u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */ 46 }; 47 48 struct brcmstb_gpio_priv { 49 struct list_head bank_list; 50 void __iomem *reg_base; 51 struct platform_device *pdev; 52 struct irq_domain *irq_domain; 53 struct irq_chip irq_chip; 54 int parent_irq; 55 int num_gpios; 56 int parent_wake_irq; 57 bool suspended; 58 }; 59 60 #define MAX_GPIO_PER_BANK 32 61 #define GPIO_BANK(gpio) ((gpio) >> 5) 62 /* assumes MAX_GPIO_PER_BANK is a multiple of 2 */ 63 #define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1)) 64 65 static inline struct brcmstb_gpio_priv * 66 brcmstb_gpio_gc_to_priv(struct gpio_chip *gc) 67 { 68 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 69 return bank->parent_priv; 70 } 71 72 static unsigned long 73 __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank) 74 { 75 void __iomem *reg_base = bank->parent_priv->reg_base; 76 77 return gpio_generic_read_reg(&bank->chip, reg_base + GIO_STAT(bank->id)) & 78 gpio_generic_read_reg(&bank->chip, reg_base + GIO_MASK(bank->id)); 79 } 80 81 static unsigned long 82 brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank) 83 { 84 unsigned long status; 85 86 guard(gpio_generic_lock_irqsave)(&bank->chip); 87 88 status = __brcmstb_gpio_get_active_irqs(bank); 89 90 return status; 91 } 92 93 static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq, 94 struct brcmstb_gpio_bank *bank) 95 { 96 return hwirq - bank->chip.gc.offset; 97 } 98 99 static void __brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, 100 irq_hw_number_t hwirq, bool enable) 101 { 102 struct brcmstb_gpio_priv *priv = bank->parent_priv; 103 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank)); 104 u32 imask; 105 106 imask = gpio_generic_read_reg(&bank->chip, 107 priv->reg_base + GIO_MASK(bank->id)); 108 if (enable) 109 imask |= mask; 110 else 111 imask &= ~mask; 112 gpio_generic_write_reg(&bank->chip, 113 priv->reg_base + GIO_MASK(bank->id), imask); 114 } 115 116 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, 117 irq_hw_number_t hwirq, bool enable) 118 { 119 guard(gpio_generic_lock_irqsave)(&bank->chip); 120 __brcmstb_gpio_set_imask(bank, hwirq, enable); 121 } 122 123 static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 124 { 125 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc); 126 /* gc_offset is relative to this gpio_chip; want real offset */ 127 int hwirq = offset + gc->offset; 128 129 if (hwirq >= priv->num_gpios) 130 return -ENXIO; 131 return irq_create_mapping(priv->irq_domain, hwirq); 132 } 133 134 /* -------------------- IRQ chip functions -------------------- */ 135 136 static void brcmstb_gpio_irq_mask(struct irq_data *d) 137 { 138 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 139 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 140 141 brcmstb_gpio_set_imask(bank, irqd_to_hwirq(d), false); 142 } 143 144 static void brcmstb_gpio_irq_mask_ack(struct irq_data *d) 145 { 146 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 147 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 148 struct brcmstb_gpio_priv *priv = bank->parent_priv; 149 irq_hw_number_t hwirq = irqd_to_hwirq(d); 150 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank)); 151 152 guard(gpio_generic_lock_irqsave)(&bank->chip); 153 __brcmstb_gpio_set_imask(bank, hwirq, false); 154 gpio_generic_write_reg(&bank->chip, 155 priv->reg_base + GIO_STAT(bank->id), mask); 156 } 157 158 static void brcmstb_gpio_irq_unmask(struct irq_data *d) 159 { 160 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 161 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 162 163 brcmstb_gpio_set_imask(bank, irqd_to_hwirq(d), true); 164 } 165 166 static void brcmstb_gpio_irq_ack(struct irq_data *d) 167 { 168 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 169 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 170 struct brcmstb_gpio_priv *priv = bank->parent_priv; 171 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(irqd_to_hwirq(d), bank)); 172 173 gpio_generic_write_reg(&bank->chip, 174 priv->reg_base + GIO_STAT(bank->id), mask); 175 } 176 177 static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type) 178 { 179 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 180 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 181 struct brcmstb_gpio_priv *priv = bank->parent_priv; 182 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(irqd_to_hwirq(d), bank)); 183 u32 edge_insensitive, iedge_insensitive; 184 u32 edge_config, iedge_config; 185 u32 level, ilevel; 186 187 switch (type) { 188 case IRQ_TYPE_LEVEL_LOW: 189 level = mask; 190 edge_config = 0; 191 edge_insensitive = 0; 192 break; 193 case IRQ_TYPE_LEVEL_HIGH: 194 level = mask; 195 edge_config = mask; 196 edge_insensitive = 0; 197 break; 198 case IRQ_TYPE_EDGE_FALLING: 199 level = 0; 200 edge_config = 0; 201 edge_insensitive = 0; 202 break; 203 case IRQ_TYPE_EDGE_RISING: 204 level = 0; 205 edge_config = mask; 206 edge_insensitive = 0; 207 break; 208 case IRQ_TYPE_EDGE_BOTH: 209 level = 0; 210 edge_config = 0; /* don't care, but want known value */ 211 edge_insensitive = mask; 212 break; 213 default: 214 return -EINVAL; 215 } 216 217 guard(gpio_generic_lock_irqsave)(&bank->chip); 218 219 iedge_config = gpio_generic_read_reg(&bank->chip, 220 priv->reg_base + GIO_EC(bank->id)) & ~mask; 221 iedge_insensitive = gpio_generic_read_reg(&bank->chip, 222 priv->reg_base + GIO_EI(bank->id)) & ~mask; 223 ilevel = gpio_generic_read_reg(&bank->chip, 224 priv->reg_base + GIO_LEVEL(bank->id)) & ~mask; 225 226 gpio_generic_write_reg(&bank->chip, 227 priv->reg_base + GIO_EC(bank->id), 228 iedge_config | edge_config); 229 gpio_generic_write_reg(&bank->chip, 230 priv->reg_base + GIO_EI(bank->id), 231 iedge_insensitive | edge_insensitive); 232 gpio_generic_write_reg(&bank->chip, 233 priv->reg_base + GIO_LEVEL(bank->id), 234 ilevel | level); 235 236 return 0; 237 } 238 239 static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv, 240 unsigned int enable) 241 { 242 int ret = 0; 243 244 if (priv->parent_wake_irq == priv->parent_irq) 245 return ret; 246 247 if (enable) 248 ret = enable_irq_wake(priv->parent_wake_irq); 249 else 250 ret = disable_irq_wake(priv->parent_wake_irq); 251 if (ret) 252 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n", 253 str_enable_disable(enable)); 254 return ret; 255 } 256 257 static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) 258 { 259 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 260 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 261 struct brcmstb_gpio_priv *priv = bank->parent_priv; 262 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(irqd_to_hwirq(d), bank)); 263 264 /* 265 * Do not do anything specific for now, suspend/resume callbacks will 266 * configure the interrupt mask appropriately 267 */ 268 if (enable) 269 bank->wake_active |= mask; 270 else 271 bank->wake_active &= ~mask; 272 273 return brcmstb_gpio_priv_set_wake(priv, enable); 274 } 275 276 static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data) 277 { 278 struct brcmstb_gpio_priv *priv = data; 279 280 if (!priv || irq != priv->parent_wake_irq) 281 return IRQ_NONE; 282 283 /* Nothing to do */ 284 return IRQ_HANDLED; 285 } 286 287 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank) 288 { 289 struct brcmstb_gpio_priv *priv = bank->parent_priv; 290 struct irq_domain *domain = priv->irq_domain; 291 int hwbase = bank->chip.gc.offset; 292 unsigned long status; 293 294 while ((status = brcmstb_gpio_get_active_irqs(bank))) { 295 unsigned int offset; 296 297 if (priv->suspended && bank->wake_active & status) { 298 priv->suspended = false; 299 pm_wakeup_event(&priv->pdev->dev, 0); 300 } 301 302 for_each_set_bit(offset, &status, 32) { 303 if (offset >= bank->width) 304 dev_warn(&priv->pdev->dev, 305 "IRQ for invalid GPIO (bank=%d, offset=%d)\n", 306 bank->id, offset); 307 generic_handle_domain_irq(domain, hwbase + offset); 308 } 309 } 310 } 311 312 /* Each UPG GIO block has one IRQ for all banks */ 313 static void brcmstb_gpio_irq_handler(struct irq_desc *desc) 314 { 315 struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc); 316 struct irq_chip *chip = irq_desc_get_chip(desc); 317 struct brcmstb_gpio_bank *bank; 318 319 /* Interrupts weren't properly cleared during probe */ 320 BUG_ON(!priv || !chip); 321 322 chained_irq_enter(chip, desc); 323 list_for_each_entry(bank, &priv->bank_list, node) 324 brcmstb_gpio_irq_bank_handler(bank); 325 chained_irq_exit(chip, desc); 326 } 327 328 static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank( 329 struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq) 330 { 331 struct brcmstb_gpio_bank *bank; 332 333 list_for_each_entry(bank, &priv->bank_list, node) { 334 if (hwirq >= bank->chip.gc.offset && 335 hwirq < (bank->chip.gc.offset + bank->chip.gc.ngpio)) 336 return bank; 337 } 338 return NULL; 339 } 340 341 /* 342 * This lock class tells lockdep that GPIO irqs are in a different 343 * category than their parents, so it won't report false recursion. 344 */ 345 static struct lock_class_key brcmstb_gpio_irq_lock_class; 346 static struct lock_class_key brcmstb_gpio_irq_request_class; 347 348 349 static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq, 350 irq_hw_number_t hwirq) 351 { 352 struct brcmstb_gpio_priv *priv = d->host_data; 353 struct brcmstb_gpio_bank *bank = 354 brcmstb_gpio_hwirq_to_bank(priv, hwirq); 355 struct platform_device *pdev = priv->pdev; 356 int ret; 357 358 if (!bank) 359 return -EINVAL; 360 361 dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n", 362 irq, (int)hwirq, bank->id); 363 ret = irq_set_chip_data(irq, &bank->chip.gc); 364 if (ret < 0) 365 return ret; 366 irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class, 367 &brcmstb_gpio_irq_request_class); 368 irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq); 369 irq_set_noprobe(irq); 370 return 0; 371 } 372 373 static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq) 374 { 375 irq_set_chip_and_handler(irq, NULL, NULL); 376 irq_set_chip_data(irq, NULL); 377 } 378 379 static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = { 380 .map = brcmstb_gpio_irq_map, 381 .unmap = brcmstb_gpio_irq_unmap, 382 .xlate = irq_domain_xlate_twocell, 383 }; 384 385 /* Make sure that the number of banks matches up between properties */ 386 static int brcmstb_gpio_sanity_check_banks(struct device *dev, 387 struct device_node *np, struct resource *res) 388 { 389 int res_num_banks = resource_size(res) / GIO_BANK_SIZE; 390 int num_banks = 391 of_property_count_u32_elems(np, "brcm,gpio-bank-widths"); 392 393 if (res_num_banks != num_banks) { 394 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n", 395 res_num_banks, num_banks); 396 return -EINVAL; 397 } else { 398 return 0; 399 } 400 } 401 402 static void brcmstb_gpio_remove(struct platform_device *pdev) 403 { 404 struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev); 405 struct brcmstb_gpio_bank *bank; 406 int offset, virq; 407 408 if (priv->parent_irq > 0) 409 irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL); 410 411 /* Remove all IRQ mappings and delete the domain */ 412 if (priv->irq_domain) { 413 for (offset = 0; offset < priv->num_gpios; offset++) { 414 virq = irq_find_mapping(priv->irq_domain, offset); 415 irq_dispose_mapping(virq); 416 } 417 irq_domain_remove(priv->irq_domain); 418 } 419 420 /* 421 * You can lose return values below, but we report all errors, and it's 422 * more important to actually perform all of the steps. 423 */ 424 list_for_each_entry(bank, &priv->bank_list, node) 425 gpiochip_remove(&bank->chip.gc); 426 } 427 428 static int brcmstb_gpio_of_xlate(struct gpio_chip *gc, 429 const struct of_phandle_args *gpiospec, u32 *flags) 430 { 431 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc); 432 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 433 int offset; 434 435 if (gc->of_gpio_n_cells != 2) { 436 WARN_ON(1); 437 return -EINVAL; 438 } 439 440 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells)) 441 return -EINVAL; 442 443 offset = gpiospec->args[0] - bank->chip.gc.offset; 444 if (offset >= gc->ngpio || offset < 0) 445 return -EINVAL; 446 447 if (unlikely(offset >= bank->width)) { 448 dev_warn_ratelimited(&priv->pdev->dev, 449 "Received request for invalid GPIO offset %d\n", 450 gpiospec->args[0]); 451 } 452 453 if (flags) 454 *flags = gpiospec->args[1]; 455 456 return offset; 457 } 458 459 /* priv->parent_irq and priv->num_gpios must be set before calling */ 460 static int brcmstb_gpio_irq_setup(struct platform_device *pdev, 461 struct brcmstb_gpio_priv *priv) 462 { 463 struct device *dev = &pdev->dev; 464 struct device_node *np = dev->of_node; 465 int err; 466 467 priv->irq_domain = irq_domain_create_linear(dev_fwnode(dev), priv->num_gpios, 468 &brcmstb_gpio_irq_domain_ops, priv); 469 if (!priv->irq_domain) { 470 dev_err(dev, "Couldn't allocate IRQ domain\n"); 471 return -ENXIO; 472 } 473 474 if (of_property_read_bool(np, "wakeup-source")) { 475 /* 476 * Set wakeup capability so we can process boot-time 477 * "wakeups" (e.g., from S5 cold boot). 478 */ 479 device_set_wakeup_capable(dev, true); 480 device_wakeup_enable(dev); 481 priv->parent_wake_irq = platform_get_irq(pdev, 1); 482 if (priv->parent_wake_irq < 0) { 483 priv->parent_wake_irq = priv->parent_irq; 484 dev_warn(dev, 485 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep"); 486 } else { 487 err = devm_request_irq(dev, priv->parent_wake_irq, 488 brcmstb_gpio_wake_irq_handler, 489 IRQF_SHARED, 490 "brcmstb-gpio-wake", priv); 491 492 if (err < 0) { 493 dev_err(dev, "Couldn't request wake IRQ"); 494 goto out_free_domain; 495 } 496 } 497 priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake; 498 } 499 500 priv->irq_chip.name = dev_name(dev); 501 priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask; 502 priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask; 503 priv->irq_chip.irq_mask_ack = brcmstb_gpio_irq_mask_ack; 504 priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask; 505 priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack; 506 priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type; 507 508 irq_set_chained_handler_and_data(priv->parent_irq, 509 brcmstb_gpio_irq_handler, priv); 510 irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY); 511 512 return 0; 513 514 out_free_domain: 515 irq_domain_remove(priv->irq_domain); 516 517 return err; 518 } 519 520 static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv, 521 struct brcmstb_gpio_bank *bank) 522 { 523 unsigned int i; 524 525 for (i = 0; i < GIO_REG_STAT; i++) 526 bank->saved_regs[i] = gpio_generic_read_reg(&bank->chip, 527 priv->reg_base + GIO_BANK_OFF(bank->id, i)); 528 } 529 530 static void brcmstb_gpio_quiesce(struct brcmstb_gpio_priv *priv, bool save) 531 { 532 struct brcmstb_gpio_bank *bank; 533 u32 imask; 534 535 list_for_each_entry(bank, &priv->bank_list, node) { 536 if (save) 537 brcmstb_gpio_bank_save(priv, bank); 538 539 /* Unmask GPIOs which have been flagged as wake-up sources */ 540 if (priv->parent_wake_irq) 541 imask = bank->wake_active; 542 else 543 imask = 0; 544 gpio_generic_write_reg(&bank->chip, 545 priv->reg_base + GIO_MASK(bank->id), 546 imask); 547 } 548 } 549 550 static void brcmstb_gpio_shutdown(struct platform_device *pdev) 551 { 552 struct brcmstb_gpio_priv *priv = dev_get_drvdata(&pdev->dev); 553 554 if (priv->parent_irq > 0) 555 disable_irq(priv->parent_irq); 556 557 /* Enable GPIO for S5 cold boot */ 558 brcmstb_gpio_quiesce(priv, false); 559 } 560 561 static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv, 562 struct brcmstb_gpio_bank *bank) 563 { 564 unsigned int i; 565 566 for (i = 0; i < GIO_REG_STAT; i++) 567 gpio_generic_write_reg(&bank->chip, 568 priv->reg_base + GIO_BANK_OFF(bank->id, i), 569 bank->saved_regs[i]); 570 } 571 572 static int brcmstb_gpio_suspend(struct device *dev) 573 { 574 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev); 575 576 if (priv->parent_irq > 0) 577 priv->suspended = true; 578 579 return 0; 580 } 581 582 static int brcmstb_gpio_suspend_noirq(struct device *dev) 583 { 584 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev); 585 586 /* Catch any wakeup sources occurring between suspend and noirq */ 587 if (!priv->suspended) 588 return -EBUSY; 589 590 if (priv->parent_irq > 0) 591 disable_irq(priv->parent_irq); 592 593 brcmstb_gpio_quiesce(priv, true); 594 595 if (priv->parent_wake_irq) 596 enable_irq(priv->parent_irq); 597 598 return 0; 599 } 600 601 static int brcmstb_gpio_resume(struct device *dev) 602 { 603 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev); 604 struct brcmstb_gpio_bank *bank; 605 606 if (priv->parent_wake_irq) 607 disable_irq(priv->parent_irq); 608 609 priv->suspended = false; 610 611 list_for_each_entry(bank, &priv->bank_list, node) 612 brcmstb_gpio_bank_restore(priv, bank); 613 614 if (priv->parent_irq > 0) 615 enable_irq(priv->parent_irq); 616 617 return 0; 618 } 619 620 static const struct dev_pm_ops brcmstb_gpio_pm_ops = { 621 .suspend = pm_sleep_ptr(brcmstb_gpio_suspend), 622 .suspend_noirq = pm_sleep_ptr(brcmstb_gpio_suspend_noirq), 623 .resume_noirq = pm_sleep_ptr(brcmstb_gpio_resume), 624 }; 625 626 static int brcmstb_gpio_probe(struct platform_device *pdev) 627 { 628 struct gpio_generic_chip_config config; 629 struct device *dev = &pdev->dev; 630 struct device_node *np = dev->of_node; 631 void __iomem *reg_base; 632 struct brcmstb_gpio_priv *priv; 633 struct resource *res; 634 u32 bank_width; 635 int num_banks = 0; 636 int num_gpios = 0; 637 int err; 638 unsigned long flags = 0; 639 bool need_wakeup_event = false; 640 641 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 642 if (!priv) 643 return -ENOMEM; 644 platform_set_drvdata(pdev, priv); 645 INIT_LIST_HEAD(&priv->bank_list); 646 647 reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 648 if (IS_ERR(reg_base)) 649 return PTR_ERR(reg_base); 650 651 priv->reg_base = reg_base; 652 priv->pdev = pdev; 653 654 if (of_property_read_bool(np, "interrupt-controller")) { 655 priv->parent_irq = platform_get_irq(pdev, 0); 656 if (priv->parent_irq <= 0) 657 return -ENOENT; 658 } else { 659 priv->parent_irq = -ENOENT; 660 } 661 662 if (brcmstb_gpio_sanity_check_banks(dev, np, res)) 663 return -EINVAL; 664 665 /* 666 * MIPS endianness is configured by boot strap, which also reverses all 667 * bus endianness (i.e., big-endian CPU + big endian bus ==> native 668 * endian I/O). 669 * 670 * Other architectures (e.g., ARM) either do not support big endian, or 671 * else leave I/O in little endian mode. 672 */ 673 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN) 674 flags = GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER; 675 #endif 676 677 of_property_for_each_u32(np, "brcm,gpio-bank-widths", bank_width) { 678 struct brcmstb_gpio_bank *bank; 679 struct gpio_chip *gc; 680 681 /* 682 * If bank_width is 0, then there is an empty bank in the 683 * register block. Special handling for this case. 684 */ 685 if (bank_width == 0) { 686 dev_dbg(dev, "Width 0 found: Empty bank @ %d\n", 687 num_banks); 688 num_banks++; 689 num_gpios += MAX_GPIO_PER_BANK; 690 continue; 691 } 692 693 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); 694 if (!bank) { 695 err = -ENOMEM; 696 goto fail; 697 } 698 699 bank->parent_priv = priv; 700 bank->id = num_banks; 701 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) { 702 dev_err(dev, "Invalid bank width %d\n", bank_width); 703 err = -EINVAL; 704 goto fail; 705 } else { 706 bank->width = bank_width; 707 } 708 709 gc = &bank->chip.gc; 710 711 /* 712 * Regs are 4 bytes wide, have data reg, no set/clear regs, 713 * and direction bits have 0 = output and 1 = input 714 */ 715 716 config = (struct gpio_generic_chip_config) { 717 .dev = dev, 718 .sz = 4, 719 .dat = reg_base + GIO_DATA(bank->id), 720 .dirin = reg_base + GIO_IODIR(bank->id), 721 .flags = flags, 722 }; 723 724 err = gpio_generic_chip_init(&bank->chip, &config); 725 if (err) { 726 dev_err(dev, "failed to initialize generic GPIO chip\n"); 727 goto fail; 728 } 729 730 gc->owner = THIS_MODULE; 731 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np); 732 if (!gc->label) { 733 err = -ENOMEM; 734 goto fail; 735 } 736 gc->of_gpio_n_cells = 2; 737 gc->of_xlate = brcmstb_gpio_of_xlate; 738 /* not all ngpio lines are valid, will use bank width later */ 739 gc->ngpio = MAX_GPIO_PER_BANK; 740 gc->offset = bank->id * MAX_GPIO_PER_BANK; 741 gc->request = gpiochip_generic_request; 742 gc->free = gpiochip_generic_free; 743 if (priv->parent_irq > 0) 744 gc->to_irq = brcmstb_gpio_to_irq; 745 746 /* 747 * Mask all interrupts by default, since wakeup interrupts may 748 * be retained from S5 cold boot 749 */ 750 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank); 751 gpio_generic_write_reg(&bank->chip, 752 reg_base + GIO_MASK(bank->id), 0); 753 754 err = gpiochip_add_data(gc, bank); 755 if (err) { 756 dev_err(dev, "Could not add gpiochip for bank %d\n", 757 bank->id); 758 goto fail; 759 } 760 num_gpios += gc->ngpio; 761 762 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id, 763 gc->base, gc->ngpio, bank->width); 764 765 /* Everything looks good, so add bank to list */ 766 list_add(&bank->node, &priv->bank_list); 767 768 num_banks++; 769 } 770 771 priv->num_gpios = num_gpios; 772 if (priv->parent_irq > 0) { 773 err = brcmstb_gpio_irq_setup(pdev, priv); 774 if (err) 775 goto fail; 776 } 777 778 if (priv->parent_wake_irq && need_wakeup_event) 779 pm_wakeup_event(dev, 0); 780 781 return 0; 782 783 fail: 784 (void) brcmstb_gpio_remove(pdev); 785 return err; 786 } 787 788 static const struct of_device_id brcmstb_gpio_of_match[] = { 789 { .compatible = "brcm,brcmstb-gpio" }, 790 {}, 791 }; 792 793 MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match); 794 795 static struct platform_driver brcmstb_gpio_driver = { 796 .driver = { 797 .name = "brcmstb-gpio", 798 .of_match_table = brcmstb_gpio_of_match, 799 .pm = pm_sleep_ptr(&brcmstb_gpio_pm_ops), 800 }, 801 .probe = brcmstb_gpio_probe, 802 .remove = brcmstb_gpio_remove, 803 .shutdown = brcmstb_gpio_shutdown, 804 }; 805 module_platform_driver(brcmstb_gpio_driver); 806 807 MODULE_AUTHOR("Gregory Fong"); 808 MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO"); 809 MODULE_LICENSE("GPL v2"); 810