xref: /linux/drivers/gpio/gpio-bcm-kona.c (revision 7a9b709e7cc5ce1ffb84ce07bf6d157e1de758df) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Broadcom Kona GPIO Driver
4  *
5  * Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>
6  * Copyright (C) 2012-2014 Broadcom Corporation
7  */
8 
9 #include <linux/bitops.h>
10 #include <linux/cleanup.h>
11 #include <linux/err.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/init.h>
14 #include <linux/io.h>
15 #include <linux/irqdomain.h>
16 #include <linux/irqchip/chained_irq.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/platform_device.h>
19 #include <linux/property.h>
20 
21 #define BCM_GPIO_PASSWD				0x00a5a501
22 #define GPIO_PER_BANK				32
23 #define GPIO_MAX_BANK_NUM			8
24 
25 #define GPIO_BANK(gpio)				((gpio) >> 5)
26 #define GPIO_BIT(gpio)				((gpio) & (GPIO_PER_BANK - 1))
27 
28 /* There is a GPIO control register for each GPIO */
29 #define GPIO_CONTROL(gpio)			(0x00000100 + ((gpio) << 2))
30 
31 /* The remaining registers are per GPIO bank */
32 #define GPIO_OUT_STATUS(bank)			(0x00000000 + ((bank) << 2))
33 #define GPIO_IN_STATUS(bank)			(0x00000020 + ((bank) << 2))
34 #define GPIO_OUT_SET(bank)			(0x00000040 + ((bank) << 2))
35 #define GPIO_OUT_CLEAR(bank)			(0x00000060 + ((bank) << 2))
36 #define GPIO_INT_STATUS(bank)			(0x00000080 + ((bank) << 2))
37 #define GPIO_INT_MASK(bank)			(0x000000a0 + ((bank) << 2))
38 #define GPIO_INT_MSKCLR(bank)			(0x000000c0 + ((bank) << 2))
39 #define GPIO_PWD_STATUS(bank)			(0x00000500 + ((bank) << 2))
40 
41 #define GPIO_GPPWR_OFFSET			0x00000520
42 
43 #define GPIO_GPCTR0_DBR_SHIFT			5
44 #define GPIO_GPCTR0_DBR_MASK			0x000001e0
45 
46 #define GPIO_GPCTR0_ITR_SHIFT			3
47 #define GPIO_GPCTR0_ITR_MASK			0x00000018
48 #define GPIO_GPCTR0_ITR_CMD_RISING_EDGE		0x00000001
49 #define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE	0x00000002
50 #define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE		0x00000003
51 
52 #define GPIO_GPCTR0_IOTR_MASK			0x00000001
53 #define GPIO_GPCTR0_IOTR_CMD_0UTPUT		0x00000000
54 #define GPIO_GPCTR0_IOTR_CMD_INPUT		0x00000001
55 
56 #define GPIO_GPCTR0_DB_ENABLE_MASK		0x00000100
57 
58 #define LOCK_CODE				0xffffffff
59 #define UNLOCK_CODE				0x00000000
60 
61 struct bcm_kona_gpio {
62 	void __iomem *reg_base;
63 	int num_bank;
64 	raw_spinlock_t lock;
65 	struct gpio_chip gpio_chip;
66 	struct irq_domain *irq_domain;
67 	struct bcm_kona_gpio_bank *banks;
68 };
69 
70 struct bcm_kona_gpio_bank {
71 	int id;
72 	int irq;
73 	/*
74 	 * Used to keep track of lock/unlock operations for each GPIO in the
75 	 * bank.
76 	 *
77 	 * All GPIOs are locked by default (see bcm_kona_gpio_reset), and the
78 	 * unlock count for all GPIOs is 0 by default. Each unlock increments
79 	 * the counter, and each lock decrements the counter.
80 	 *
81 	 * The lock function only locks the GPIO once its unlock counter is
82 	 * down to 0. This is necessary because the GPIO is unlocked in two
83 	 * places in this driver: once for requested GPIOs, and once for
84 	 * requested IRQs. Since it is possible for a GPIO to be requested
85 	 * as both a GPIO and an IRQ, we need to ensure that we don't lock it
86 	 * too early.
87 	 */
88 	u8 gpio_unlock_count[GPIO_PER_BANK];
89 	/* Used in the interrupt handler */
90 	struct bcm_kona_gpio *kona_gpio;
91 };
92 
93 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
94 						int bank_id, u32 lockcode)
95 {
96 	writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
97 	writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
98 }
99 
100 static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
101 					unsigned gpio)
102 {
103 	u32 val;
104 	int bank_id = GPIO_BANK(gpio);
105 	int bit = GPIO_BIT(gpio);
106 	struct bcm_kona_gpio_bank *bank = &kona_gpio->banks[bank_id];
107 
108 	if (bank->gpio_unlock_count[bit] == 0) {
109 		dev_err(kona_gpio->gpio_chip.parent,
110 			"Unbalanced locks for GPIO %u\n", gpio);
111 		return;
112 	}
113 
114 	if (--bank->gpio_unlock_count[bit] == 0) {
115 		guard(raw_spinlock_irqsave)(&kona_gpio->lock);
116 
117 		val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
118 		val |= BIT(bit);
119 		bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
120 	}
121 }
122 
123 static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
124 					unsigned gpio)
125 {
126 	u32 val;
127 	int bank_id = GPIO_BANK(gpio);
128 	int bit = GPIO_BIT(gpio);
129 	struct bcm_kona_gpio_bank *bank = &kona_gpio->banks[bank_id];
130 
131 	if (bank->gpio_unlock_count[bit] == 0) {
132 		guard(raw_spinlock_irqsave)(&kona_gpio->lock);
133 
134 		val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
135 		val &= ~BIT(bit);
136 		bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
137 	}
138 
139 	++bank->gpio_unlock_count[bit];
140 }
141 
142 static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
143 {
144 	struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
145 	void __iomem *reg_base = kona_gpio->reg_base;
146 	u32 val;
147 
148 	val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
149 	return val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
150 }
151 
152 static int bcm_kona_gpio_set(struct gpio_chip *chip, unsigned int gpio,
153 			     int value)
154 {
155 	struct bcm_kona_gpio *kona_gpio;
156 	void __iomem *reg_base;
157 	int bank_id = GPIO_BANK(gpio);
158 	int bit = GPIO_BIT(gpio);
159 	u32 val, reg_offset;
160 
161 	kona_gpio = gpiochip_get_data(chip);
162 	reg_base = kona_gpio->reg_base;
163 
164 	guard(raw_spinlock_irqsave)(&kona_gpio->lock);
165 
166 	/* this function only applies to output pin */
167 	if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
168 		return 0;
169 
170 	reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
171 
172 	val = readl(reg_base + reg_offset);
173 	val |= BIT(bit);
174 	writel(val, reg_base + reg_offset);
175 
176 	return 0;
177 }
178 
179 static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
180 {
181 	struct bcm_kona_gpio *kona_gpio;
182 	void __iomem *reg_base;
183 	int bank_id = GPIO_BANK(gpio);
184 	int bit = GPIO_BIT(gpio);
185 	u32 val, reg_offset;
186 
187 	kona_gpio = gpiochip_get_data(chip);
188 	reg_base = kona_gpio->reg_base;
189 
190 	guard(raw_spinlock_irqsave)(&kona_gpio->lock);
191 
192 	if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
193 		reg_offset = GPIO_IN_STATUS(bank_id);
194 	else
195 		reg_offset = GPIO_OUT_STATUS(bank_id);
196 
197 	/* read the GPIO bank status */
198 	val = readl(reg_base + reg_offset);
199 
200 	/* return the specified bit status */
201 	return !!(val & BIT(bit));
202 }
203 
204 static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
205 {
206 	struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
207 
208 	bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
209 	return 0;
210 }
211 
212 static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
213 {
214 	struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
215 
216 	bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
217 }
218 
219 static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
220 {
221 	struct bcm_kona_gpio *kona_gpio;
222 	void __iomem *reg_base;
223 	u32 val;
224 
225 	kona_gpio = gpiochip_get_data(chip);
226 	reg_base = kona_gpio->reg_base;
227 
228 	guard(raw_spinlock_irqsave)(&kona_gpio->lock);
229 
230 	val = readl(reg_base + GPIO_CONTROL(gpio));
231 	val &= ~GPIO_GPCTR0_IOTR_MASK;
232 	val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
233 	writel(val, reg_base + GPIO_CONTROL(gpio));
234 
235 	return 0;
236 }
237 
238 static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
239 					  unsigned gpio, int value)
240 {
241 	struct bcm_kona_gpio *kona_gpio;
242 	void __iomem *reg_base;
243 	int bank_id = GPIO_BANK(gpio);
244 	int bit = GPIO_BIT(gpio);
245 	u32 val, reg_offset;
246 
247 	kona_gpio = gpiochip_get_data(chip);
248 	reg_base = kona_gpio->reg_base;
249 
250 	guard(raw_spinlock_irqsave)(&kona_gpio->lock);
251 
252 	val = readl(reg_base + GPIO_CONTROL(gpio));
253 	val &= ~GPIO_GPCTR0_IOTR_MASK;
254 	val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
255 	writel(val, reg_base + GPIO_CONTROL(gpio));
256 	reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
257 
258 	val = readl(reg_base + reg_offset);
259 	val |= BIT(bit);
260 	writel(val, reg_base + reg_offset);
261 
262 	return 0;
263 }
264 
265 static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
266 {
267 	struct bcm_kona_gpio *kona_gpio;
268 
269 	kona_gpio = gpiochip_get_data(chip);
270 	if (gpio >= kona_gpio->gpio_chip.ngpio)
271 		return -ENXIO;
272 	return irq_create_mapping(kona_gpio->irq_domain, gpio);
273 }
274 
275 static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
276 				      unsigned debounce)
277 {
278 	struct bcm_kona_gpio *kona_gpio;
279 	void __iomem *reg_base;
280 	u32 val, res;
281 
282 	kona_gpio = gpiochip_get_data(chip);
283 	reg_base = kona_gpio->reg_base;
284 	/* debounce must be 1-128ms (or 0) */
285 	if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
286 		dev_err(chip->parent, "Debounce value %u not in range\n",
287 			debounce);
288 		return -EINVAL;
289 	}
290 
291 	/* calculate debounce bit value */
292 	if (debounce != 0) {
293 		/* Convert to ms */
294 		debounce /= 1000;
295 		/* find the MSB */
296 		res = fls(debounce) - 1;
297 		/* Check if MSB-1 is set (round up or down) */
298 		if (res > 0 && (debounce & BIT(res - 1)))
299 			res++;
300 	}
301 
302 	/* spin lock for read-modify-write of the GPIO register */
303 	guard(raw_spinlock_irqsave)(&kona_gpio->lock);
304 
305 	val = readl(reg_base + GPIO_CONTROL(gpio));
306 	val &= ~GPIO_GPCTR0_DBR_MASK;
307 
308 	if (debounce == 0) {
309 		/* disable debounce */
310 		val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
311 	} else {
312 		val |= GPIO_GPCTR0_DB_ENABLE_MASK |
313 		    (res << GPIO_GPCTR0_DBR_SHIFT);
314 	}
315 
316 	writel(val, reg_base + GPIO_CONTROL(gpio));
317 
318 	return 0;
319 }
320 
321 static int bcm_kona_gpio_set_config(struct gpio_chip *chip, unsigned gpio,
322 				    unsigned long config)
323 {
324 	u32 debounce;
325 
326 	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
327 		return -ENOTSUPP;
328 
329 	debounce = pinconf_to_config_argument(config);
330 	return bcm_kona_gpio_set_debounce(chip, gpio, debounce);
331 }
332 
333 static const struct gpio_chip template_chip = {
334 	.label = "bcm-kona-gpio",
335 	.owner = THIS_MODULE,
336 	.request = bcm_kona_gpio_request,
337 	.free = bcm_kona_gpio_free,
338 	.get_direction = bcm_kona_gpio_get_dir,
339 	.direction_input = bcm_kona_gpio_direction_input,
340 	.get = bcm_kona_gpio_get,
341 	.direction_output = bcm_kona_gpio_direction_output,
342 	.set_rv = bcm_kona_gpio_set,
343 	.set_config = bcm_kona_gpio_set_config,
344 	.to_irq = bcm_kona_gpio_to_irq,
345 	.base = 0,
346 };
347 
348 static void bcm_kona_gpio_irq_ack(struct irq_data *d)
349 {
350 	struct bcm_kona_gpio *kona_gpio;
351 	void __iomem *reg_base;
352 	unsigned gpio = d->hwirq;
353 	int bank_id = GPIO_BANK(gpio);
354 	int bit = GPIO_BIT(gpio);
355 	u32 val;
356 
357 	kona_gpio = irq_data_get_irq_chip_data(d);
358 	reg_base = kona_gpio->reg_base;
359 
360 	guard(raw_spinlock_irqsave)(&kona_gpio->lock);
361 
362 	val = readl(reg_base + GPIO_INT_STATUS(bank_id));
363 	val |= BIT(bit);
364 	writel(val, reg_base + GPIO_INT_STATUS(bank_id));
365 }
366 
367 static void bcm_kona_gpio_irq_mask(struct irq_data *d)
368 {
369 	struct bcm_kona_gpio *kona_gpio;
370 	void __iomem *reg_base;
371 	unsigned gpio = d->hwirq;
372 	int bank_id = GPIO_BANK(gpio);
373 	int bit = GPIO_BIT(gpio);
374 	u32 val;
375 
376 	kona_gpio = irq_data_get_irq_chip_data(d);
377 	reg_base = kona_gpio->reg_base;
378 
379 	guard(raw_spinlock_irqsave)(&kona_gpio->lock);
380 
381 	val = readl(reg_base + GPIO_INT_MASK(bank_id));
382 	val |= BIT(bit);
383 	writel(val, reg_base + GPIO_INT_MASK(bank_id));
384 	gpiochip_disable_irq(&kona_gpio->gpio_chip, gpio);
385 }
386 
387 static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
388 {
389 	struct bcm_kona_gpio *kona_gpio;
390 	void __iomem *reg_base;
391 	unsigned gpio = d->hwirq;
392 	int bank_id = GPIO_BANK(gpio);
393 	int bit = GPIO_BIT(gpio);
394 	u32 val;
395 
396 	kona_gpio = irq_data_get_irq_chip_data(d);
397 	reg_base = kona_gpio->reg_base;
398 
399 	guard(raw_spinlock_irqsave)(&kona_gpio->lock);
400 
401 	val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
402 	val |= BIT(bit);
403 	writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
404 	gpiochip_enable_irq(&kona_gpio->gpio_chip, gpio);
405 }
406 
407 static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
408 {
409 	struct bcm_kona_gpio *kona_gpio;
410 	void __iomem *reg_base;
411 	unsigned gpio = d->hwirq;
412 	u32 lvl_type;
413 	u32 val;
414 
415 	kona_gpio = irq_data_get_irq_chip_data(d);
416 	reg_base = kona_gpio->reg_base;
417 	switch (type & IRQ_TYPE_SENSE_MASK) {
418 	case IRQ_TYPE_EDGE_RISING:
419 		lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
420 		break;
421 
422 	case IRQ_TYPE_EDGE_FALLING:
423 		lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
424 		break;
425 
426 	case IRQ_TYPE_EDGE_BOTH:
427 		lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
428 		break;
429 
430 	case IRQ_TYPE_LEVEL_HIGH:
431 	case IRQ_TYPE_LEVEL_LOW:
432 		/* BCM GPIO doesn't support level triggering */
433 	default:
434 		dev_err(kona_gpio->gpio_chip.parent,
435 			"Invalid BCM GPIO irq type 0x%x\n", type);
436 		return -EINVAL;
437 	}
438 
439 	guard(raw_spinlock_irqsave)(&kona_gpio->lock);
440 
441 	val = readl(reg_base + GPIO_CONTROL(gpio));
442 	val &= ~GPIO_GPCTR0_ITR_MASK;
443 	val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
444 	writel(val, reg_base + GPIO_CONTROL(gpio));
445 
446 	return 0;
447 }
448 
449 static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
450 {
451 	void __iomem *reg_base;
452 	int bit, bank_id;
453 	unsigned long sta;
454 	struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
455 	struct irq_chip *chip = irq_desc_get_chip(desc);
456 
457 	chained_irq_enter(chip, desc);
458 
459 	/*
460 	 * For bank interrupts, we can't use chip_data to store the kona_gpio
461 	 * pointer, since GIC needs it for its own purposes. Therefore, we get
462 	 * our pointer from the bank structure.
463 	 */
464 	reg_base = bank->kona_gpio->reg_base;
465 	bank_id = bank->id;
466 
467 	while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
468 		    (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
469 		for_each_set_bit(bit, &sta, 32) {
470 			int hwirq = GPIO_PER_BANK * bank_id + bit;
471 			/*
472 			 * Clear interrupt before handler is called so we don't
473 			 * miss any interrupt occurred during executing them.
474 			 */
475 			writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
476 			       BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
477 			/* Invoke interrupt handler */
478 			generic_handle_domain_irq(bank->kona_gpio->irq_domain,
479 						  hwirq);
480 		}
481 	}
482 
483 	chained_irq_exit(chip, desc);
484 }
485 
486 static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
487 {
488 	struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
489 	unsigned int gpio = d->hwirq;
490 
491 	/*
492 	 * We need to unlock the GPIO before any other operations are performed
493 	 * on the relevant GPIO configuration registers
494 	 */
495 	bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
496 
497 	return gpiochip_reqres_irq(&kona_gpio->gpio_chip, gpio);
498 }
499 
500 static void bcm_kona_gpio_irq_relres(struct irq_data *d)
501 {
502 	struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
503 	unsigned int gpio = d->hwirq;
504 
505 	/* Once we no longer use it, lock the GPIO again */
506 	bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
507 
508 	gpiochip_relres_irq(&kona_gpio->gpio_chip, gpio);
509 }
510 
511 static struct irq_chip bcm_gpio_irq_chip = {
512 	.name = "bcm-kona-gpio",
513 	.irq_ack = bcm_kona_gpio_irq_ack,
514 	.irq_mask = bcm_kona_gpio_irq_mask,
515 	.irq_unmask = bcm_kona_gpio_irq_unmask,
516 	.irq_set_type = bcm_kona_gpio_irq_set_type,
517 	.irq_request_resources = bcm_kona_gpio_irq_reqres,
518 	.irq_release_resources = bcm_kona_gpio_irq_relres,
519 };
520 
521 static struct of_device_id const bcm_kona_gpio_of_match[] = {
522 	{ .compatible = "brcm,kona-gpio" },
523 	{}
524 };
525 
526 /*
527  * This lock class tells lockdep that GPIO irqs are in a different
528  * category than their parents, so it won't report false recursion.
529  */
530 static struct lock_class_key gpio_lock_class;
531 static struct lock_class_key gpio_request_class;
532 
533 static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
534 				 irq_hw_number_t hwirq)
535 {
536 	int ret;
537 
538 	ret = irq_set_chip_data(irq, d->host_data);
539 	if (ret < 0)
540 		return ret;
541 	irq_set_lockdep_class(irq, &gpio_lock_class, &gpio_request_class);
542 	irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
543 	irq_set_noprobe(irq);
544 
545 	return 0;
546 }
547 
548 static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
549 {
550 	irq_set_chip_and_handler(irq, NULL, NULL);
551 	irq_set_chip_data(irq, NULL);
552 }
553 
554 static const struct irq_domain_ops bcm_kona_irq_ops = {
555 	.map = bcm_kona_gpio_irq_map,
556 	.unmap = bcm_kona_gpio_irq_unmap,
557 	.xlate = irq_domain_xlate_twocell,
558 };
559 
560 static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
561 {
562 	void __iomem *reg_base;
563 	int i;
564 
565 	reg_base = kona_gpio->reg_base;
566 	/* disable interrupts and clear status */
567 	for (i = 0; i < kona_gpio->num_bank; i++) {
568 		/* Unlock the entire bank first */
569 		bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);
570 		writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
571 		writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
572 		/* Now re-lock the bank */
573 		bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);
574 	}
575 }
576 
577 static int bcm_kona_gpio_probe(struct platform_device *pdev)
578 {
579 	struct device *dev = &pdev->dev;
580 	struct bcm_kona_gpio_bank *bank;
581 	struct bcm_kona_gpio *kona_gpio;
582 	struct gpio_chip *chip;
583 	int ret;
584 	int i;
585 
586 	kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
587 	if (!kona_gpio)
588 		return -ENOMEM;
589 
590 	kona_gpio->gpio_chip = template_chip;
591 	chip = &kona_gpio->gpio_chip;
592 	ret = platform_irq_count(pdev);
593 	if (!ret) {
594 		dev_err(dev, "Couldn't determine # GPIO banks\n");
595 		return -ENOENT;
596 	} else if (ret < 0) {
597 		return dev_err_probe(dev, ret, "Couldn't determine GPIO banks\n");
598 	}
599 	kona_gpio->num_bank = ret;
600 
601 	if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
602 		dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
603 			GPIO_MAX_BANK_NUM);
604 		return -ENXIO;
605 	}
606 	kona_gpio->banks = devm_kcalloc(dev,
607 					kona_gpio->num_bank,
608 					sizeof(*kona_gpio->banks),
609 					GFP_KERNEL);
610 	if (!kona_gpio->banks)
611 		return -ENOMEM;
612 
613 	chip->parent = dev;
614 	chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
615 
616 	kona_gpio->irq_domain = irq_domain_create_linear(dev_fwnode(dev),
617 							 chip->ngpio,
618 							 &bcm_kona_irq_ops,
619 							 kona_gpio);
620 	if (!kona_gpio->irq_domain) {
621 		dev_err(dev, "Couldn't allocate IRQ domain\n");
622 		return -ENXIO;
623 	}
624 
625 	kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
626 	if (IS_ERR(kona_gpio->reg_base)) {
627 		ret = PTR_ERR(kona_gpio->reg_base);
628 		goto err_irq_domain;
629 	}
630 
631 	for (i = 0; i < kona_gpio->num_bank; i++) {
632 		bank = &kona_gpio->banks[i];
633 		bank->id = i;
634 		bank->irq = platform_get_irq(pdev, i);
635 		bank->kona_gpio = kona_gpio;
636 		if (bank->irq < 0) {
637 			dev_err(dev, "Couldn't get IRQ for bank %d\n", i);
638 			ret = -ENOENT;
639 			goto err_irq_domain;
640 		}
641 	}
642 
643 	dev_info(&pdev->dev, "Setting up Kona GPIO\n");
644 
645 	bcm_kona_gpio_reset(kona_gpio);
646 
647 	ret = devm_gpiochip_add_data(dev, chip, kona_gpio);
648 	if (ret < 0) {
649 		dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
650 		goto err_irq_domain;
651 	}
652 	for (i = 0; i < kona_gpio->num_bank; i++) {
653 		bank = &kona_gpio->banks[i];
654 		irq_set_chained_handler_and_data(bank->irq,
655 						 bcm_kona_gpio_irq_handler,
656 						 bank);
657 	}
658 
659 	raw_spin_lock_init(&kona_gpio->lock);
660 
661 	return 0;
662 
663 err_irq_domain:
664 	irq_domain_remove(kona_gpio->irq_domain);
665 
666 	return ret;
667 }
668 
669 static struct platform_driver bcm_kona_gpio_driver = {
670 	.driver = {
671 			.name = "bcm-kona-gpio",
672 			.of_match_table = bcm_kona_gpio_of_match,
673 	},
674 	.probe = bcm_kona_gpio_probe,
675 };
676 builtin_platform_driver(bcm_kona_gpio_driver);
677