1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom Kona GPIO Driver 4 * 5 * Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com> 6 * Copyright (C) 2012-2014 Broadcom Corporation 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/err.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/init.h> 13 #include <linux/io.h> 14 #include <linux/irqdomain.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/platform_device.h> 18 #include <linux/property.h> 19 20 #define BCM_GPIO_PASSWD 0x00a5a501 21 #define GPIO_PER_BANK 32 22 #define GPIO_MAX_BANK_NUM 8 23 24 #define GPIO_BANK(gpio) ((gpio) >> 5) 25 #define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1)) 26 27 /* There is a GPIO control register for each GPIO */ 28 #define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2)) 29 30 /* The remaining registers are per GPIO bank */ 31 #define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2)) 32 #define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2)) 33 #define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2)) 34 #define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2)) 35 #define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2)) 36 #define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2)) 37 #define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2)) 38 #define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2)) 39 40 #define GPIO_GPPWR_OFFSET 0x00000520 41 42 #define GPIO_GPCTR0_DBR_SHIFT 5 43 #define GPIO_GPCTR0_DBR_MASK 0x000001e0 44 45 #define GPIO_GPCTR0_ITR_SHIFT 3 46 #define GPIO_GPCTR0_ITR_MASK 0x00000018 47 #define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001 48 #define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002 49 #define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003 50 51 #define GPIO_GPCTR0_IOTR_MASK 0x00000001 52 #define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000 53 #define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001 54 55 #define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100 56 57 #define LOCK_CODE 0xffffffff 58 #define UNLOCK_CODE 0x00000000 59 60 struct bcm_kona_gpio { 61 void __iomem *reg_base; 62 int num_bank; 63 raw_spinlock_t lock; 64 struct gpio_chip gpio_chip; 65 struct irq_domain *irq_domain; 66 struct bcm_kona_gpio_bank *banks; 67 }; 68 69 struct bcm_kona_gpio_bank { 70 int id; 71 int irq; 72 /* 73 * Used to keep track of lock/unlock operations for each GPIO in the 74 * bank. 75 * 76 * All GPIOs are locked by default (see bcm_kona_gpio_reset), and the 77 * unlock count for all GPIOs is 0 by default. Each unlock increments 78 * the counter, and each lock decrements the counter. 79 * 80 * The lock function only locks the GPIO once its unlock counter is 81 * down to 0. This is necessary because the GPIO is unlocked in two 82 * places in this driver: once for requested GPIOs, and once for 83 * requested IRQs. Since it is possible for a GPIO to be requested 84 * as both a GPIO and an IRQ, we need to ensure that we don't lock it 85 * too early. 86 */ 87 u8 gpio_unlock_count[GPIO_PER_BANK]; 88 /* Used in the interrupt handler */ 89 struct bcm_kona_gpio *kona_gpio; 90 }; 91 92 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base, 93 int bank_id, u32 lockcode) 94 { 95 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET); 96 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id)); 97 } 98 99 static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio, 100 unsigned gpio) 101 { 102 u32 val; 103 unsigned long flags; 104 int bank_id = GPIO_BANK(gpio); 105 int bit = GPIO_BIT(gpio); 106 struct bcm_kona_gpio_bank *bank = &kona_gpio->banks[bank_id]; 107 108 if (bank->gpio_unlock_count[bit] == 0) { 109 dev_err(kona_gpio->gpio_chip.parent, 110 "Unbalanced locks for GPIO %u\n", gpio); 111 return; 112 } 113 114 if (--bank->gpio_unlock_count[bit] == 0) { 115 raw_spin_lock_irqsave(&kona_gpio->lock, flags); 116 117 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); 118 val |= BIT(bit); 119 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); 120 121 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 122 } 123 } 124 125 static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio, 126 unsigned gpio) 127 { 128 u32 val; 129 unsigned long flags; 130 int bank_id = GPIO_BANK(gpio); 131 int bit = GPIO_BIT(gpio); 132 struct bcm_kona_gpio_bank *bank = &kona_gpio->banks[bank_id]; 133 134 if (bank->gpio_unlock_count[bit] == 0) { 135 raw_spin_lock_irqsave(&kona_gpio->lock, flags); 136 137 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); 138 val &= ~BIT(bit); 139 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); 140 141 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 142 } 143 144 ++bank->gpio_unlock_count[bit]; 145 } 146 147 static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio) 148 { 149 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip); 150 void __iomem *reg_base = kona_gpio->reg_base; 151 u32 val; 152 153 val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK; 154 return val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; 155 } 156 157 static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) 158 { 159 struct bcm_kona_gpio *kona_gpio; 160 void __iomem *reg_base; 161 int bank_id = GPIO_BANK(gpio); 162 int bit = GPIO_BIT(gpio); 163 u32 val, reg_offset; 164 unsigned long flags; 165 166 kona_gpio = gpiochip_get_data(chip); 167 reg_base = kona_gpio->reg_base; 168 raw_spin_lock_irqsave(&kona_gpio->lock, flags); 169 170 /* this function only applies to output pin */ 171 if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN) 172 goto out; 173 174 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); 175 176 val = readl(reg_base + reg_offset); 177 val |= BIT(bit); 178 writel(val, reg_base + reg_offset); 179 180 out: 181 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 182 } 183 184 static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio) 185 { 186 struct bcm_kona_gpio *kona_gpio; 187 void __iomem *reg_base; 188 int bank_id = GPIO_BANK(gpio); 189 int bit = GPIO_BIT(gpio); 190 u32 val, reg_offset; 191 unsigned long flags; 192 193 kona_gpio = gpiochip_get_data(chip); 194 reg_base = kona_gpio->reg_base; 195 raw_spin_lock_irqsave(&kona_gpio->lock, flags); 196 197 if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN) 198 reg_offset = GPIO_IN_STATUS(bank_id); 199 else 200 reg_offset = GPIO_OUT_STATUS(bank_id); 201 202 /* read the GPIO bank status */ 203 val = readl(reg_base + reg_offset); 204 205 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 206 207 /* return the specified bit status */ 208 return !!(val & BIT(bit)); 209 } 210 211 static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio) 212 { 213 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip); 214 215 bcm_kona_gpio_unlock_gpio(kona_gpio, gpio); 216 return 0; 217 } 218 219 static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio) 220 { 221 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip); 222 223 bcm_kona_gpio_lock_gpio(kona_gpio, gpio); 224 } 225 226 static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 227 { 228 struct bcm_kona_gpio *kona_gpio; 229 void __iomem *reg_base; 230 u32 val; 231 unsigned long flags; 232 233 kona_gpio = gpiochip_get_data(chip); 234 reg_base = kona_gpio->reg_base; 235 raw_spin_lock_irqsave(&kona_gpio->lock, flags); 236 237 val = readl(reg_base + GPIO_CONTROL(gpio)); 238 val &= ~GPIO_GPCTR0_IOTR_MASK; 239 val |= GPIO_GPCTR0_IOTR_CMD_INPUT; 240 writel(val, reg_base + GPIO_CONTROL(gpio)); 241 242 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 243 244 return 0; 245 } 246 247 static int bcm_kona_gpio_direction_output(struct gpio_chip *chip, 248 unsigned gpio, int value) 249 { 250 struct bcm_kona_gpio *kona_gpio; 251 void __iomem *reg_base; 252 int bank_id = GPIO_BANK(gpio); 253 int bit = GPIO_BIT(gpio); 254 u32 val, reg_offset; 255 unsigned long flags; 256 257 kona_gpio = gpiochip_get_data(chip); 258 reg_base = kona_gpio->reg_base; 259 raw_spin_lock_irqsave(&kona_gpio->lock, flags); 260 261 val = readl(reg_base + GPIO_CONTROL(gpio)); 262 val &= ~GPIO_GPCTR0_IOTR_MASK; 263 val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT; 264 writel(val, reg_base + GPIO_CONTROL(gpio)); 265 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); 266 267 val = readl(reg_base + reg_offset); 268 val |= BIT(bit); 269 writel(val, reg_base + reg_offset); 270 271 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 272 273 return 0; 274 } 275 276 static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) 277 { 278 struct bcm_kona_gpio *kona_gpio; 279 280 kona_gpio = gpiochip_get_data(chip); 281 if (gpio >= kona_gpio->gpio_chip.ngpio) 282 return -ENXIO; 283 return irq_create_mapping(kona_gpio->irq_domain, gpio); 284 } 285 286 static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio, 287 unsigned debounce) 288 { 289 struct bcm_kona_gpio *kona_gpio; 290 void __iomem *reg_base; 291 u32 val, res; 292 unsigned long flags; 293 294 kona_gpio = gpiochip_get_data(chip); 295 reg_base = kona_gpio->reg_base; 296 /* debounce must be 1-128ms (or 0) */ 297 if ((debounce > 0 && debounce < 1000) || debounce > 128000) { 298 dev_err(chip->parent, "Debounce value %u not in range\n", 299 debounce); 300 return -EINVAL; 301 } 302 303 /* calculate debounce bit value */ 304 if (debounce != 0) { 305 /* Convert to ms */ 306 debounce /= 1000; 307 /* find the MSB */ 308 res = fls(debounce) - 1; 309 /* Check if MSB-1 is set (round up or down) */ 310 if (res > 0 && (debounce & BIT(res - 1))) 311 res++; 312 } 313 314 /* spin lock for read-modify-write of the GPIO register */ 315 raw_spin_lock_irqsave(&kona_gpio->lock, flags); 316 317 val = readl(reg_base + GPIO_CONTROL(gpio)); 318 val &= ~GPIO_GPCTR0_DBR_MASK; 319 320 if (debounce == 0) { 321 /* disable debounce */ 322 val &= ~GPIO_GPCTR0_DB_ENABLE_MASK; 323 } else { 324 val |= GPIO_GPCTR0_DB_ENABLE_MASK | 325 (res << GPIO_GPCTR0_DBR_SHIFT); 326 } 327 328 writel(val, reg_base + GPIO_CONTROL(gpio)); 329 330 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 331 332 return 0; 333 } 334 335 static int bcm_kona_gpio_set_config(struct gpio_chip *chip, unsigned gpio, 336 unsigned long config) 337 { 338 u32 debounce; 339 340 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 341 return -ENOTSUPP; 342 343 debounce = pinconf_to_config_argument(config); 344 return bcm_kona_gpio_set_debounce(chip, gpio, debounce); 345 } 346 347 static const struct gpio_chip template_chip = { 348 .label = "bcm-kona-gpio", 349 .owner = THIS_MODULE, 350 .request = bcm_kona_gpio_request, 351 .free = bcm_kona_gpio_free, 352 .get_direction = bcm_kona_gpio_get_dir, 353 .direction_input = bcm_kona_gpio_direction_input, 354 .get = bcm_kona_gpio_get, 355 .direction_output = bcm_kona_gpio_direction_output, 356 .set = bcm_kona_gpio_set, 357 .set_config = bcm_kona_gpio_set_config, 358 .to_irq = bcm_kona_gpio_to_irq, 359 .base = 0, 360 }; 361 362 static void bcm_kona_gpio_irq_ack(struct irq_data *d) 363 { 364 struct bcm_kona_gpio *kona_gpio; 365 void __iomem *reg_base; 366 unsigned gpio = d->hwirq; 367 int bank_id = GPIO_BANK(gpio); 368 int bit = GPIO_BIT(gpio); 369 u32 val; 370 unsigned long flags; 371 372 kona_gpio = irq_data_get_irq_chip_data(d); 373 reg_base = kona_gpio->reg_base; 374 raw_spin_lock_irqsave(&kona_gpio->lock, flags); 375 376 val = readl(reg_base + GPIO_INT_STATUS(bank_id)); 377 val |= BIT(bit); 378 writel(val, reg_base + GPIO_INT_STATUS(bank_id)); 379 380 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 381 } 382 383 static void bcm_kona_gpio_irq_mask(struct irq_data *d) 384 { 385 struct bcm_kona_gpio *kona_gpio; 386 void __iomem *reg_base; 387 unsigned gpio = d->hwirq; 388 int bank_id = GPIO_BANK(gpio); 389 int bit = GPIO_BIT(gpio); 390 u32 val; 391 unsigned long flags; 392 393 kona_gpio = irq_data_get_irq_chip_data(d); 394 reg_base = kona_gpio->reg_base; 395 396 raw_spin_lock_irqsave(&kona_gpio->lock, flags); 397 398 val = readl(reg_base + GPIO_INT_MASK(bank_id)); 399 val |= BIT(bit); 400 writel(val, reg_base + GPIO_INT_MASK(bank_id)); 401 gpiochip_disable_irq(&kona_gpio->gpio_chip, gpio); 402 403 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 404 } 405 406 static void bcm_kona_gpio_irq_unmask(struct irq_data *d) 407 { 408 struct bcm_kona_gpio *kona_gpio; 409 void __iomem *reg_base; 410 unsigned gpio = d->hwirq; 411 int bank_id = GPIO_BANK(gpio); 412 int bit = GPIO_BIT(gpio); 413 u32 val; 414 unsigned long flags; 415 416 kona_gpio = irq_data_get_irq_chip_data(d); 417 reg_base = kona_gpio->reg_base; 418 419 raw_spin_lock_irqsave(&kona_gpio->lock, flags); 420 421 val = readl(reg_base + GPIO_INT_MSKCLR(bank_id)); 422 val |= BIT(bit); 423 writel(val, reg_base + GPIO_INT_MSKCLR(bank_id)); 424 gpiochip_enable_irq(&kona_gpio->gpio_chip, gpio); 425 426 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 427 } 428 429 static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type) 430 { 431 struct bcm_kona_gpio *kona_gpio; 432 void __iomem *reg_base; 433 unsigned gpio = d->hwirq; 434 u32 lvl_type; 435 u32 val; 436 unsigned long flags; 437 438 kona_gpio = irq_data_get_irq_chip_data(d); 439 reg_base = kona_gpio->reg_base; 440 switch (type & IRQ_TYPE_SENSE_MASK) { 441 case IRQ_TYPE_EDGE_RISING: 442 lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE; 443 break; 444 445 case IRQ_TYPE_EDGE_FALLING: 446 lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE; 447 break; 448 449 case IRQ_TYPE_EDGE_BOTH: 450 lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE; 451 break; 452 453 case IRQ_TYPE_LEVEL_HIGH: 454 case IRQ_TYPE_LEVEL_LOW: 455 /* BCM GPIO doesn't support level triggering */ 456 default: 457 dev_err(kona_gpio->gpio_chip.parent, 458 "Invalid BCM GPIO irq type 0x%x\n", type); 459 return -EINVAL; 460 } 461 462 raw_spin_lock_irqsave(&kona_gpio->lock, flags); 463 464 val = readl(reg_base + GPIO_CONTROL(gpio)); 465 val &= ~GPIO_GPCTR0_ITR_MASK; 466 val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT; 467 writel(val, reg_base + GPIO_CONTROL(gpio)); 468 469 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 470 471 return 0; 472 } 473 474 static void bcm_kona_gpio_irq_handler(struct irq_desc *desc) 475 { 476 void __iomem *reg_base; 477 int bit, bank_id; 478 unsigned long sta; 479 struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc); 480 struct irq_chip *chip = irq_desc_get_chip(desc); 481 482 chained_irq_enter(chip, desc); 483 484 /* 485 * For bank interrupts, we can't use chip_data to store the kona_gpio 486 * pointer, since GIC needs it for its own purposes. Therefore, we get 487 * our pointer from the bank structure. 488 */ 489 reg_base = bank->kona_gpio->reg_base; 490 bank_id = bank->id; 491 492 while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) & 493 (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) { 494 for_each_set_bit(bit, &sta, 32) { 495 int hwirq = GPIO_PER_BANK * bank_id + bit; 496 /* 497 * Clear interrupt before handler is called so we don't 498 * miss any interrupt occurred during executing them. 499 */ 500 writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) | 501 BIT(bit), reg_base + GPIO_INT_STATUS(bank_id)); 502 /* Invoke interrupt handler */ 503 generic_handle_domain_irq(bank->kona_gpio->irq_domain, 504 hwirq); 505 } 506 } 507 508 chained_irq_exit(chip, desc); 509 } 510 511 static int bcm_kona_gpio_irq_reqres(struct irq_data *d) 512 { 513 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d); 514 unsigned int gpio = d->hwirq; 515 516 /* 517 * We need to unlock the GPIO before any other operations are performed 518 * on the relevant GPIO configuration registers 519 */ 520 bcm_kona_gpio_unlock_gpio(kona_gpio, gpio); 521 522 return gpiochip_reqres_irq(&kona_gpio->gpio_chip, gpio); 523 } 524 525 static void bcm_kona_gpio_irq_relres(struct irq_data *d) 526 { 527 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d); 528 unsigned int gpio = d->hwirq; 529 530 /* Once we no longer use it, lock the GPIO again */ 531 bcm_kona_gpio_lock_gpio(kona_gpio, gpio); 532 533 gpiochip_relres_irq(&kona_gpio->gpio_chip, gpio); 534 } 535 536 static struct irq_chip bcm_gpio_irq_chip = { 537 .name = "bcm-kona-gpio", 538 .irq_ack = bcm_kona_gpio_irq_ack, 539 .irq_mask = bcm_kona_gpio_irq_mask, 540 .irq_unmask = bcm_kona_gpio_irq_unmask, 541 .irq_set_type = bcm_kona_gpio_irq_set_type, 542 .irq_request_resources = bcm_kona_gpio_irq_reqres, 543 .irq_release_resources = bcm_kona_gpio_irq_relres, 544 }; 545 546 static struct of_device_id const bcm_kona_gpio_of_match[] = { 547 { .compatible = "brcm,kona-gpio" }, 548 {} 549 }; 550 551 /* 552 * This lock class tells lockdep that GPIO irqs are in a different 553 * category than their parents, so it won't report false recursion. 554 */ 555 static struct lock_class_key gpio_lock_class; 556 static struct lock_class_key gpio_request_class; 557 558 static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq, 559 irq_hw_number_t hwirq) 560 { 561 int ret; 562 563 ret = irq_set_chip_data(irq, d->host_data); 564 if (ret < 0) 565 return ret; 566 irq_set_lockdep_class(irq, &gpio_lock_class, &gpio_request_class); 567 irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq); 568 irq_set_noprobe(irq); 569 570 return 0; 571 } 572 573 static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq) 574 { 575 irq_set_chip_and_handler(irq, NULL, NULL); 576 irq_set_chip_data(irq, NULL); 577 } 578 579 static const struct irq_domain_ops bcm_kona_irq_ops = { 580 .map = bcm_kona_gpio_irq_map, 581 .unmap = bcm_kona_gpio_irq_unmap, 582 .xlate = irq_domain_xlate_twocell, 583 }; 584 585 static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio) 586 { 587 void __iomem *reg_base; 588 int i; 589 590 reg_base = kona_gpio->reg_base; 591 /* disable interrupts and clear status */ 592 for (i = 0; i < kona_gpio->num_bank; i++) { 593 /* Unlock the entire bank first */ 594 bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE); 595 writel(0xffffffff, reg_base + GPIO_INT_MASK(i)); 596 writel(0xffffffff, reg_base + GPIO_INT_STATUS(i)); 597 /* Now re-lock the bank */ 598 bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE); 599 } 600 } 601 602 static int bcm_kona_gpio_probe(struct platform_device *pdev) 603 { 604 struct device *dev = &pdev->dev; 605 struct bcm_kona_gpio_bank *bank; 606 struct bcm_kona_gpio *kona_gpio; 607 struct gpio_chip *chip; 608 int ret; 609 int i; 610 611 kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL); 612 if (!kona_gpio) 613 return -ENOMEM; 614 615 kona_gpio->gpio_chip = template_chip; 616 chip = &kona_gpio->gpio_chip; 617 ret = platform_irq_count(pdev); 618 if (!ret) { 619 dev_err(dev, "Couldn't determine # GPIO banks\n"); 620 return -ENOENT; 621 } else if (ret < 0) { 622 return dev_err_probe(dev, ret, "Couldn't determine GPIO banks\n"); 623 } 624 kona_gpio->num_bank = ret; 625 626 if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) { 627 dev_err(dev, "Too many GPIO banks configured (max=%d)\n", 628 GPIO_MAX_BANK_NUM); 629 return -ENXIO; 630 } 631 kona_gpio->banks = devm_kcalloc(dev, 632 kona_gpio->num_bank, 633 sizeof(*kona_gpio->banks), 634 GFP_KERNEL); 635 if (!kona_gpio->banks) 636 return -ENOMEM; 637 638 chip->parent = dev; 639 chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK; 640 641 kona_gpio->irq_domain = irq_domain_create_linear(dev_fwnode(dev), 642 chip->ngpio, 643 &bcm_kona_irq_ops, 644 kona_gpio); 645 if (!kona_gpio->irq_domain) { 646 dev_err(dev, "Couldn't allocate IRQ domain\n"); 647 return -ENXIO; 648 } 649 650 kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0); 651 if (IS_ERR(kona_gpio->reg_base)) { 652 ret = PTR_ERR(kona_gpio->reg_base); 653 goto err_irq_domain; 654 } 655 656 for (i = 0; i < kona_gpio->num_bank; i++) { 657 bank = &kona_gpio->banks[i]; 658 bank->id = i; 659 bank->irq = platform_get_irq(pdev, i); 660 bank->kona_gpio = kona_gpio; 661 if (bank->irq < 0) { 662 dev_err(dev, "Couldn't get IRQ for bank %d\n", i); 663 ret = -ENOENT; 664 goto err_irq_domain; 665 } 666 } 667 668 dev_info(&pdev->dev, "Setting up Kona GPIO\n"); 669 670 bcm_kona_gpio_reset(kona_gpio); 671 672 ret = devm_gpiochip_add_data(dev, chip, kona_gpio); 673 if (ret < 0) { 674 dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret); 675 goto err_irq_domain; 676 } 677 for (i = 0; i < kona_gpio->num_bank; i++) { 678 bank = &kona_gpio->banks[i]; 679 irq_set_chained_handler_and_data(bank->irq, 680 bcm_kona_gpio_irq_handler, 681 bank); 682 } 683 684 raw_spin_lock_init(&kona_gpio->lock); 685 686 return 0; 687 688 err_irq_domain: 689 irq_domain_remove(kona_gpio->irq_domain); 690 691 return ret; 692 } 693 694 static struct platform_driver bcm_kona_gpio_driver = { 695 .driver = { 696 .name = "bcm-kona-gpio", 697 .of_match_table = bcm_kona_gpio_of_match, 698 }, 699 .probe = bcm_kona_gpio_probe, 700 }; 701 builtin_platform_driver(bcm_kona_gpio_driver); 702