1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Atheros AR71XX/AR724X/AR913X GPIO API support 4 * 5 * Copyright (C) 2015 Alban Bedel <albeu@free.fr> 6 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 7 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 8 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 9 */ 10 11 #include <linux/gpio/driver.h> 12 #include <linux/platform_data/gpio-ath79.h> 13 #include <linux/of_device.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/irq.h> 17 18 #define AR71XX_GPIO_REG_OE 0x00 19 #define AR71XX_GPIO_REG_IN 0x04 20 #define AR71XX_GPIO_REG_SET 0x0c 21 #define AR71XX_GPIO_REG_CLEAR 0x10 22 23 #define AR71XX_GPIO_REG_INT_ENABLE 0x14 24 #define AR71XX_GPIO_REG_INT_TYPE 0x18 25 #define AR71XX_GPIO_REG_INT_POLARITY 0x1c 26 #define AR71XX_GPIO_REG_INT_PENDING 0x20 27 #define AR71XX_GPIO_REG_INT_MASK 0x24 28 29 struct ath79_gpio_ctrl { 30 struct gpio_chip gc; 31 void __iomem *base; 32 raw_spinlock_t lock; 33 unsigned long both_edges; 34 }; 35 36 static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *data) 37 { 38 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 39 40 return container_of(gc, struct ath79_gpio_ctrl, gc); 41 } 42 43 static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg) 44 { 45 return readl(ctrl->base + reg); 46 } 47 48 static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl, 49 unsigned reg, u32 val) 50 { 51 writel(val, ctrl->base + reg); 52 } 53 54 static bool ath79_gpio_update_bits( 55 struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits) 56 { 57 u32 old_val, new_val; 58 59 old_val = ath79_gpio_read(ctrl, reg); 60 new_val = (old_val & ~mask) | (bits & mask); 61 62 if (new_val != old_val) 63 ath79_gpio_write(ctrl, reg, new_val); 64 65 return new_val != old_val; 66 } 67 68 static void ath79_gpio_irq_unmask(struct irq_data *data) 69 { 70 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 71 u32 mask = BIT(irqd_to_hwirq(data)); 72 unsigned long flags; 73 74 raw_spin_lock_irqsave(&ctrl->lock, flags); 75 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); 76 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 77 } 78 79 static void ath79_gpio_irq_mask(struct irq_data *data) 80 { 81 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 82 u32 mask = BIT(irqd_to_hwirq(data)); 83 unsigned long flags; 84 85 raw_spin_lock_irqsave(&ctrl->lock, flags); 86 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); 87 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 88 } 89 90 static void ath79_gpio_irq_enable(struct irq_data *data) 91 { 92 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 93 u32 mask = BIT(irqd_to_hwirq(data)); 94 unsigned long flags; 95 96 raw_spin_lock_irqsave(&ctrl->lock, flags); 97 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); 98 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); 99 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 100 } 101 102 static void ath79_gpio_irq_disable(struct irq_data *data) 103 { 104 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 105 u32 mask = BIT(irqd_to_hwirq(data)); 106 unsigned long flags; 107 108 raw_spin_lock_irqsave(&ctrl->lock, flags); 109 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); 110 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0); 111 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 112 } 113 114 static int ath79_gpio_irq_set_type(struct irq_data *data, 115 unsigned int flow_type) 116 { 117 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 118 u32 mask = BIT(irqd_to_hwirq(data)); 119 u32 type = 0, polarity = 0; 120 unsigned long flags; 121 bool disabled; 122 123 switch (flow_type) { 124 case IRQ_TYPE_EDGE_RISING: 125 polarity |= mask; 126 fallthrough; 127 case IRQ_TYPE_EDGE_FALLING: 128 case IRQ_TYPE_EDGE_BOTH: 129 break; 130 131 case IRQ_TYPE_LEVEL_HIGH: 132 polarity |= mask; 133 fallthrough; 134 case IRQ_TYPE_LEVEL_LOW: 135 type |= mask; 136 break; 137 138 default: 139 return -EINVAL; 140 } 141 142 raw_spin_lock_irqsave(&ctrl->lock, flags); 143 144 if (flow_type == IRQ_TYPE_EDGE_BOTH) { 145 ctrl->both_edges |= mask; 146 polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN); 147 } else { 148 ctrl->both_edges &= ~mask; 149 } 150 151 /* As the IRQ configuration can't be loaded atomically we 152 * have to disable the interrupt while the configuration state 153 * is invalid. 154 */ 155 disabled = ath79_gpio_update_bits( 156 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0); 157 158 ath79_gpio_update_bits( 159 ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type); 160 ath79_gpio_update_bits( 161 ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity); 162 163 if (disabled) 164 ath79_gpio_update_bits( 165 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); 166 167 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 168 169 return 0; 170 } 171 172 static struct irq_chip ath79_gpio_irqchip = { 173 .name = "gpio-ath79", 174 .irq_enable = ath79_gpio_irq_enable, 175 .irq_disable = ath79_gpio_irq_disable, 176 .irq_mask = ath79_gpio_irq_mask, 177 .irq_unmask = ath79_gpio_irq_unmask, 178 .irq_set_type = ath79_gpio_irq_set_type, 179 }; 180 181 static void ath79_gpio_irq_handler(struct irq_desc *desc) 182 { 183 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 184 struct irq_chip *irqchip = irq_desc_get_chip(desc); 185 struct ath79_gpio_ctrl *ctrl = 186 container_of(gc, struct ath79_gpio_ctrl, gc); 187 unsigned long flags, pending; 188 u32 both_edges, state; 189 int irq; 190 191 chained_irq_enter(irqchip, desc); 192 193 raw_spin_lock_irqsave(&ctrl->lock, flags); 194 195 pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING); 196 197 /* Update the polarity of the both edges irqs */ 198 both_edges = ctrl->both_edges & pending; 199 if (both_edges) { 200 state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN); 201 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY, 202 both_edges, ~state); 203 } 204 205 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 206 207 if (pending) { 208 for_each_set_bit(irq, &pending, gc->ngpio) 209 generic_handle_irq( 210 irq_linear_revmap(gc->irq.domain, irq)); 211 } 212 213 chained_irq_exit(irqchip, desc); 214 } 215 216 static const struct of_device_id ath79_gpio_of_match[] = { 217 { .compatible = "qca,ar7100-gpio" }, 218 { .compatible = "qca,ar9340-gpio" }, 219 {}, 220 }; 221 MODULE_DEVICE_TABLE(of, ath79_gpio_of_match); 222 223 static int ath79_gpio_probe(struct platform_device *pdev) 224 { 225 struct ath79_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev); 226 struct device *dev = &pdev->dev; 227 struct device_node *np = dev->of_node; 228 struct ath79_gpio_ctrl *ctrl; 229 struct gpio_irq_chip *girq; 230 u32 ath79_gpio_count; 231 bool oe_inverted; 232 int err; 233 234 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 235 if (!ctrl) 236 return -ENOMEM; 237 238 if (np) { 239 err = of_property_read_u32(np, "ngpios", &ath79_gpio_count); 240 if (err) { 241 dev_err(dev, "ngpios property is not valid\n"); 242 return err; 243 } 244 oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio"); 245 } else if (pdata) { 246 ath79_gpio_count = pdata->ngpios; 247 oe_inverted = pdata->oe_inverted; 248 } else { 249 dev_err(dev, "No DT node or platform data found\n"); 250 return -EINVAL; 251 } 252 253 if (ath79_gpio_count >= 32) { 254 dev_err(dev, "ngpios must be less than 32\n"); 255 return -EINVAL; 256 } 257 258 ctrl->base = devm_platform_ioremap_resource(pdev, 0); 259 if (IS_ERR(ctrl->base)) 260 return PTR_ERR(ctrl->base); 261 262 raw_spin_lock_init(&ctrl->lock); 263 err = bgpio_init(&ctrl->gc, dev, 4, 264 ctrl->base + AR71XX_GPIO_REG_IN, 265 ctrl->base + AR71XX_GPIO_REG_SET, 266 ctrl->base + AR71XX_GPIO_REG_CLEAR, 267 oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE, 268 oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL, 269 0); 270 if (err) { 271 dev_err(dev, "bgpio_init failed\n"); 272 return err; 273 } 274 /* Use base 0 to stay compatible with legacy platforms */ 275 ctrl->gc.base = 0; 276 277 /* Optional interrupt setup */ 278 if (!np || of_property_read_bool(np, "interrupt-controller")) { 279 girq = &ctrl->gc.irq; 280 girq->chip = &ath79_gpio_irqchip; 281 girq->parent_handler = ath79_gpio_irq_handler; 282 girq->num_parents = 1; 283 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 284 GFP_KERNEL); 285 if (!girq->parents) 286 return -ENOMEM; 287 girq->parents[0] = platform_get_irq(pdev, 0); 288 girq->default_type = IRQ_TYPE_NONE; 289 girq->handler = handle_simple_irq; 290 } 291 292 return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl); 293 } 294 295 static struct platform_driver ath79_gpio_driver = { 296 .driver = { 297 .name = "ath79-gpio", 298 .of_match_table = ath79_gpio_of_match, 299 }, 300 .probe = ath79_gpio_probe, 301 }; 302 303 module_platform_driver(ath79_gpio_driver); 304 305 MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support"); 306 MODULE_LICENSE("GPL v2"); 307