1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Atheros AR71XX/AR724X/AR913X GPIO API support 4 * 5 * Copyright (C) 2015 Alban Bedel <albeu@free.fr> 6 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 7 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 8 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 9 */ 10 11 #include <linux/device.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/gpio/generic.h> 14 #include <linux/gpio/machine.h> /* For WLAN GPIOs */ 15 #include <linux/interrupt.h> 16 #include <linux/irq.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 21 #define AR71XX_GPIO_REG_OE 0x00 22 #define AR71XX_GPIO_REG_IN 0x04 23 #define AR71XX_GPIO_REG_SET 0x0c 24 #define AR71XX_GPIO_REG_CLEAR 0x10 25 26 #define AR71XX_GPIO_REG_INT_ENABLE 0x14 27 #define AR71XX_GPIO_REG_INT_TYPE 0x18 28 #define AR71XX_GPIO_REG_INT_POLARITY 0x1c 29 #define AR71XX_GPIO_REG_INT_PENDING 0x20 30 #define AR71XX_GPIO_REG_INT_MASK 0x24 31 32 struct ath79_gpio_ctrl { 33 struct gpio_generic_chip chip; 34 void __iomem *base; 35 unsigned long both_edges; 36 }; 37 38 static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *data) 39 { 40 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 41 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc); 42 43 return container_of(gen_gc, struct ath79_gpio_ctrl, chip); 44 } 45 46 static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg) 47 { 48 return readl(ctrl->base + reg); 49 } 50 51 static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl, 52 unsigned reg, u32 val) 53 { 54 writel(val, ctrl->base + reg); 55 } 56 57 static bool ath79_gpio_update_bits( 58 struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits) 59 { 60 u32 old_val, new_val; 61 62 old_val = ath79_gpio_read(ctrl, reg); 63 new_val = (old_val & ~mask) | (bits & mask); 64 65 if (new_val != old_val) 66 ath79_gpio_write(ctrl, reg, new_val); 67 68 return new_val != old_val; 69 } 70 71 static void ath79_gpio_irq_unmask(struct irq_data *data) 72 { 73 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 74 u32 mask = BIT(irqd_to_hwirq(data)); 75 76 gpiochip_enable_irq(&ctrl->chip.gc, irqd_to_hwirq(data)); 77 78 guard(gpio_generic_lock_irqsave)(&ctrl->chip); 79 80 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); 81 } 82 83 static void ath79_gpio_irq_mask(struct irq_data *data) 84 { 85 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 86 u32 mask = BIT(irqd_to_hwirq(data)); 87 88 scoped_guard(gpio_generic_lock_irqsave, &ctrl->chip) 89 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); 90 91 gpiochip_disable_irq(&ctrl->chip.gc, irqd_to_hwirq(data)); 92 } 93 94 static void ath79_gpio_irq_enable(struct irq_data *data) 95 { 96 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 97 u32 mask = BIT(irqd_to_hwirq(data)); 98 99 guard(gpio_generic_lock_irqsave)(&ctrl->chip); 100 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); 101 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); 102 } 103 104 static void ath79_gpio_irq_disable(struct irq_data *data) 105 { 106 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 107 u32 mask = BIT(irqd_to_hwirq(data)); 108 109 guard(gpio_generic_lock_irqsave)(&ctrl->chip); 110 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); 111 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0); 112 } 113 114 static int ath79_gpio_irq_set_type(struct irq_data *data, 115 unsigned int flow_type) 116 { 117 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 118 u32 mask = BIT(irqd_to_hwirq(data)); 119 u32 type = 0, polarity = 0; 120 bool disabled; 121 122 switch (flow_type) { 123 case IRQ_TYPE_EDGE_RISING: 124 polarity |= mask; 125 fallthrough; 126 case IRQ_TYPE_EDGE_FALLING: 127 case IRQ_TYPE_EDGE_BOTH: 128 break; 129 130 case IRQ_TYPE_LEVEL_HIGH: 131 polarity |= mask; 132 fallthrough; 133 case IRQ_TYPE_LEVEL_LOW: 134 type |= mask; 135 break; 136 137 default: 138 return -EINVAL; 139 } 140 141 guard(gpio_generic_lock_irqsave)(&ctrl->chip); 142 143 if (flow_type == IRQ_TYPE_EDGE_BOTH) { 144 ctrl->both_edges |= mask; 145 polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN); 146 } else { 147 ctrl->both_edges &= ~mask; 148 } 149 150 /* As the IRQ configuration can't be loaded atomically we 151 * have to disable the interrupt while the configuration state 152 * is invalid. 153 */ 154 disabled = ath79_gpio_update_bits( 155 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0); 156 157 ath79_gpio_update_bits( 158 ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type); 159 ath79_gpio_update_bits( 160 ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity); 161 162 if (disabled) 163 ath79_gpio_update_bits( 164 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); 165 166 return 0; 167 } 168 169 static const struct irq_chip ath79_gpio_irqchip = { 170 .name = "gpio-ath79", 171 .irq_enable = ath79_gpio_irq_enable, 172 .irq_disable = ath79_gpio_irq_disable, 173 .irq_mask = ath79_gpio_irq_mask, 174 .irq_unmask = ath79_gpio_irq_unmask, 175 .irq_set_type = ath79_gpio_irq_set_type, 176 .flags = IRQCHIP_IMMUTABLE, 177 GPIOCHIP_IRQ_RESOURCE_HELPERS, 178 }; 179 180 static void ath79_gpio_irq_handler(struct irq_desc *desc) 181 { 182 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 183 struct irq_chip *irqchip = irq_desc_get_chip(desc); 184 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc); 185 struct ath79_gpio_ctrl *ctrl = 186 container_of(gen_gc, struct ath79_gpio_ctrl, chip); 187 unsigned long pending; 188 u32 both_edges, state; 189 int irq; 190 191 chained_irq_enter(irqchip, desc); 192 193 scoped_guard(gpio_generic_lock_irqsave, &ctrl->chip) { 194 pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING); 195 196 /* Update the polarity of the both edges irqs */ 197 both_edges = ctrl->both_edges & pending; 198 if (both_edges) { 199 state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN); 200 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY, 201 both_edges, ~state); 202 } 203 } 204 205 for_each_set_bit(irq, &pending, gc->ngpio) 206 generic_handle_domain_irq(gc->irq.domain, irq); 207 208 chained_irq_exit(irqchip, desc); 209 } 210 211 static const struct of_device_id ath79_gpio_of_match[] = { 212 { .compatible = "qca,ar7100-gpio" }, 213 { .compatible = "qca,ar9340-gpio" }, 214 {}, 215 }; 216 MODULE_DEVICE_TABLE(of, ath79_gpio_of_match); 217 218 #if IS_ENABLED(CONFIG_ATH9K_AHB) 219 /* 220 * This registers all of the ath79k GPIOs as descriptors to be picked 221 * directly from the ATH79K wifi driver if the two are jitted together 222 * in the same SoC. 223 */ 224 #define ATH79K_WIFI_DESCS 32 225 static int ath79_gpio_register_wifi_descriptors(struct device *dev, 226 const char *label) 227 { 228 struct gpiod_lookup_table *lookup; 229 int i; 230 231 /* Create a gpiod lookup using gpiochip-local offsets + 1 for NULL */ 232 lookup = devm_kzalloc(dev, 233 struct_size(lookup, table, ATH79K_WIFI_DESCS + 1), 234 GFP_KERNEL); 235 if (!lookup) 236 return -ENOMEM; 237 238 /* 239 * Ugly system-wide lookup for the NULL device: we know this 240 * is already NULL but explicitly assign it here for people to 241 * know what is going on. (Yes this is an ugly legacy hack, live 242 * with it.) 243 */ 244 lookup->dev_id = NULL; 245 246 for (i = 0; i < ATH79K_WIFI_DESCS; i++) { 247 lookup->table[i] = 248 /* 249 * Set the HW offset on the chip and the lookup 250 * index to the same value, so looking up index 0 251 * will get HW offset 0, index 1 HW offset 1 etc. 252 */ 253 GPIO_LOOKUP_IDX(label, i, "ath9k", i, GPIO_ACTIVE_HIGH); 254 } 255 256 gpiod_add_lookup_table(lookup); 257 258 return 0; 259 } 260 #else 261 static int ath79_gpio_register_wifi_descriptors(struct device *dev, 262 const char *label) 263 { 264 return 0; 265 } 266 #endif 267 268 static int ath79_gpio_probe(struct platform_device *pdev) 269 { 270 struct gpio_generic_chip_config config; 271 struct device *dev = &pdev->dev; 272 struct ath79_gpio_ctrl *ctrl; 273 struct gpio_irq_chip *girq; 274 u32 ath79_gpio_count; 275 bool oe_inverted; 276 int err; 277 278 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 279 if (!ctrl) 280 return -ENOMEM; 281 282 err = device_property_read_u32(dev, "ngpios", &ath79_gpio_count); 283 if (err) { 284 dev_err(dev, "ngpios property is not valid\n"); 285 return err; 286 } 287 288 oe_inverted = device_is_compatible(dev, "qca,ar9340-gpio"); 289 290 if (ath79_gpio_count >= 32) { 291 dev_err(dev, "ngpios must be less than 32\n"); 292 return -EINVAL; 293 } 294 295 ctrl->base = devm_platform_ioremap_resource(pdev, 0); 296 if (IS_ERR(ctrl->base)) 297 return PTR_ERR(ctrl->base); 298 299 config = (struct gpio_generic_chip_config) { 300 .dev = dev, 301 .sz = 4, 302 .dat = ctrl->base + AR71XX_GPIO_REG_IN, 303 .set = ctrl->base + AR71XX_GPIO_REG_SET, 304 .clr = ctrl->base + AR71XX_GPIO_REG_CLEAR, 305 .dirout = oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE, 306 .dirin = oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL, 307 }; 308 309 err = gpio_generic_chip_init(&ctrl->chip, &config); 310 if (err) { 311 dev_err(dev, "failed to initialize generic GPIO chip\n"); 312 return err; 313 } 314 315 /* Optional interrupt setup */ 316 if (device_property_read_bool(dev, "interrupt-controller")) { 317 girq = &ctrl->chip.gc.irq; 318 gpio_irq_chip_set_chip(girq, &ath79_gpio_irqchip); 319 girq->parent_handler = ath79_gpio_irq_handler; 320 girq->num_parents = 1; 321 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 322 GFP_KERNEL); 323 if (!girq->parents) 324 return -ENOMEM; 325 girq->parents[0] = platform_get_irq(pdev, 0); 326 girq->default_type = IRQ_TYPE_NONE; 327 girq->handler = handle_simple_irq; 328 } 329 330 err = devm_gpiochip_add_data(dev, &ctrl->chip.gc, ctrl); 331 if (err) 332 return err; 333 334 return ath79_gpio_register_wifi_descriptors(dev, ctrl->chip.gc.label); 335 } 336 337 static struct platform_driver ath79_gpio_driver = { 338 .driver = { 339 .name = "ath79-gpio", 340 .of_match_table = ath79_gpio_of_match, 341 }, 342 .probe = ath79_gpio_probe, 343 }; 344 345 module_platform_driver(ath79_gpio_driver); 346 347 MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support"); 348 MODULE_LICENSE("GPL v2"); 349