1 /* 2 * Atheros AR71XX/AR724X/AR913X GPIO API support 3 * 4 * Copyright (C) 2015 Alban Bedel <albeu@free.fr> 5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published 11 * by the Free Software Foundation. 12 */ 13 14 #include <linux/gpio/driver.h> 15 #include <linux/platform_data/gpio-ath79.h> 16 #include <linux/of_device.h> 17 #include <linux/interrupt.h> 18 #include <linux/irq.h> 19 20 #define AR71XX_GPIO_REG_OE 0x00 21 #define AR71XX_GPIO_REG_IN 0x04 22 #define AR71XX_GPIO_REG_SET 0x0c 23 #define AR71XX_GPIO_REG_CLEAR 0x10 24 25 #define AR71XX_GPIO_REG_INT_ENABLE 0x14 26 #define AR71XX_GPIO_REG_INT_TYPE 0x18 27 #define AR71XX_GPIO_REG_INT_POLARITY 0x1c 28 #define AR71XX_GPIO_REG_INT_PENDING 0x20 29 #define AR71XX_GPIO_REG_INT_MASK 0x24 30 31 struct ath79_gpio_ctrl { 32 struct gpio_chip gc; 33 void __iomem *base; 34 spinlock_t lock; 35 unsigned long both_edges; 36 }; 37 38 static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *data) 39 { 40 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 41 42 return container_of(gc, struct ath79_gpio_ctrl, gc); 43 } 44 45 static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg) 46 { 47 return readl(ctrl->base + reg); 48 } 49 50 static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl, 51 unsigned reg, u32 val) 52 { 53 return writel(val, ctrl->base + reg); 54 } 55 56 static bool ath79_gpio_update_bits( 57 struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits) 58 { 59 u32 old_val, new_val; 60 61 old_val = ath79_gpio_read(ctrl, reg); 62 new_val = (old_val & ~mask) | (bits & mask); 63 64 if (new_val != old_val) 65 ath79_gpio_write(ctrl, reg, new_val); 66 67 return new_val != old_val; 68 } 69 70 static void ath79_gpio_irq_unmask(struct irq_data *data) 71 { 72 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 73 u32 mask = BIT(irqd_to_hwirq(data)); 74 unsigned long flags; 75 76 spin_lock_irqsave(&ctrl->lock, flags); 77 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); 78 spin_unlock_irqrestore(&ctrl->lock, flags); 79 } 80 81 static void ath79_gpio_irq_mask(struct irq_data *data) 82 { 83 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 84 u32 mask = BIT(irqd_to_hwirq(data)); 85 unsigned long flags; 86 87 spin_lock_irqsave(&ctrl->lock, flags); 88 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); 89 spin_unlock_irqrestore(&ctrl->lock, flags); 90 } 91 92 static void ath79_gpio_irq_enable(struct irq_data *data) 93 { 94 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 95 u32 mask = BIT(irqd_to_hwirq(data)); 96 unsigned long flags; 97 98 spin_lock_irqsave(&ctrl->lock, flags); 99 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); 100 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); 101 spin_unlock_irqrestore(&ctrl->lock, flags); 102 } 103 104 static void ath79_gpio_irq_disable(struct irq_data *data) 105 { 106 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 107 u32 mask = BIT(irqd_to_hwirq(data)); 108 unsigned long flags; 109 110 spin_lock_irqsave(&ctrl->lock, flags); 111 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); 112 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0); 113 spin_unlock_irqrestore(&ctrl->lock, flags); 114 } 115 116 static int ath79_gpio_irq_set_type(struct irq_data *data, 117 unsigned int flow_type) 118 { 119 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 120 u32 mask = BIT(irqd_to_hwirq(data)); 121 u32 type = 0, polarity = 0; 122 unsigned long flags; 123 bool disabled; 124 125 switch (flow_type) { 126 case IRQ_TYPE_EDGE_RISING: 127 polarity |= mask; 128 case IRQ_TYPE_EDGE_FALLING: 129 case IRQ_TYPE_EDGE_BOTH: 130 break; 131 132 case IRQ_TYPE_LEVEL_HIGH: 133 polarity |= mask; 134 case IRQ_TYPE_LEVEL_LOW: 135 type |= mask; 136 break; 137 138 default: 139 return -EINVAL; 140 } 141 142 spin_lock_irqsave(&ctrl->lock, flags); 143 144 if (flow_type == IRQ_TYPE_EDGE_BOTH) { 145 ctrl->both_edges |= mask; 146 polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN); 147 } else { 148 ctrl->both_edges &= ~mask; 149 } 150 151 /* As the IRQ configuration can't be loaded atomically we 152 * have to disable the interrupt while the configuration state 153 * is invalid. 154 */ 155 disabled = ath79_gpio_update_bits( 156 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0); 157 158 ath79_gpio_update_bits( 159 ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type); 160 ath79_gpio_update_bits( 161 ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity); 162 163 if (disabled) 164 ath79_gpio_update_bits( 165 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); 166 167 spin_unlock_irqrestore(&ctrl->lock, flags); 168 169 return 0; 170 } 171 172 static struct irq_chip ath79_gpio_irqchip = { 173 .name = "gpio-ath79", 174 .irq_enable = ath79_gpio_irq_enable, 175 .irq_disable = ath79_gpio_irq_disable, 176 .irq_mask = ath79_gpio_irq_mask, 177 .irq_unmask = ath79_gpio_irq_unmask, 178 .irq_set_type = ath79_gpio_irq_set_type, 179 }; 180 181 static void ath79_gpio_irq_handler(struct irq_desc *desc) 182 { 183 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 184 struct irq_chip *irqchip = irq_desc_get_chip(desc); 185 struct ath79_gpio_ctrl *ctrl = 186 container_of(gc, struct ath79_gpio_ctrl, gc); 187 unsigned long flags, pending; 188 u32 both_edges, state; 189 int irq; 190 191 chained_irq_enter(irqchip, desc); 192 193 spin_lock_irqsave(&ctrl->lock, flags); 194 195 pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING); 196 197 /* Update the polarity of the both edges irqs */ 198 both_edges = ctrl->both_edges & pending; 199 if (both_edges) { 200 state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN); 201 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY, 202 both_edges, ~state); 203 } 204 205 spin_unlock_irqrestore(&ctrl->lock, flags); 206 207 if (pending) { 208 for_each_set_bit(irq, &pending, gc->ngpio) 209 generic_handle_irq( 210 irq_linear_revmap(gc->irqdomain, irq)); 211 } 212 213 chained_irq_exit(irqchip, desc); 214 } 215 216 static const struct of_device_id ath79_gpio_of_match[] = { 217 { .compatible = "qca,ar7100-gpio" }, 218 { .compatible = "qca,ar9340-gpio" }, 219 {}, 220 }; 221 222 static int ath79_gpio_probe(struct platform_device *pdev) 223 { 224 struct ath79_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev); 225 struct device_node *np = pdev->dev.of_node; 226 struct ath79_gpio_ctrl *ctrl; 227 struct resource *res; 228 u32 ath79_gpio_count; 229 bool oe_inverted; 230 int err; 231 232 ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL); 233 if (!ctrl) 234 return -ENOMEM; 235 platform_set_drvdata(pdev, ctrl); 236 237 if (np) { 238 err = of_property_read_u32(np, "ngpios", &ath79_gpio_count); 239 if (err) { 240 dev_err(&pdev->dev, "ngpios property is not valid\n"); 241 return err; 242 } 243 oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio"); 244 } else if (pdata) { 245 ath79_gpio_count = pdata->ngpios; 246 oe_inverted = pdata->oe_inverted; 247 } else { 248 dev_err(&pdev->dev, "No DT node or platform data found\n"); 249 return -EINVAL; 250 } 251 252 if (ath79_gpio_count >= 32) { 253 dev_err(&pdev->dev, "ngpios must be less than 32\n"); 254 return -EINVAL; 255 } 256 257 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 258 ctrl->base = devm_ioremap_nocache( 259 &pdev->dev, res->start, resource_size(res)); 260 if (!ctrl->base) 261 return -ENOMEM; 262 263 spin_lock_init(&ctrl->lock); 264 err = bgpio_init(&ctrl->gc, &pdev->dev, 4, 265 ctrl->base + AR71XX_GPIO_REG_IN, 266 ctrl->base + AR71XX_GPIO_REG_SET, 267 ctrl->base + AR71XX_GPIO_REG_CLEAR, 268 oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE, 269 oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL, 270 0); 271 if (err) { 272 dev_err(&pdev->dev, "bgpio_init failed\n"); 273 return err; 274 } 275 /* Use base 0 to stay compatible with legacy platforms */ 276 ctrl->gc.base = 0; 277 278 err = gpiochip_add_data(&ctrl->gc, ctrl); 279 if (err) { 280 dev_err(&pdev->dev, 281 "cannot add AR71xx GPIO chip, error=%d", err); 282 return err; 283 } 284 285 if (np && !of_property_read_bool(np, "interrupt-controller")) 286 return 0; 287 288 err = gpiochip_irqchip_add(&ctrl->gc, &ath79_gpio_irqchip, 0, 289 handle_simple_irq, IRQ_TYPE_NONE); 290 if (err) { 291 dev_err(&pdev->dev, "failed to add gpiochip_irqchip\n"); 292 goto gpiochip_remove; 293 } 294 295 gpiochip_set_chained_irqchip(&ctrl->gc, &ath79_gpio_irqchip, 296 platform_get_irq(pdev, 0), 297 ath79_gpio_irq_handler); 298 299 return 0; 300 301 gpiochip_remove: 302 gpiochip_remove(&ctrl->gc); 303 return err; 304 } 305 306 static int ath79_gpio_remove(struct platform_device *pdev) 307 { 308 struct ath79_gpio_ctrl *ctrl = platform_get_drvdata(pdev); 309 310 gpiochip_remove(&ctrl->gc); 311 return 0; 312 } 313 314 static struct platform_driver ath79_gpio_driver = { 315 .driver = { 316 .name = "ath79-gpio", 317 .of_match_table = ath79_gpio_of_match, 318 }, 319 .probe = ath79_gpio_probe, 320 .remove = ath79_gpio_remove, 321 }; 322 323 module_platform_driver(ath79_gpio_driver); 324