1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2015 IBM Corp. 4 * 5 * Joel Stanley <joel@jms.id.au> 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/cleanup.h> 10 #include <linux/clk.h> 11 #include <linux/gpio/aspeed.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/hashtable.h> 14 #include <linux/init.h> 15 #include <linux/io.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/pinctrl/consumer.h> 19 #include <linux/platform_device.h> 20 #include <linux/seq_file.h> 21 #include <linux/spinlock.h> 22 #include <linux/string.h> 23 24 #include <asm/div64.h> 25 26 /* 27 * These two headers aren't meant to be used by GPIO drivers. We need 28 * them in order to access gpiod_hwgpio() which we need to implement 29 * the aspeed specific API which allows the coprocessor to request 30 * access to some GPIOs and to arbitrate between coprocessor and ARM. 31 */ 32 #include <linux/gpio/consumer.h> 33 34 #define GPIO_G7_IRQ_STS_BASE 0x100 35 #define GPIO_G7_IRQ_STS_OFFSET(x) (GPIO_G7_IRQ_STS_BASE + (x) * 0x4) 36 #define GPIO_G7_CTRL_REG_BASE 0x180 37 #define GPIO_G7_CTRL_REG_OFFSET(x) (GPIO_G7_CTRL_REG_BASE + (x) * 0x4) 38 #define GPIO_G7_CTRL_OUT_DATA BIT(0) 39 #define GPIO_G7_CTRL_DIR BIT(1) 40 #define GPIO_G7_CTRL_IRQ_EN BIT(2) 41 #define GPIO_G7_CTRL_IRQ_TYPE0 BIT(3) 42 #define GPIO_G7_CTRL_IRQ_TYPE1 BIT(4) 43 #define GPIO_G7_CTRL_IRQ_TYPE2 BIT(5) 44 #define GPIO_G7_CTRL_RST_TOLERANCE BIT(6) 45 #define GPIO_G7_CTRL_DEBOUNCE_SEL1 BIT(7) 46 #define GPIO_G7_CTRL_DEBOUNCE_SEL2 BIT(8) 47 #define GPIO_G7_CTRL_INPUT_MASK BIT(9) 48 #define GPIO_G7_CTRL_IRQ_STS BIT(12) 49 #define GPIO_G7_CTRL_IN_DATA BIT(13) 50 51 struct aspeed_bank_props { 52 unsigned int bank; 53 u32 input; 54 u32 output; 55 }; 56 57 struct aspeed_gpio_config { 58 unsigned int nr_gpios; 59 const struct aspeed_bank_props *props; 60 const struct aspeed_gpio_llops *llops; 61 const int *debounce_timers_array; 62 int debounce_timers_num; 63 bool require_dcache; 64 }; 65 66 /* 67 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled 68 * @timer_users: Tracks the number of users for each timer 69 * 70 * The @timer_users has four elements but the first element is unused. This is 71 * to simplify accounting and indexing, as a zero value in @offset_timer 72 * represents disabled debouncing for the GPIO. Any other value for an element 73 * of @offset_timer is used as an index into @timer_users. This behaviour of 74 * the zero value aligns with the behaviour of zero built from the timer 75 * configuration registers (i.e. debouncing is disabled). 76 */ 77 struct aspeed_gpio { 78 struct gpio_chip chip; 79 struct device *dev; 80 raw_spinlock_t lock; 81 void __iomem *base; 82 int irq; 83 const struct aspeed_gpio_config *config; 84 85 u8 *offset_timer; 86 unsigned int timer_users[4]; 87 struct clk *clk; 88 89 u32 *dcache; 90 u8 *cf_copro_bankmap; 91 }; 92 93 struct aspeed_gpio_bank { 94 uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch 95 * +4: Rd/Wr: Direction (0=in, 1=out) 96 */ 97 uint16_t rdata_reg; /* Rd: read write latch, Wr: <none> */ 98 uint16_t irq_regs; 99 uint16_t debounce_regs; 100 uint16_t tolerance_regs; 101 uint16_t cmdsrc_regs; 102 }; 103 104 /* 105 * Note: The "value" register returns the input value sampled on the 106 * line even when the GPIO is configured as an output. Since 107 * that input goes through synchronizers, writing, then reading 108 * back may not return the written value right away. 109 * 110 * The "rdata" register returns the content of the write latch 111 * and thus can be used to read back what was last written 112 * reliably. 113 */ 114 115 static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 }; 116 static const int g7_debounce_timers[4] = { 0x00, 0x00, 0x04, 0x08 }; 117 118 /* 119 * The debounce timers array is used to configure the debounce timer settings.Here’s how it works: 120 * Array Value: Indicates the offset for configuring the debounce timer. 121 * Array Index: Corresponds to the debounce setting register. 122 * The debounce timers array follows this pattern for configuring the debounce setting registers: 123 * Array Index 0: No debounce timer is set; 124 * Array Value is irrelevant (don’t care). 125 * Array Index 1: Debounce setting #2 is set to 1, and debounce setting #1 is set to 0. 126 * Array Value: offset for configuring debounce timer 0 (g4: 0x50, g7: 0x00) 127 * Array Index 2: Debounce setting #2 is set to 0, and debounce setting #1 is set to 1. 128 * Array Value: offset for configuring debounce timer 1 (g4: 0x54, g7: 0x04) 129 * Array Index 3: Debounce setting #2 is set to 1, and debounce setting #1 is set to 1. 130 * Array Value: offset for configuring debounce timer 2 (g4: 0x58, g7: 0x8) 131 */ 132 133 static const struct aspeed_gpio_copro_ops *copro_ops; 134 static void *copro_data; 135 136 static const struct aspeed_gpio_bank aspeed_gpio_banks[] = { 137 { 138 .val_regs = 0x0000, 139 .rdata_reg = 0x00c0, 140 .irq_regs = 0x0008, 141 .debounce_regs = 0x0040, 142 .tolerance_regs = 0x001c, 143 .cmdsrc_regs = 0x0060, 144 }, 145 { 146 .val_regs = 0x0020, 147 .rdata_reg = 0x00c4, 148 .irq_regs = 0x0028, 149 .debounce_regs = 0x0048, 150 .tolerance_regs = 0x003c, 151 .cmdsrc_regs = 0x0068, 152 }, 153 { 154 .val_regs = 0x0070, 155 .rdata_reg = 0x00c8, 156 .irq_regs = 0x0098, 157 .debounce_regs = 0x00b0, 158 .tolerance_regs = 0x00ac, 159 .cmdsrc_regs = 0x0090, 160 }, 161 { 162 .val_regs = 0x0078, 163 .rdata_reg = 0x00cc, 164 .irq_regs = 0x00e8, 165 .debounce_regs = 0x0100, 166 .tolerance_regs = 0x00fc, 167 .cmdsrc_regs = 0x00e0, 168 }, 169 { 170 .val_regs = 0x0080, 171 .rdata_reg = 0x00d0, 172 .irq_regs = 0x0118, 173 .debounce_regs = 0x0130, 174 .tolerance_regs = 0x012c, 175 .cmdsrc_regs = 0x0110, 176 }, 177 { 178 .val_regs = 0x0088, 179 .rdata_reg = 0x00d4, 180 .irq_regs = 0x0148, 181 .debounce_regs = 0x0160, 182 .tolerance_regs = 0x015c, 183 .cmdsrc_regs = 0x0140, 184 }, 185 { 186 .val_regs = 0x01E0, 187 .rdata_reg = 0x00d8, 188 .irq_regs = 0x0178, 189 .debounce_regs = 0x0190, 190 .tolerance_regs = 0x018c, 191 .cmdsrc_regs = 0x0170, 192 }, 193 { 194 .val_regs = 0x01e8, 195 .rdata_reg = 0x00dc, 196 .irq_regs = 0x01a8, 197 .debounce_regs = 0x01c0, 198 .tolerance_regs = 0x01bc, 199 .cmdsrc_regs = 0x01a0, 200 }, 201 }; 202 203 enum aspeed_gpio_reg { 204 reg_val, 205 reg_rdata, 206 reg_dir, 207 reg_irq_enable, 208 reg_irq_type0, 209 reg_irq_type1, 210 reg_irq_type2, 211 reg_irq_status, 212 reg_debounce_sel1, 213 reg_debounce_sel2, 214 reg_tolerance, 215 reg_cmdsrc0, 216 reg_cmdsrc1, 217 }; 218 219 struct aspeed_gpio_llops { 220 void (*reg_bit_set)(struct aspeed_gpio *gpio, unsigned int offset, 221 const enum aspeed_gpio_reg reg, bool val); 222 bool (*reg_bit_get)(struct aspeed_gpio *gpio, unsigned int offset, 223 const enum aspeed_gpio_reg reg); 224 int (*reg_bank_get)(struct aspeed_gpio *gpio, unsigned int offset, 225 const enum aspeed_gpio_reg reg); 226 void (*privilege_ctrl)(struct aspeed_gpio *gpio, unsigned int offset, int owner); 227 void (*privilege_init)(struct aspeed_gpio *gpio); 228 bool (*copro_request)(struct aspeed_gpio *gpio, unsigned int offset); 229 void (*copro_release)(struct aspeed_gpio *gpio, unsigned int offset); 230 }; 231 232 #define GPIO_VAL_VALUE 0x00 233 #define GPIO_VAL_DIR 0x04 234 235 #define GPIO_IRQ_ENABLE 0x00 236 #define GPIO_IRQ_TYPE0 0x04 237 #define GPIO_IRQ_TYPE1 0x08 238 #define GPIO_IRQ_TYPE2 0x0c 239 #define GPIO_IRQ_STATUS 0x10 240 241 #define GPIO_DEBOUNCE_SEL1 0x00 242 #define GPIO_DEBOUNCE_SEL2 0x04 243 244 #define GPIO_CMDSRC_0 0x00 245 #define GPIO_CMDSRC_1 0x04 246 #define GPIO_CMDSRC_ARM 0 247 #define GPIO_CMDSRC_LPC 1 248 #define GPIO_CMDSRC_COLDFIRE 2 249 #define GPIO_CMDSRC_RESERVED 3 250 251 /* This will be resolved at compile time */ 252 static void __iomem *aspeed_gpio_g4_bank_reg(struct aspeed_gpio *gpio, 253 const struct aspeed_gpio_bank *bank, 254 const enum aspeed_gpio_reg reg) 255 { 256 switch (reg) { 257 case reg_val: 258 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; 259 case reg_rdata: 260 return gpio->base + bank->rdata_reg; 261 case reg_dir: 262 return gpio->base + bank->val_regs + GPIO_VAL_DIR; 263 case reg_irq_enable: 264 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; 265 case reg_irq_type0: 266 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; 267 case reg_irq_type1: 268 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; 269 case reg_irq_type2: 270 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; 271 case reg_irq_status: 272 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; 273 case reg_debounce_sel1: 274 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1; 275 case reg_debounce_sel2: 276 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2; 277 case reg_tolerance: 278 return gpio->base + bank->tolerance_regs; 279 case reg_cmdsrc0: 280 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0; 281 case reg_cmdsrc1: 282 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1; 283 } 284 BUG(); 285 } 286 287 static u32 aspeed_gpio_g7_reg_mask(const enum aspeed_gpio_reg reg) 288 { 289 switch (reg) { 290 case reg_val: 291 return GPIO_G7_CTRL_OUT_DATA; 292 case reg_dir: 293 return GPIO_G7_CTRL_DIR; 294 case reg_irq_enable: 295 return GPIO_G7_CTRL_IRQ_EN; 296 case reg_irq_type0: 297 return GPIO_G7_CTRL_IRQ_TYPE0; 298 case reg_irq_type1: 299 return GPIO_G7_CTRL_IRQ_TYPE1; 300 case reg_irq_type2: 301 return GPIO_G7_CTRL_IRQ_TYPE2; 302 case reg_tolerance: 303 return GPIO_G7_CTRL_RST_TOLERANCE; 304 case reg_debounce_sel1: 305 return GPIO_G7_CTRL_DEBOUNCE_SEL1; 306 case reg_debounce_sel2: 307 return GPIO_G7_CTRL_DEBOUNCE_SEL2; 308 case reg_rdata: 309 return GPIO_G7_CTRL_OUT_DATA; 310 case reg_irq_status: 311 return GPIO_G7_CTRL_IRQ_STS; 312 case reg_cmdsrc0: 313 case reg_cmdsrc1: 314 default: 315 WARN_ON_ONCE(1); 316 return 0; 317 } 318 } 319 320 #define GPIO_BANK(x) ((x) >> 5) 321 #define GPIO_OFFSET(x) ((x) & 0x1f) 322 #define GPIO_BIT(x) BIT(GPIO_OFFSET(x)) 323 324 static const struct aspeed_gpio_bank *to_bank(unsigned int offset) 325 { 326 unsigned int bank = GPIO_BANK(offset); 327 328 WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks)); 329 return &aspeed_gpio_banks[bank]; 330 } 331 332 static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props) 333 { 334 return !(props->input || props->output); 335 } 336 337 static inline const struct aspeed_bank_props *find_bank_props( 338 struct aspeed_gpio *gpio, unsigned int offset) 339 { 340 const struct aspeed_bank_props *props = gpio->config->props; 341 342 while (!is_bank_props_sentinel(props)) { 343 if (props->bank == GPIO_BANK(offset)) 344 return props; 345 props++; 346 } 347 348 return NULL; 349 } 350 351 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset) 352 { 353 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 354 355 if (offset >= gpio->chip.ngpio) 356 return false; 357 358 return (!props || ((props->input | props->output) & GPIO_BIT(offset))); 359 } 360 361 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset) 362 { 363 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 364 365 return !props || (props->input & GPIO_BIT(offset)); 366 } 367 368 #define have_irq(g, o) have_input((g), (o)) 369 #define have_debounce(g, o) have_input((g), (o)) 370 371 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset) 372 { 373 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 374 375 return !props || (props->output & GPIO_BIT(offset)); 376 } 377 378 static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio, unsigned int offset, int cmdsrc) 379 { 380 if (gpio->config->llops->privilege_ctrl) 381 gpio->config->llops->privilege_ctrl(gpio, offset, cmdsrc); 382 } 383 384 static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio, 385 unsigned int offset) 386 { 387 if (gpio->config->llops->copro_request) 388 return gpio->config->llops->copro_request(gpio, offset); 389 390 return false; 391 } 392 393 static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio, 394 unsigned int offset) 395 { 396 if (gpio->config->llops->copro_release) 397 gpio->config->llops->copro_release(gpio, offset); 398 } 399 400 static bool aspeed_gpio_support_copro(struct aspeed_gpio *gpio) 401 { 402 return gpio->config->llops->copro_request && gpio->config->llops->copro_release && 403 gpio->config->llops->privilege_ctrl && gpio->config->llops->privilege_init; 404 } 405 406 static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset) 407 { 408 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 409 410 return gpio->config->llops->reg_bit_get(gpio, offset, reg_val); 411 } 412 413 static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, 414 int val) 415 { 416 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 417 418 gpio->config->llops->reg_bit_set(gpio, offset, reg_val, val); 419 /* Flush write */ 420 gpio->config->llops->reg_bit_get(gpio, offset, reg_val); 421 } 422 423 static int aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, int val) 424 { 425 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 426 bool copro = false; 427 428 guard(raw_spinlock_irqsave)(&gpio->lock); 429 430 copro = aspeed_gpio_copro_request(gpio, offset); 431 432 __aspeed_gpio_set(gc, offset, val); 433 434 if (copro) 435 aspeed_gpio_copro_release(gpio, offset); 436 437 return 0; 438 } 439 440 static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset) 441 { 442 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 443 bool copro = false; 444 445 if (!have_input(gpio, offset)) 446 return -ENOTSUPP; 447 448 guard(raw_spinlock_irqsave)(&gpio->lock); 449 450 copro = aspeed_gpio_copro_request(gpio, offset); 451 gpio->config->llops->reg_bit_set(gpio, offset, reg_dir, 0); 452 if (copro) 453 aspeed_gpio_copro_release(gpio, offset); 454 455 return 0; 456 } 457 458 static int aspeed_gpio_dir_out(struct gpio_chip *gc, 459 unsigned int offset, int val) 460 { 461 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 462 bool copro = false; 463 464 if (!have_output(gpio, offset)) 465 return -ENOTSUPP; 466 467 guard(raw_spinlock_irqsave)(&gpio->lock); 468 469 copro = aspeed_gpio_copro_request(gpio, offset); 470 __aspeed_gpio_set(gc, offset, val); 471 gpio->config->llops->reg_bit_set(gpio, offset, reg_dir, 1); 472 473 if (copro) 474 aspeed_gpio_copro_release(gpio, offset); 475 476 return 0; 477 } 478 479 static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 480 { 481 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 482 u32 val; 483 484 if (!have_input(gpio, offset)) 485 return GPIO_LINE_DIRECTION_OUT; 486 487 if (!have_output(gpio, offset)) 488 return GPIO_LINE_DIRECTION_IN; 489 490 guard(raw_spinlock_irqsave)(&gpio->lock); 491 492 val = gpio->config->llops->reg_bit_get(gpio, offset, reg_dir); 493 494 return val ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 495 } 496 497 static inline int irqd_to_aspeed_gpio_data(struct irq_data *d, 498 struct aspeed_gpio **gpio, 499 int *offset) 500 { 501 struct aspeed_gpio *internal; 502 503 *offset = irqd_to_hwirq(d); 504 505 internal = irq_data_get_irq_chip_data(d); 506 507 /* This might be a bit of a questionable place to check */ 508 if (!have_irq(internal, *offset)) 509 return -ENOTSUPP; 510 511 *gpio = internal; 512 513 return 0; 514 } 515 516 static void aspeed_gpio_irq_ack(struct irq_data *d) 517 { 518 struct aspeed_gpio *gpio; 519 int rc, offset; 520 bool copro = false; 521 522 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset); 523 if (rc) 524 return; 525 526 guard(raw_spinlock_irqsave)(&gpio->lock); 527 528 copro = aspeed_gpio_copro_request(gpio, offset); 529 530 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_status, 1); 531 532 if (copro) 533 aspeed_gpio_copro_release(gpio, offset); 534 } 535 536 static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set) 537 { 538 struct aspeed_gpio *gpio; 539 int rc, offset; 540 bool copro = false; 541 542 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset); 543 if (rc) 544 return; 545 546 /* Unmasking the IRQ */ 547 if (set) 548 gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d)); 549 550 guard(raw_spinlock_irqsave)(&gpio->lock); 551 552 copro = aspeed_gpio_copro_request(gpio, offset); 553 554 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_enable, set); 555 556 if (copro) 557 aspeed_gpio_copro_release(gpio, offset); 558 559 /* Masking the IRQ */ 560 if (!set) 561 gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(d)); 562 } 563 564 static void aspeed_gpio_irq_mask(struct irq_data *d) 565 { 566 aspeed_gpio_irq_set_mask(d, false); 567 } 568 569 static void aspeed_gpio_irq_unmask(struct irq_data *d) 570 { 571 aspeed_gpio_irq_set_mask(d, true); 572 } 573 574 static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type) 575 { 576 u32 type0 = 0; 577 u32 type1 = 0; 578 u32 type2 = 0; 579 irq_flow_handler_t handler; 580 struct aspeed_gpio *gpio; 581 int rc, offset; 582 bool copro = false; 583 584 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset); 585 if (rc) 586 return -EINVAL; 587 588 switch (type & IRQ_TYPE_SENSE_MASK) { 589 case IRQ_TYPE_EDGE_BOTH: 590 type2 = 1; 591 fallthrough; 592 case IRQ_TYPE_EDGE_RISING: 593 type0 = 1; 594 fallthrough; 595 case IRQ_TYPE_EDGE_FALLING: 596 handler = handle_edge_irq; 597 break; 598 case IRQ_TYPE_LEVEL_HIGH: 599 type0 = 1; 600 fallthrough; 601 case IRQ_TYPE_LEVEL_LOW: 602 type1 = 1; 603 handler = handle_level_irq; 604 break; 605 default: 606 return -EINVAL; 607 } 608 609 scoped_guard(raw_spinlock_irqsave, &gpio->lock) { 610 copro = aspeed_gpio_copro_request(gpio, offset); 611 612 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type0, 613 type0); 614 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type1, 615 type1); 616 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type2, 617 type2); 618 619 if (copro) 620 aspeed_gpio_copro_release(gpio, offset); 621 } 622 623 irq_set_handler_locked(d, handler); 624 625 return 0; 626 } 627 628 static void aspeed_gpio_irq_handler(struct irq_desc *desc) 629 { 630 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 631 struct irq_chip *ic = irq_desc_get_chip(desc); 632 unsigned int i, p, banks; 633 unsigned long reg; 634 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 635 636 chained_irq_enter(ic, desc); 637 638 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); 639 for (i = 0; i < banks; i++) { 640 reg = gpio->config->llops->reg_bank_get(gpio, i * 32, reg_irq_status); 641 642 for_each_set_bit(p, ®, 32) 643 generic_handle_domain_irq(gc->irq.domain, i * 32 + p); 644 } 645 646 chained_irq_exit(ic, desc); 647 } 648 649 static void aspeed_init_irq_valid_mask(struct gpio_chip *gc, 650 unsigned long *valid_mask, 651 unsigned int ngpios) 652 { 653 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 654 const struct aspeed_bank_props *props = gpio->config->props; 655 656 while (!is_bank_props_sentinel(props)) { 657 unsigned int offset; 658 const unsigned long int input = props->input; 659 660 /* Pretty crummy approach, but similar to GPIO core */ 661 for_each_clear_bit(offset, &input, 32) { 662 unsigned int i = props->bank * 32 + offset; 663 664 if (i >= gpio->chip.ngpio) 665 break; 666 667 clear_bit(i, valid_mask); 668 } 669 670 props++; 671 } 672 } 673 674 static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip, 675 unsigned int offset, bool enable) 676 { 677 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 678 bool copro = false; 679 680 guard(raw_spinlock_irqsave)(&gpio->lock); 681 682 copro = aspeed_gpio_copro_request(gpio, offset); 683 684 gpio->config->llops->reg_bit_set(gpio, offset, reg_tolerance, enable); 685 686 if (copro) 687 aspeed_gpio_copro_release(gpio, offset); 688 689 return 0; 690 } 691 692 static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset) 693 { 694 if (!have_gpio(gpiochip_get_data(chip), offset)) 695 return -ENODEV; 696 697 return pinctrl_gpio_request(chip, offset); 698 } 699 700 static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset) 701 { 702 pinctrl_gpio_free(chip, offset); 703 } 704 705 static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs, 706 u32 *cycles) 707 { 708 u64 rate; 709 u64 n; 710 u32 r; 711 712 rate = clk_get_rate(gpio->clk); 713 if (!rate) 714 return -ENOTSUPP; 715 716 n = rate * usecs; 717 r = do_div(n, 1000000); 718 719 if (n >= U32_MAX) 720 return -ERANGE; 721 722 /* At least as long as the requested time */ 723 *cycles = n + (!!r); 724 725 return 0; 726 } 727 728 /* Call under gpio->lock */ 729 static int register_allocated_timer(struct aspeed_gpio *gpio, 730 unsigned int offset, unsigned int timer) 731 { 732 if (WARN(gpio->offset_timer[offset] != 0, 733 "Offset %d already allocated timer %d\n", 734 offset, gpio->offset_timer[offset])) 735 return -EINVAL; 736 737 if (WARN(gpio->timer_users[timer] == UINT_MAX, 738 "Timer user count would overflow\n")) 739 return -EPERM; 740 741 gpio->offset_timer[offset] = timer; 742 gpio->timer_users[timer]++; 743 744 return 0; 745 } 746 747 /* Call under gpio->lock */ 748 static int unregister_allocated_timer(struct aspeed_gpio *gpio, 749 unsigned int offset) 750 { 751 if (WARN(gpio->offset_timer[offset] == 0, 752 "No timer allocated to offset %d\n", offset)) 753 return -EINVAL; 754 755 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0, 756 "No users recorded for timer %d\n", 757 gpio->offset_timer[offset])) 758 return -EINVAL; 759 760 gpio->timer_users[gpio->offset_timer[offset]]--; 761 gpio->offset_timer[offset] = 0; 762 763 return 0; 764 } 765 766 /* Call under gpio->lock */ 767 static inline bool timer_allocation_registered(struct aspeed_gpio *gpio, 768 unsigned int offset) 769 { 770 return gpio->offset_timer[offset] > 0; 771 } 772 773 /* Call under gpio->lock */ 774 static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset, 775 unsigned int timer) 776 { 777 /* Note: Debounce timer isn't under control of the command 778 * source registers, so no need to sync with the coprocessor 779 */ 780 gpio->config->llops->reg_bit_set(gpio, offset, reg_debounce_sel1, !!(timer & BIT(1))); 781 gpio->config->llops->reg_bit_set(gpio, offset, reg_debounce_sel2, !!(timer & BIT(0))); 782 } 783 784 static int enable_debounce(struct gpio_chip *chip, unsigned int offset, 785 unsigned long usecs) 786 { 787 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 788 u32 requested_cycles; 789 int rc; 790 int i; 791 792 if (!gpio->clk) 793 return -EINVAL; 794 795 rc = usecs_to_cycles(gpio, usecs, &requested_cycles); 796 if (rc < 0) { 797 dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n", 798 usecs, clk_get_rate(gpio->clk), rc); 799 return rc; 800 } 801 802 guard(raw_spinlock_irqsave)(&gpio->lock); 803 804 if (timer_allocation_registered(gpio, offset)) { 805 rc = unregister_allocated_timer(gpio, offset); 806 if (rc < 0) 807 return rc; 808 } 809 810 /* Try to find a timer already configured for the debounce period */ 811 for (i = 1; i < gpio->config->debounce_timers_num; i++) { 812 u32 cycles; 813 814 cycles = ioread32(gpio->base + gpio->config->debounce_timers_array[i]); 815 if (requested_cycles == cycles) 816 break; 817 } 818 819 if (i == gpio->config->debounce_timers_num) { 820 int j; 821 822 /* 823 * As there are no timers configured for the requested debounce 824 * period, find an unused timer instead 825 */ 826 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) { 827 if (gpio->timer_users[j] == 0) 828 break; 829 } 830 831 if (j == ARRAY_SIZE(gpio->timer_users)) { 832 dev_warn(chip->parent, 833 "Debounce timers exhausted, cannot debounce for period %luus\n", 834 usecs); 835 836 rc = -EPERM; 837 838 /* 839 * We already adjusted the accounting to remove @offset 840 * as a user of its previous timer, so also configure 841 * the hardware so @offset has timers disabled for 842 * consistency. 843 */ 844 configure_timer(gpio, offset, 0); 845 return rc; 846 } 847 848 i = j; 849 850 iowrite32(requested_cycles, gpio->base + gpio->config->debounce_timers_array[i]); 851 } 852 853 if (WARN(i == 0, "Cannot register index of disabled timer\n")) 854 return -EINVAL; 855 856 register_allocated_timer(gpio, offset, i); 857 configure_timer(gpio, offset, i); 858 859 return rc; 860 } 861 862 static int disable_debounce(struct gpio_chip *chip, unsigned int offset) 863 { 864 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 865 int rc; 866 867 guard(raw_spinlock_irqsave)(&gpio->lock); 868 869 rc = unregister_allocated_timer(gpio, offset); 870 if (!rc) 871 configure_timer(gpio, offset, 0); 872 873 return rc; 874 } 875 876 static int set_debounce(struct gpio_chip *chip, unsigned int offset, 877 unsigned long usecs) 878 { 879 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 880 881 if (!have_debounce(gpio, offset)) 882 return -ENOTSUPP; 883 884 if (usecs) 885 return enable_debounce(chip, offset, usecs); 886 887 return disable_debounce(chip, offset); 888 } 889 890 static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 891 unsigned long config) 892 { 893 unsigned long param = pinconf_to_config_param(config); 894 u32 arg = pinconf_to_config_argument(config); 895 896 if (param == PIN_CONFIG_INPUT_DEBOUNCE) 897 return set_debounce(chip, offset, arg); 898 else if (param == PIN_CONFIG_BIAS_DISABLE || 899 param == PIN_CONFIG_BIAS_PULL_DOWN || 900 param == PIN_CONFIG_DRIVE_STRENGTH) 901 return pinctrl_gpio_set_config(chip, offset, config); 902 else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN || 903 param == PIN_CONFIG_DRIVE_OPEN_SOURCE) 904 /* Return -ENOTSUPP to trigger emulation, as per datasheet */ 905 return -ENOTSUPP; 906 else if (param == PIN_CONFIG_PERSIST_STATE) 907 return aspeed_gpio_reset_tolerance(chip, offset, arg); 908 909 return -ENOTSUPP; 910 } 911 912 /** 913 * aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with 914 * the coprocessor for shared GPIO banks 915 * @ops: The callbacks 916 * @data: Pointer passed back to the callbacks 917 */ 918 int aspeed_gpio_copro_set_ops(const struct aspeed_gpio_copro_ops *ops, void *data) 919 { 920 copro_data = data; 921 copro_ops = ops; 922 923 return 0; 924 } 925 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_set_ops); 926 927 /** 928 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire 929 * bank gets marked and any access from the ARM will 930 * result in handshaking via callbacks. 931 * @desc: The GPIO to be marked 932 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space 933 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space 934 * @bit: If non-NULL, returns the bit number of the GPIO in the registers 935 */ 936 int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc, 937 u16 *vreg_offset, u16 *dreg_offset, u8 *bit) 938 { 939 struct gpio_chip *chip = gpiod_to_chip(desc); 940 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 941 int rc = 0, bindex, offset = gpiod_hwgpio(desc); 942 const struct aspeed_gpio_bank *bank = to_bank(offset); 943 944 if (!aspeed_gpio_support_copro(gpio)) 945 return -EOPNOTSUPP; 946 947 if (!gpio->cf_copro_bankmap) 948 gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL); 949 if (!gpio->cf_copro_bankmap) 950 return -ENOMEM; 951 if (offset < 0 || offset > gpio->chip.ngpio) 952 return -EINVAL; 953 bindex = offset >> 3; 954 955 guard(raw_spinlock_irqsave)(&gpio->lock); 956 957 /* Sanity check, this shouldn't happen */ 958 if (gpio->cf_copro_bankmap[bindex] == 0xff) 959 return -EIO; 960 961 gpio->cf_copro_bankmap[bindex]++; 962 963 /* Switch command source */ 964 if (gpio->cf_copro_bankmap[bindex] == 1) 965 aspeed_gpio_change_cmd_source(gpio, offset, 966 GPIO_CMDSRC_COLDFIRE); 967 968 if (vreg_offset) 969 *vreg_offset = bank->val_regs; 970 if (dreg_offset) 971 *dreg_offset = bank->rdata_reg; 972 if (bit) 973 *bit = GPIO_OFFSET(offset); 974 return rc; 975 } 976 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio); 977 978 /** 979 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor. 980 * @desc: The GPIO to be marked 981 */ 982 int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc) 983 { 984 struct gpio_chip *chip = gpiod_to_chip(desc); 985 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 986 int rc = 0, bindex, offset = gpiod_hwgpio(desc); 987 988 if (!aspeed_gpio_support_copro(gpio)) 989 return -EOPNOTSUPP; 990 991 if (!gpio->cf_copro_bankmap) 992 return -ENXIO; 993 994 if (offset < 0 || offset > gpio->chip.ngpio) 995 return -EINVAL; 996 bindex = offset >> 3; 997 998 guard(raw_spinlock_irqsave)(&gpio->lock); 999 1000 /* Sanity check, this shouldn't happen */ 1001 if (gpio->cf_copro_bankmap[bindex] == 0) 1002 return -EIO; 1003 1004 gpio->cf_copro_bankmap[bindex]--; 1005 1006 /* Switch command source */ 1007 if (gpio->cf_copro_bankmap[bindex] == 0) 1008 aspeed_gpio_change_cmd_source(gpio, offset, 1009 GPIO_CMDSRC_ARM); 1010 1011 return rc; 1012 } 1013 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio); 1014 1015 static void aspeed_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p) 1016 { 1017 struct aspeed_gpio *gpio; 1018 int rc, offset; 1019 1020 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset); 1021 if (rc) 1022 return; 1023 1024 seq_puts(p, dev_name(gpio->dev)); 1025 } 1026 1027 static const struct irq_chip aspeed_gpio_irq_chip = { 1028 .irq_ack = aspeed_gpio_irq_ack, 1029 .irq_mask = aspeed_gpio_irq_mask, 1030 .irq_unmask = aspeed_gpio_irq_unmask, 1031 .irq_set_type = aspeed_gpio_set_type, 1032 .irq_print_chip = aspeed_gpio_irq_print_chip, 1033 .flags = IRQCHIP_IMMUTABLE, 1034 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1035 }; 1036 1037 static void aspeed_g4_reg_bit_set(struct aspeed_gpio *gpio, unsigned int offset, 1038 const enum aspeed_gpio_reg reg, bool val) 1039 { 1040 const struct aspeed_gpio_bank *bank = to_bank(offset); 1041 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg); 1042 u32 temp; 1043 1044 if (reg == reg_val) 1045 temp = gpio->dcache[GPIO_BANK(offset)]; 1046 else 1047 temp = ioread32(addr); 1048 1049 if (val) 1050 temp |= GPIO_BIT(offset); 1051 else 1052 temp &= ~GPIO_BIT(offset); 1053 1054 if (reg == reg_val) 1055 gpio->dcache[GPIO_BANK(offset)] = temp; 1056 iowrite32(temp, addr); 1057 } 1058 1059 static bool aspeed_g4_reg_bit_get(struct aspeed_gpio *gpio, unsigned int offset, 1060 const enum aspeed_gpio_reg reg) 1061 { 1062 const struct aspeed_gpio_bank *bank = to_bank(offset); 1063 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg); 1064 1065 return !!(ioread32(addr) & GPIO_BIT(offset)); 1066 } 1067 1068 static int aspeed_g4_reg_bank_get(struct aspeed_gpio *gpio, unsigned int offset, 1069 const enum aspeed_gpio_reg reg) 1070 { 1071 const struct aspeed_gpio_bank *bank = to_bank(offset); 1072 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg); 1073 1074 if (reg == reg_rdata || reg == reg_irq_status) 1075 return ioread32(addr); 1076 else 1077 return -EOPNOTSUPP; 1078 } 1079 1080 static void aspeed_g4_privilege_ctrl(struct aspeed_gpio *gpio, unsigned int offset, int cmdsrc) 1081 { 1082 /* 1083 * The command source register is only valid in bits 0, 8, 16, and 24, so we use 1084 * (offset & ~(0x7)) to ensure that reg_bits_set always targets a valid bit. 1085 */ 1086 /* Source 1 first to avoid illegal 11 combination */ 1087 aspeed_g4_reg_bit_set(gpio, offset & ~(0x7), reg_cmdsrc1, !!(cmdsrc & BIT(1))); 1088 /* Then Source 0 */ 1089 aspeed_g4_reg_bit_set(gpio, offset & ~(0x7), reg_cmdsrc0, !!(cmdsrc & BIT(0))); 1090 } 1091 1092 static void aspeed_g4_privilege_init(struct aspeed_gpio *gpio) 1093 { 1094 u32 i; 1095 1096 /* Switch all command sources to the ARM by default */ 1097 for (i = 0; i < DIV_ROUND_UP(gpio->chip.ngpio, 32); i++) { 1098 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 0, GPIO_CMDSRC_ARM); 1099 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 8, GPIO_CMDSRC_ARM); 1100 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 16, GPIO_CMDSRC_ARM); 1101 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 24, GPIO_CMDSRC_ARM); 1102 } 1103 } 1104 1105 static bool aspeed_g4_copro_request(struct aspeed_gpio *gpio, unsigned int offset) 1106 { 1107 if (!copro_ops || !gpio->cf_copro_bankmap) 1108 return false; 1109 if (!gpio->cf_copro_bankmap[offset >> 3]) 1110 return false; 1111 if (!copro_ops->request_access) 1112 return false; 1113 1114 /* Pause the coprocessor */ 1115 copro_ops->request_access(copro_data); 1116 1117 /* Change command source back to ARM */ 1118 aspeed_g4_privilege_ctrl(gpio, offset, GPIO_CMDSRC_ARM); 1119 1120 /* Update cache */ 1121 gpio->dcache[GPIO_BANK(offset)] = aspeed_g4_reg_bank_get(gpio, offset, reg_rdata); 1122 1123 return true; 1124 } 1125 1126 static void aspeed_g4_copro_release(struct aspeed_gpio *gpio, unsigned int offset) 1127 { 1128 if (!copro_ops || !gpio->cf_copro_bankmap) 1129 return; 1130 if (!gpio->cf_copro_bankmap[offset >> 3]) 1131 return; 1132 if (!copro_ops->release_access) 1133 return; 1134 1135 /* Change command source back to ColdFire */ 1136 aspeed_g4_privilege_ctrl(gpio, offset, GPIO_CMDSRC_COLDFIRE); 1137 1138 /* Restart the coprocessor */ 1139 copro_ops->release_access(copro_data); 1140 } 1141 1142 static const struct aspeed_gpio_llops aspeed_g4_llops = { 1143 .reg_bit_set = aspeed_g4_reg_bit_set, 1144 .reg_bit_get = aspeed_g4_reg_bit_get, 1145 .reg_bank_get = aspeed_g4_reg_bank_get, 1146 .privilege_ctrl = aspeed_g4_privilege_ctrl, 1147 .privilege_init = aspeed_g4_privilege_init, 1148 .copro_request = aspeed_g4_copro_request, 1149 .copro_release = aspeed_g4_copro_release, 1150 }; 1151 1152 static void aspeed_g7_reg_bit_set(struct aspeed_gpio *gpio, unsigned int offset, 1153 const enum aspeed_gpio_reg reg, bool val) 1154 { 1155 u32 mask = aspeed_gpio_g7_reg_mask(reg); 1156 void __iomem *addr = gpio->base + GPIO_G7_CTRL_REG_OFFSET(offset); 1157 u32 write_val; 1158 1159 if (mask) { 1160 write_val = (ioread32(addr) & ~(mask)) | field_prep(mask, val); 1161 iowrite32(write_val, addr); 1162 } 1163 } 1164 1165 static bool aspeed_g7_reg_bit_get(struct aspeed_gpio *gpio, unsigned int offset, 1166 const enum aspeed_gpio_reg reg) 1167 { 1168 u32 mask = aspeed_gpio_g7_reg_mask(reg); 1169 void __iomem *addr; 1170 1171 addr = gpio->base + GPIO_G7_CTRL_REG_OFFSET(offset); 1172 if (reg == reg_val) 1173 mask = GPIO_G7_CTRL_IN_DATA; 1174 1175 if (mask) 1176 return field_get(mask, ioread32(addr)); 1177 else 1178 return 0; 1179 } 1180 1181 static int aspeed_g7_reg_bank_get(struct aspeed_gpio *gpio, unsigned int offset, 1182 const enum aspeed_gpio_reg reg) 1183 { 1184 void __iomem *addr; 1185 1186 if (reg == reg_irq_status) { 1187 addr = gpio->base + GPIO_G7_IRQ_STS_OFFSET(offset >> 5); 1188 return ioread32(addr); 1189 } else { 1190 return -EOPNOTSUPP; 1191 } 1192 } 1193 1194 static const struct aspeed_gpio_llops aspeed_g7_llops = { 1195 .reg_bit_set = aspeed_g7_reg_bit_set, 1196 .reg_bit_get = aspeed_g7_reg_bit_get, 1197 .reg_bank_get = aspeed_g7_reg_bank_get, 1198 .privilege_ctrl = NULL, 1199 .privilege_init = NULL, 1200 .copro_request = NULL, 1201 .copro_release = NULL, 1202 }; 1203 1204 /* 1205 * Any banks not specified in a struct aspeed_bank_props array are assumed to 1206 * have the properties: 1207 * 1208 * { .input = 0xffffffff, .output = 0xffffffff } 1209 */ 1210 1211 static const struct aspeed_bank_props ast2400_bank_props[] = { 1212 /* input output */ 1213 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ 1214 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */ 1215 { }, 1216 }; 1217 1218 static const struct aspeed_gpio_config ast2400_config = 1219 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */ 1220 { 1221 .nr_gpios = 220, 1222 .props = ast2400_bank_props, 1223 .llops = &aspeed_g4_llops, 1224 .debounce_timers_array = debounce_timers, 1225 .debounce_timers_num = ARRAY_SIZE(debounce_timers), 1226 .require_dcache = true, 1227 }; 1228 1229 static const struct aspeed_bank_props ast2500_bank_props[] = { 1230 /* input output */ 1231 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ 1232 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */ 1233 { 7, 0x000000ff, 0x000000ff }, /* AC */ 1234 { }, 1235 }; 1236 1237 static const struct aspeed_gpio_config ast2500_config = 1238 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */ 1239 { 1240 .nr_gpios = 232, 1241 .props = ast2500_bank_props, 1242 .llops = &aspeed_g4_llops, 1243 .debounce_timers_array = debounce_timers, 1244 .debounce_timers_num = ARRAY_SIZE(debounce_timers), 1245 .require_dcache = true, 1246 }; 1247 1248 static const struct aspeed_bank_props ast2600_bank_props[] = { 1249 /* input output */ 1250 {4, 0xffffffff, 0x00ffffff}, /* Q/R/S/T */ 1251 {5, 0xffffffff, 0xffffff00}, /* U/V/W/X */ 1252 {6, 0x0000ffff, 0x0000ffff}, /* Y/Z */ 1253 { }, 1254 }; 1255 1256 static const struct aspeed_gpio_config ast2600_config = 1257 /* 1258 * ast2600 has two controllers one with 208 GPIOs and one with 36 GPIOs. 1259 * We expect ngpio being set in the device tree and this is a fallback 1260 * option. 1261 */ 1262 { 1263 .nr_gpios = 208, 1264 .props = ast2600_bank_props, 1265 .llops = &aspeed_g4_llops, 1266 .debounce_timers_array = debounce_timers, 1267 .debounce_timers_num = ARRAY_SIZE(debounce_timers), 1268 .require_dcache = true, 1269 }; 1270 1271 static const struct aspeed_bank_props ast2700_bank_props[] = { 1272 /* input output */ 1273 { 1, 0x0fffffff, 0x0fffffff }, /* E/F/G/H, 4-GPIO hole */ 1274 { 6, 0x00ffffff, 0x00ff0000 }, /* Y/Z/AA */ 1275 {}, 1276 }; 1277 1278 static const struct aspeed_gpio_config ast2700_config = 1279 /* 1280 * ast2700 has two controllers one with 212 GPIOs and one with 16 GPIOs. 1281 * 216 for simplicity, actual number is 212 (4-GPIO hole in GPIOH) 1282 * We expect ngpio being set in the device tree and this is a fallback 1283 * option. 1284 */ 1285 { 1286 .nr_gpios = 216, 1287 .props = ast2700_bank_props, 1288 .llops = &aspeed_g7_llops, 1289 .debounce_timers_array = g7_debounce_timers, 1290 .debounce_timers_num = ARRAY_SIZE(g7_debounce_timers), 1291 .require_dcache = false, 1292 }; 1293 1294 static const struct of_device_id aspeed_gpio_of_table[] = { 1295 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, }, 1296 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, }, 1297 { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, }, 1298 { .compatible = "aspeed,ast2700-gpio", .data = &ast2700_config, }, 1299 {} 1300 }; 1301 MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table); 1302 1303 static int aspeed_gpio_probe(struct platform_device *pdev) 1304 { 1305 const struct of_device_id *gpio_id; 1306 struct gpio_irq_chip *girq; 1307 struct aspeed_gpio *gpio; 1308 int rc, irq, i, banks, err; 1309 u32 ngpio; 1310 1311 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 1312 if (!gpio) 1313 return -ENOMEM; 1314 1315 gpio->base = devm_platform_ioremap_resource(pdev, 0); 1316 if (IS_ERR(gpio->base)) 1317 return PTR_ERR(gpio->base); 1318 1319 gpio->dev = &pdev->dev; 1320 1321 raw_spin_lock_init(&gpio->lock); 1322 1323 gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); 1324 if (!gpio_id) 1325 return -EINVAL; 1326 1327 gpio->clk = devm_clk_get_enabled(&pdev->dev, NULL); 1328 if (IS_ERR(gpio->clk)) { 1329 dev_warn(&pdev->dev, 1330 "Failed to get clock from devicetree, debouncing disabled\n"); 1331 gpio->clk = NULL; 1332 } 1333 1334 gpio->config = gpio_id->data; 1335 1336 if (!gpio->config->llops->reg_bit_set || !gpio->config->llops->reg_bit_get || 1337 !gpio->config->llops->reg_bank_get) 1338 return -EINVAL; 1339 1340 gpio->chip.parent = &pdev->dev; 1341 err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio); 1342 gpio->chip.ngpio = (u16) ngpio; 1343 if (err) 1344 gpio->chip.ngpio = gpio->config->nr_gpios; 1345 gpio->chip.direction_input = aspeed_gpio_dir_in; 1346 gpio->chip.direction_output = aspeed_gpio_dir_out; 1347 gpio->chip.get_direction = aspeed_gpio_get_direction; 1348 gpio->chip.request = aspeed_gpio_request; 1349 gpio->chip.free = aspeed_gpio_free; 1350 gpio->chip.get = aspeed_gpio_get; 1351 gpio->chip.set = aspeed_gpio_set; 1352 gpio->chip.set_config = aspeed_gpio_set_config; 1353 gpio->chip.label = dev_name(&pdev->dev); 1354 gpio->chip.base = -1; 1355 1356 if (gpio->config->require_dcache) { 1357 /* Allocate a cache of the output registers */ 1358 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); 1359 gpio->dcache = devm_kcalloc(&pdev->dev, banks, sizeof(u32), GFP_KERNEL); 1360 if (!gpio->dcache) 1361 return -ENOMEM; 1362 /* 1363 * Populate it with initial values read from the HW 1364 */ 1365 for (i = 0; i < banks; i++) 1366 gpio->dcache[i] = 1367 gpio->config->llops->reg_bank_get(gpio, (i << 5), reg_rdata); 1368 } 1369 1370 if (gpio->config->llops->privilege_init) 1371 gpio->config->llops->privilege_init(gpio); 1372 1373 /* Set up an irqchip */ 1374 irq = platform_get_irq(pdev, 0); 1375 if (irq < 0) 1376 return irq; 1377 gpio->irq = irq; 1378 girq = &gpio->chip.irq; 1379 gpio_irq_chip_set_chip(girq, &aspeed_gpio_irq_chip); 1380 1381 girq->parent_handler = aspeed_gpio_irq_handler; 1382 girq->num_parents = 1; 1383 girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), GFP_KERNEL); 1384 if (!girq->parents) 1385 return -ENOMEM; 1386 girq->parents[0] = gpio->irq; 1387 girq->default_type = IRQ_TYPE_NONE; 1388 girq->handler = handle_bad_irq; 1389 girq->init_valid_mask = aspeed_init_irq_valid_mask; 1390 1391 gpio->offset_timer = 1392 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL); 1393 if (!gpio->offset_timer) 1394 return -ENOMEM; 1395 1396 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); 1397 if (rc < 0) 1398 return rc; 1399 1400 return 0; 1401 } 1402 1403 static struct platform_driver aspeed_gpio_driver = { 1404 .probe = aspeed_gpio_probe, 1405 .driver = { 1406 .name = KBUILD_MODNAME, 1407 .of_match_table = aspeed_gpio_of_table, 1408 }, 1409 }; 1410 1411 module_platform_driver(aspeed_gpio_driver); 1412 1413 MODULE_DESCRIPTION("Aspeed GPIO Driver"); 1414 MODULE_LICENSE("GPL"); 1415