1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2015 IBM Corp. 4 * 5 * Joel Stanley <joel@jms.id.au> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/gpio/aspeed.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/hashtable.h> 12 #include <linux/init.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/platform_device.h> 18 #include <linux/seq_file.h> 19 #include <linux/spinlock.h> 20 #include <linux/string.h> 21 22 #include <asm/div64.h> 23 24 /* 25 * These two headers aren't meant to be used by GPIO drivers. We need 26 * them in order to access gpio_chip_hwgpio() which we need to implement 27 * the aspeed specific API which allows the coprocessor to request 28 * access to some GPIOs and to arbitrate between coprocessor and ARM. 29 */ 30 #include <linux/gpio/consumer.h> 31 #include "gpiolib.h" 32 33 struct aspeed_bank_props { 34 unsigned int bank; 35 u32 input; 36 u32 output; 37 }; 38 39 struct aspeed_gpio_config { 40 unsigned int nr_gpios; 41 const struct aspeed_bank_props *props; 42 }; 43 44 /* 45 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled 46 * @timer_users: Tracks the number of users for each timer 47 * 48 * The @timer_users has four elements but the first element is unused. This is 49 * to simplify accounting and indexing, as a zero value in @offset_timer 50 * represents disabled debouncing for the GPIO. Any other value for an element 51 * of @offset_timer is used as an index into @timer_users. This behaviour of 52 * the zero value aligns with the behaviour of zero built from the timer 53 * configuration registers (i.e. debouncing is disabled). 54 */ 55 struct aspeed_gpio { 56 struct gpio_chip chip; 57 struct device *dev; 58 raw_spinlock_t lock; 59 void __iomem *base; 60 int irq; 61 const struct aspeed_gpio_config *config; 62 63 u8 *offset_timer; 64 unsigned int timer_users[4]; 65 struct clk *clk; 66 67 u32 *dcache; 68 u8 *cf_copro_bankmap; 69 }; 70 71 struct aspeed_gpio_bank { 72 uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch 73 * +4: Rd/Wr: Direction (0=in, 1=out) 74 */ 75 uint16_t rdata_reg; /* Rd: read write latch, Wr: <none> */ 76 uint16_t irq_regs; 77 uint16_t debounce_regs; 78 uint16_t tolerance_regs; 79 uint16_t cmdsrc_regs; 80 const char names[4][3]; 81 }; 82 83 /* 84 * Note: The "value" register returns the input value sampled on the 85 * line even when the GPIO is configured as an output. Since 86 * that input goes through synchronizers, writing, then reading 87 * back may not return the written value right away. 88 * 89 * The "rdata" register returns the content of the write latch 90 * and thus can be used to read back what was last written 91 * reliably. 92 */ 93 94 static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 }; 95 96 static const struct aspeed_gpio_copro_ops *copro_ops; 97 static void *copro_data; 98 99 static const struct aspeed_gpio_bank aspeed_gpio_banks[] = { 100 { 101 .val_regs = 0x0000, 102 .rdata_reg = 0x00c0, 103 .irq_regs = 0x0008, 104 .debounce_regs = 0x0040, 105 .tolerance_regs = 0x001c, 106 .cmdsrc_regs = 0x0060, 107 .names = { "A", "B", "C", "D" }, 108 }, 109 { 110 .val_regs = 0x0020, 111 .rdata_reg = 0x00c4, 112 .irq_regs = 0x0028, 113 .debounce_regs = 0x0048, 114 .tolerance_regs = 0x003c, 115 .cmdsrc_regs = 0x0068, 116 .names = { "E", "F", "G", "H" }, 117 }, 118 { 119 .val_regs = 0x0070, 120 .rdata_reg = 0x00c8, 121 .irq_regs = 0x0098, 122 .debounce_regs = 0x00b0, 123 .tolerance_regs = 0x00ac, 124 .cmdsrc_regs = 0x0090, 125 .names = { "I", "J", "K", "L" }, 126 }, 127 { 128 .val_regs = 0x0078, 129 .rdata_reg = 0x00cc, 130 .irq_regs = 0x00e8, 131 .debounce_regs = 0x0100, 132 .tolerance_regs = 0x00fc, 133 .cmdsrc_regs = 0x00e0, 134 .names = { "M", "N", "O", "P" }, 135 }, 136 { 137 .val_regs = 0x0080, 138 .rdata_reg = 0x00d0, 139 .irq_regs = 0x0118, 140 .debounce_regs = 0x0130, 141 .tolerance_regs = 0x012c, 142 .cmdsrc_regs = 0x0110, 143 .names = { "Q", "R", "S", "T" }, 144 }, 145 { 146 .val_regs = 0x0088, 147 .rdata_reg = 0x00d4, 148 .irq_regs = 0x0148, 149 .debounce_regs = 0x0160, 150 .tolerance_regs = 0x015c, 151 .cmdsrc_regs = 0x0140, 152 .names = { "U", "V", "W", "X" }, 153 }, 154 { 155 .val_regs = 0x01E0, 156 .rdata_reg = 0x00d8, 157 .irq_regs = 0x0178, 158 .debounce_regs = 0x0190, 159 .tolerance_regs = 0x018c, 160 .cmdsrc_regs = 0x0170, 161 .names = { "Y", "Z", "AA", "AB" }, 162 }, 163 { 164 .val_regs = 0x01e8, 165 .rdata_reg = 0x00dc, 166 .irq_regs = 0x01a8, 167 .debounce_regs = 0x01c0, 168 .tolerance_regs = 0x01bc, 169 .cmdsrc_regs = 0x01a0, 170 .names = { "AC", "", "", "" }, 171 }, 172 }; 173 174 enum aspeed_gpio_reg { 175 reg_val, 176 reg_rdata, 177 reg_dir, 178 reg_irq_enable, 179 reg_irq_type0, 180 reg_irq_type1, 181 reg_irq_type2, 182 reg_irq_status, 183 reg_debounce_sel1, 184 reg_debounce_sel2, 185 reg_tolerance, 186 reg_cmdsrc0, 187 reg_cmdsrc1, 188 }; 189 190 #define GPIO_VAL_VALUE 0x00 191 #define GPIO_VAL_DIR 0x04 192 193 #define GPIO_IRQ_ENABLE 0x00 194 #define GPIO_IRQ_TYPE0 0x04 195 #define GPIO_IRQ_TYPE1 0x08 196 #define GPIO_IRQ_TYPE2 0x0c 197 #define GPIO_IRQ_STATUS 0x10 198 199 #define GPIO_DEBOUNCE_SEL1 0x00 200 #define GPIO_DEBOUNCE_SEL2 0x04 201 202 #define GPIO_CMDSRC_0 0x00 203 #define GPIO_CMDSRC_1 0x04 204 #define GPIO_CMDSRC_ARM 0 205 #define GPIO_CMDSRC_LPC 1 206 #define GPIO_CMDSRC_COLDFIRE 2 207 #define GPIO_CMDSRC_RESERVED 3 208 209 /* This will be resolved at compile time */ 210 static inline void __iomem *bank_reg(struct aspeed_gpio *gpio, 211 const struct aspeed_gpio_bank *bank, 212 const enum aspeed_gpio_reg reg) 213 { 214 switch (reg) { 215 case reg_val: 216 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; 217 case reg_rdata: 218 return gpio->base + bank->rdata_reg; 219 case reg_dir: 220 return gpio->base + bank->val_regs + GPIO_VAL_DIR; 221 case reg_irq_enable: 222 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; 223 case reg_irq_type0: 224 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; 225 case reg_irq_type1: 226 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; 227 case reg_irq_type2: 228 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; 229 case reg_irq_status: 230 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; 231 case reg_debounce_sel1: 232 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1; 233 case reg_debounce_sel2: 234 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2; 235 case reg_tolerance: 236 return gpio->base + bank->tolerance_regs; 237 case reg_cmdsrc0: 238 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0; 239 case reg_cmdsrc1: 240 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1; 241 } 242 BUG(); 243 } 244 245 #define GPIO_BANK(x) ((x) >> 5) 246 #define GPIO_OFFSET(x) ((x) & 0x1f) 247 #define GPIO_BIT(x) BIT(GPIO_OFFSET(x)) 248 249 #define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o)) 250 #define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1) 251 #define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0) 252 253 static const struct aspeed_gpio_bank *to_bank(unsigned int offset) 254 { 255 unsigned int bank = GPIO_BANK(offset); 256 257 WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks)); 258 return &aspeed_gpio_banks[bank]; 259 } 260 261 static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props) 262 { 263 return !(props->input || props->output); 264 } 265 266 static inline const struct aspeed_bank_props *find_bank_props( 267 struct aspeed_gpio *gpio, unsigned int offset) 268 { 269 const struct aspeed_bank_props *props = gpio->config->props; 270 271 while (!is_bank_props_sentinel(props)) { 272 if (props->bank == GPIO_BANK(offset)) 273 return props; 274 props++; 275 } 276 277 return NULL; 278 } 279 280 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset) 281 { 282 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 283 const struct aspeed_gpio_bank *bank = to_bank(offset); 284 unsigned int group = GPIO_OFFSET(offset) / 8; 285 286 return bank->names[group][0] != '\0' && 287 (!props || ((props->input | props->output) & GPIO_BIT(offset))); 288 } 289 290 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset) 291 { 292 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 293 294 return !props || (props->input & GPIO_BIT(offset)); 295 } 296 297 #define have_irq(g, o) have_input((g), (o)) 298 #define have_debounce(g, o) have_input((g), (o)) 299 300 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset) 301 { 302 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 303 304 return !props || (props->output & GPIO_BIT(offset)); 305 } 306 307 static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio, 308 const struct aspeed_gpio_bank *bank, 309 int bindex, int cmdsrc) 310 { 311 void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0); 312 void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1); 313 u32 bit, reg; 314 315 /* 316 * Each register controls 4 banks, so take the bottom 2 317 * bits of the bank index, and use them to select the 318 * right control bit (0, 8, 16 or 24). 319 */ 320 bit = BIT((bindex & 3) << 3); 321 322 /* Source 1 first to avoid illegal 11 combination */ 323 reg = ioread32(c1); 324 if (cmdsrc & 2) 325 reg |= bit; 326 else 327 reg &= ~bit; 328 iowrite32(reg, c1); 329 330 /* Then Source 0 */ 331 reg = ioread32(c0); 332 if (cmdsrc & 1) 333 reg |= bit; 334 else 335 reg &= ~bit; 336 iowrite32(reg, c0); 337 } 338 339 static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio, 340 unsigned int offset) 341 { 342 const struct aspeed_gpio_bank *bank = to_bank(offset); 343 344 if (!copro_ops || !gpio->cf_copro_bankmap) 345 return false; 346 if (!gpio->cf_copro_bankmap[offset >> 3]) 347 return false; 348 if (!copro_ops->request_access) 349 return false; 350 351 /* Pause the coprocessor */ 352 copro_ops->request_access(copro_data); 353 354 /* Change command source back to ARM */ 355 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, GPIO_CMDSRC_ARM); 356 357 /* Update cache */ 358 gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata)); 359 360 return true; 361 } 362 363 static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio, 364 unsigned int offset) 365 { 366 const struct aspeed_gpio_bank *bank = to_bank(offset); 367 368 if (!copro_ops || !gpio->cf_copro_bankmap) 369 return; 370 if (!gpio->cf_copro_bankmap[offset >> 3]) 371 return; 372 if (!copro_ops->release_access) 373 return; 374 375 /* Change command source back to ColdFire */ 376 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, 377 GPIO_CMDSRC_COLDFIRE); 378 379 /* Restart the coprocessor */ 380 copro_ops->release_access(copro_data); 381 } 382 383 static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset) 384 { 385 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 386 const struct aspeed_gpio_bank *bank = to_bank(offset); 387 388 return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset)); 389 } 390 391 static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, 392 int val) 393 { 394 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 395 const struct aspeed_gpio_bank *bank = to_bank(offset); 396 void __iomem *addr; 397 u32 reg; 398 399 addr = bank_reg(gpio, bank, reg_val); 400 reg = gpio->dcache[GPIO_BANK(offset)]; 401 402 if (val) 403 reg |= GPIO_BIT(offset); 404 else 405 reg &= ~GPIO_BIT(offset); 406 gpio->dcache[GPIO_BANK(offset)] = reg; 407 408 iowrite32(reg, addr); 409 /* Flush write */ 410 ioread32(addr); 411 } 412 413 static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, 414 int val) 415 { 416 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 417 unsigned long flags; 418 bool copro; 419 420 raw_spin_lock_irqsave(&gpio->lock, flags); 421 copro = aspeed_gpio_copro_request(gpio, offset); 422 423 __aspeed_gpio_set(gc, offset, val); 424 425 if (copro) 426 aspeed_gpio_copro_release(gpio, offset); 427 raw_spin_unlock_irqrestore(&gpio->lock, flags); 428 } 429 430 static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset) 431 { 432 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 433 const struct aspeed_gpio_bank *bank = to_bank(offset); 434 void __iomem *addr = bank_reg(gpio, bank, reg_dir); 435 unsigned long flags; 436 bool copro; 437 u32 reg; 438 439 if (!have_input(gpio, offset)) 440 return -ENOTSUPP; 441 442 raw_spin_lock_irqsave(&gpio->lock, flags); 443 444 reg = ioread32(addr); 445 reg &= ~GPIO_BIT(offset); 446 447 copro = aspeed_gpio_copro_request(gpio, offset); 448 iowrite32(reg, addr); 449 if (copro) 450 aspeed_gpio_copro_release(gpio, offset); 451 452 raw_spin_unlock_irqrestore(&gpio->lock, flags); 453 454 return 0; 455 } 456 457 static int aspeed_gpio_dir_out(struct gpio_chip *gc, 458 unsigned int offset, int val) 459 { 460 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 461 const struct aspeed_gpio_bank *bank = to_bank(offset); 462 void __iomem *addr = bank_reg(gpio, bank, reg_dir); 463 unsigned long flags; 464 bool copro; 465 u32 reg; 466 467 if (!have_output(gpio, offset)) 468 return -ENOTSUPP; 469 470 raw_spin_lock_irqsave(&gpio->lock, flags); 471 472 reg = ioread32(addr); 473 reg |= GPIO_BIT(offset); 474 475 copro = aspeed_gpio_copro_request(gpio, offset); 476 __aspeed_gpio_set(gc, offset, val); 477 iowrite32(reg, addr); 478 479 if (copro) 480 aspeed_gpio_copro_release(gpio, offset); 481 raw_spin_unlock_irqrestore(&gpio->lock, flags); 482 483 return 0; 484 } 485 486 static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 487 { 488 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 489 const struct aspeed_gpio_bank *bank = to_bank(offset); 490 unsigned long flags; 491 u32 val; 492 493 if (!have_input(gpio, offset)) 494 return GPIO_LINE_DIRECTION_OUT; 495 496 if (!have_output(gpio, offset)) 497 return GPIO_LINE_DIRECTION_IN; 498 499 raw_spin_lock_irqsave(&gpio->lock, flags); 500 501 val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset); 502 503 raw_spin_unlock_irqrestore(&gpio->lock, flags); 504 505 return val ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 506 } 507 508 static inline int irqd_to_aspeed_gpio_data(struct irq_data *d, 509 struct aspeed_gpio **gpio, 510 const struct aspeed_gpio_bank **bank, 511 u32 *bit, int *offset) 512 { 513 struct aspeed_gpio *internal; 514 515 *offset = irqd_to_hwirq(d); 516 517 internal = irq_data_get_irq_chip_data(d); 518 519 /* This might be a bit of a questionable place to check */ 520 if (!have_irq(internal, *offset)) 521 return -ENOTSUPP; 522 523 *gpio = internal; 524 *bank = to_bank(*offset); 525 *bit = GPIO_BIT(*offset); 526 527 return 0; 528 } 529 530 static void aspeed_gpio_irq_ack(struct irq_data *d) 531 { 532 const struct aspeed_gpio_bank *bank; 533 struct aspeed_gpio *gpio; 534 unsigned long flags; 535 void __iomem *status_addr; 536 int rc, offset; 537 bool copro; 538 u32 bit; 539 540 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); 541 if (rc) 542 return; 543 544 status_addr = bank_reg(gpio, bank, reg_irq_status); 545 546 raw_spin_lock_irqsave(&gpio->lock, flags); 547 copro = aspeed_gpio_copro_request(gpio, offset); 548 549 iowrite32(bit, status_addr); 550 551 if (copro) 552 aspeed_gpio_copro_release(gpio, offset); 553 raw_spin_unlock_irqrestore(&gpio->lock, flags); 554 } 555 556 static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set) 557 { 558 const struct aspeed_gpio_bank *bank; 559 struct aspeed_gpio *gpio; 560 unsigned long flags; 561 u32 reg, bit; 562 void __iomem *addr; 563 int rc, offset; 564 bool copro; 565 566 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); 567 if (rc) 568 return; 569 570 addr = bank_reg(gpio, bank, reg_irq_enable); 571 572 /* Unmasking the IRQ */ 573 if (set) 574 gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d)); 575 576 raw_spin_lock_irqsave(&gpio->lock, flags); 577 copro = aspeed_gpio_copro_request(gpio, offset); 578 579 reg = ioread32(addr); 580 if (set) 581 reg |= bit; 582 else 583 reg &= ~bit; 584 iowrite32(reg, addr); 585 586 if (copro) 587 aspeed_gpio_copro_release(gpio, offset); 588 raw_spin_unlock_irqrestore(&gpio->lock, flags); 589 590 /* Masking the IRQ */ 591 if (!set) 592 gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(d)); 593 } 594 595 static void aspeed_gpio_irq_mask(struct irq_data *d) 596 { 597 aspeed_gpio_irq_set_mask(d, false); 598 } 599 600 static void aspeed_gpio_irq_unmask(struct irq_data *d) 601 { 602 aspeed_gpio_irq_set_mask(d, true); 603 } 604 605 static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type) 606 { 607 u32 type0 = 0; 608 u32 type1 = 0; 609 u32 type2 = 0; 610 u32 bit, reg; 611 const struct aspeed_gpio_bank *bank; 612 irq_flow_handler_t handler; 613 struct aspeed_gpio *gpio; 614 unsigned long flags; 615 void __iomem *addr; 616 int rc, offset; 617 bool copro; 618 619 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); 620 if (rc) 621 return -EINVAL; 622 623 switch (type & IRQ_TYPE_SENSE_MASK) { 624 case IRQ_TYPE_EDGE_BOTH: 625 type2 |= bit; 626 fallthrough; 627 case IRQ_TYPE_EDGE_RISING: 628 type0 |= bit; 629 fallthrough; 630 case IRQ_TYPE_EDGE_FALLING: 631 handler = handle_edge_irq; 632 break; 633 case IRQ_TYPE_LEVEL_HIGH: 634 type0 |= bit; 635 fallthrough; 636 case IRQ_TYPE_LEVEL_LOW: 637 type1 |= bit; 638 handler = handle_level_irq; 639 break; 640 default: 641 return -EINVAL; 642 } 643 644 raw_spin_lock_irqsave(&gpio->lock, flags); 645 copro = aspeed_gpio_copro_request(gpio, offset); 646 647 addr = bank_reg(gpio, bank, reg_irq_type0); 648 reg = ioread32(addr); 649 reg = (reg & ~bit) | type0; 650 iowrite32(reg, addr); 651 652 addr = bank_reg(gpio, bank, reg_irq_type1); 653 reg = ioread32(addr); 654 reg = (reg & ~bit) | type1; 655 iowrite32(reg, addr); 656 657 addr = bank_reg(gpio, bank, reg_irq_type2); 658 reg = ioread32(addr); 659 reg = (reg & ~bit) | type2; 660 iowrite32(reg, addr); 661 662 if (copro) 663 aspeed_gpio_copro_release(gpio, offset); 664 raw_spin_unlock_irqrestore(&gpio->lock, flags); 665 666 irq_set_handler_locked(d, handler); 667 668 return 0; 669 } 670 671 static void aspeed_gpio_irq_handler(struct irq_desc *desc) 672 { 673 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 674 struct irq_chip *ic = irq_desc_get_chip(desc); 675 struct aspeed_gpio *data = gpiochip_get_data(gc); 676 unsigned int i, p, banks; 677 unsigned long reg; 678 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 679 680 chained_irq_enter(ic, desc); 681 682 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); 683 for (i = 0; i < banks; i++) { 684 const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i]; 685 686 reg = ioread32(bank_reg(data, bank, reg_irq_status)); 687 688 for_each_set_bit(p, ®, 32) 689 generic_handle_domain_irq(gc->irq.domain, i * 32 + p); 690 } 691 692 chained_irq_exit(ic, desc); 693 } 694 695 static void aspeed_init_irq_valid_mask(struct gpio_chip *gc, 696 unsigned long *valid_mask, 697 unsigned int ngpios) 698 { 699 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 700 const struct aspeed_bank_props *props = gpio->config->props; 701 702 while (!is_bank_props_sentinel(props)) { 703 unsigned int offset; 704 const unsigned long int input = props->input; 705 706 /* Pretty crummy approach, but similar to GPIO core */ 707 for_each_clear_bit(offset, &input, 32) { 708 unsigned int i = props->bank * 32 + offset; 709 710 if (i >= gpio->chip.ngpio) 711 break; 712 713 clear_bit(i, valid_mask); 714 } 715 716 props++; 717 } 718 } 719 720 static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip, 721 unsigned int offset, bool enable) 722 { 723 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 724 unsigned long flags; 725 void __iomem *treg; 726 bool copro; 727 u32 val; 728 729 treg = bank_reg(gpio, to_bank(offset), reg_tolerance); 730 731 raw_spin_lock_irqsave(&gpio->lock, flags); 732 copro = aspeed_gpio_copro_request(gpio, offset); 733 734 val = readl(treg); 735 736 if (enable) 737 val |= GPIO_BIT(offset); 738 else 739 val &= ~GPIO_BIT(offset); 740 741 writel(val, treg); 742 743 if (copro) 744 aspeed_gpio_copro_release(gpio, offset); 745 raw_spin_unlock_irqrestore(&gpio->lock, flags); 746 747 return 0; 748 } 749 750 static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset) 751 { 752 if (!have_gpio(gpiochip_get_data(chip), offset)) 753 return -ENODEV; 754 755 return pinctrl_gpio_request(chip, offset); 756 } 757 758 static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset) 759 { 760 pinctrl_gpio_free(chip, offset); 761 } 762 763 static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs, 764 u32 *cycles) 765 { 766 u64 rate; 767 u64 n; 768 u32 r; 769 770 rate = clk_get_rate(gpio->clk); 771 if (!rate) 772 return -ENOTSUPP; 773 774 n = rate * usecs; 775 r = do_div(n, 1000000); 776 777 if (n >= U32_MAX) 778 return -ERANGE; 779 780 /* At least as long as the requested time */ 781 *cycles = n + (!!r); 782 783 return 0; 784 } 785 786 /* Call under gpio->lock */ 787 static int register_allocated_timer(struct aspeed_gpio *gpio, 788 unsigned int offset, unsigned int timer) 789 { 790 if (WARN(gpio->offset_timer[offset] != 0, 791 "Offset %d already allocated timer %d\n", 792 offset, gpio->offset_timer[offset])) 793 return -EINVAL; 794 795 if (WARN(gpio->timer_users[timer] == UINT_MAX, 796 "Timer user count would overflow\n")) 797 return -EPERM; 798 799 gpio->offset_timer[offset] = timer; 800 gpio->timer_users[timer]++; 801 802 return 0; 803 } 804 805 /* Call under gpio->lock */ 806 static int unregister_allocated_timer(struct aspeed_gpio *gpio, 807 unsigned int offset) 808 { 809 if (WARN(gpio->offset_timer[offset] == 0, 810 "No timer allocated to offset %d\n", offset)) 811 return -EINVAL; 812 813 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0, 814 "No users recorded for timer %d\n", 815 gpio->offset_timer[offset])) 816 return -EINVAL; 817 818 gpio->timer_users[gpio->offset_timer[offset]]--; 819 gpio->offset_timer[offset] = 0; 820 821 return 0; 822 } 823 824 /* Call under gpio->lock */ 825 static inline bool timer_allocation_registered(struct aspeed_gpio *gpio, 826 unsigned int offset) 827 { 828 return gpio->offset_timer[offset] > 0; 829 } 830 831 /* Call under gpio->lock */ 832 static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset, 833 unsigned int timer) 834 { 835 const struct aspeed_gpio_bank *bank = to_bank(offset); 836 const u32 mask = GPIO_BIT(offset); 837 void __iomem *addr; 838 u32 val; 839 840 /* Note: Debounce timer isn't under control of the command 841 * source registers, so no need to sync with the coprocessor 842 */ 843 addr = bank_reg(gpio, bank, reg_debounce_sel1); 844 val = ioread32(addr); 845 iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr); 846 847 addr = bank_reg(gpio, bank, reg_debounce_sel2); 848 val = ioread32(addr); 849 iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr); 850 } 851 852 static int enable_debounce(struct gpio_chip *chip, unsigned int offset, 853 unsigned long usecs) 854 { 855 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 856 u32 requested_cycles; 857 unsigned long flags; 858 int rc; 859 int i; 860 861 if (!gpio->clk) 862 return -EINVAL; 863 864 rc = usecs_to_cycles(gpio, usecs, &requested_cycles); 865 if (rc < 0) { 866 dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n", 867 usecs, clk_get_rate(gpio->clk), rc); 868 return rc; 869 } 870 871 raw_spin_lock_irqsave(&gpio->lock, flags); 872 873 if (timer_allocation_registered(gpio, offset)) { 874 rc = unregister_allocated_timer(gpio, offset); 875 if (rc < 0) 876 goto out; 877 } 878 879 /* Try to find a timer already configured for the debounce period */ 880 for (i = 1; i < ARRAY_SIZE(debounce_timers); i++) { 881 u32 cycles; 882 883 cycles = ioread32(gpio->base + debounce_timers[i]); 884 if (requested_cycles == cycles) 885 break; 886 } 887 888 if (i == ARRAY_SIZE(debounce_timers)) { 889 int j; 890 891 /* 892 * As there are no timers configured for the requested debounce 893 * period, find an unused timer instead 894 */ 895 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) { 896 if (gpio->timer_users[j] == 0) 897 break; 898 } 899 900 if (j == ARRAY_SIZE(gpio->timer_users)) { 901 dev_warn(chip->parent, 902 "Debounce timers exhausted, cannot debounce for period %luus\n", 903 usecs); 904 905 rc = -EPERM; 906 907 /* 908 * We already adjusted the accounting to remove @offset 909 * as a user of its previous timer, so also configure 910 * the hardware so @offset has timers disabled for 911 * consistency. 912 */ 913 configure_timer(gpio, offset, 0); 914 goto out; 915 } 916 917 i = j; 918 919 iowrite32(requested_cycles, gpio->base + debounce_timers[i]); 920 } 921 922 if (WARN(i == 0, "Cannot register index of disabled timer\n")) { 923 rc = -EINVAL; 924 goto out; 925 } 926 927 register_allocated_timer(gpio, offset, i); 928 configure_timer(gpio, offset, i); 929 930 out: 931 raw_spin_unlock_irqrestore(&gpio->lock, flags); 932 933 return rc; 934 } 935 936 static int disable_debounce(struct gpio_chip *chip, unsigned int offset) 937 { 938 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 939 unsigned long flags; 940 int rc; 941 942 raw_spin_lock_irqsave(&gpio->lock, flags); 943 944 rc = unregister_allocated_timer(gpio, offset); 945 if (!rc) 946 configure_timer(gpio, offset, 0); 947 948 raw_spin_unlock_irqrestore(&gpio->lock, flags); 949 950 return rc; 951 } 952 953 static int set_debounce(struct gpio_chip *chip, unsigned int offset, 954 unsigned long usecs) 955 { 956 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 957 958 if (!have_debounce(gpio, offset)) 959 return -ENOTSUPP; 960 961 if (usecs) 962 return enable_debounce(chip, offset, usecs); 963 964 return disable_debounce(chip, offset); 965 } 966 967 static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 968 unsigned long config) 969 { 970 unsigned long param = pinconf_to_config_param(config); 971 u32 arg = pinconf_to_config_argument(config); 972 973 if (param == PIN_CONFIG_INPUT_DEBOUNCE) 974 return set_debounce(chip, offset, arg); 975 else if (param == PIN_CONFIG_BIAS_DISABLE || 976 param == PIN_CONFIG_BIAS_PULL_DOWN || 977 param == PIN_CONFIG_DRIVE_STRENGTH) 978 return pinctrl_gpio_set_config(chip, offset, config); 979 else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN || 980 param == PIN_CONFIG_DRIVE_OPEN_SOURCE) 981 /* Return -ENOTSUPP to trigger emulation, as per datasheet */ 982 return -ENOTSUPP; 983 else if (param == PIN_CONFIG_PERSIST_STATE) 984 return aspeed_gpio_reset_tolerance(chip, offset, arg); 985 986 return -ENOTSUPP; 987 } 988 989 /** 990 * aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with 991 * the coprocessor for shared GPIO banks 992 * @ops: The callbacks 993 * @data: Pointer passed back to the callbacks 994 */ 995 int aspeed_gpio_copro_set_ops(const struct aspeed_gpio_copro_ops *ops, void *data) 996 { 997 copro_data = data; 998 copro_ops = ops; 999 1000 return 0; 1001 } 1002 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_set_ops); 1003 1004 /** 1005 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire 1006 * bank gets marked and any access from the ARM will 1007 * result in handshaking via callbacks. 1008 * @desc: The GPIO to be marked 1009 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space 1010 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space 1011 * @bit: If non-NULL, returns the bit number of the GPIO in the registers 1012 */ 1013 int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc, 1014 u16 *vreg_offset, u16 *dreg_offset, u8 *bit) 1015 { 1016 struct gpio_chip *chip = gpiod_to_chip(desc); 1017 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 1018 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc); 1019 const struct aspeed_gpio_bank *bank = to_bank(offset); 1020 unsigned long flags; 1021 1022 if (!gpio->cf_copro_bankmap) 1023 gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL); 1024 if (!gpio->cf_copro_bankmap) 1025 return -ENOMEM; 1026 if (offset < 0 || offset > gpio->chip.ngpio) 1027 return -EINVAL; 1028 bindex = offset >> 3; 1029 1030 raw_spin_lock_irqsave(&gpio->lock, flags); 1031 1032 /* Sanity check, this shouldn't happen */ 1033 if (gpio->cf_copro_bankmap[bindex] == 0xff) { 1034 rc = -EIO; 1035 goto bail; 1036 } 1037 gpio->cf_copro_bankmap[bindex]++; 1038 1039 /* Switch command source */ 1040 if (gpio->cf_copro_bankmap[bindex] == 1) 1041 aspeed_gpio_change_cmd_source(gpio, bank, bindex, 1042 GPIO_CMDSRC_COLDFIRE); 1043 1044 if (vreg_offset) 1045 *vreg_offset = bank->val_regs; 1046 if (dreg_offset) 1047 *dreg_offset = bank->rdata_reg; 1048 if (bit) 1049 *bit = GPIO_OFFSET(offset); 1050 bail: 1051 raw_spin_unlock_irqrestore(&gpio->lock, flags); 1052 return rc; 1053 } 1054 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio); 1055 1056 /** 1057 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor. 1058 * @desc: The GPIO to be marked 1059 */ 1060 int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc) 1061 { 1062 struct gpio_chip *chip = gpiod_to_chip(desc); 1063 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 1064 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc); 1065 const struct aspeed_gpio_bank *bank = to_bank(offset); 1066 unsigned long flags; 1067 1068 if (!gpio->cf_copro_bankmap) 1069 return -ENXIO; 1070 1071 if (offset < 0 || offset > gpio->chip.ngpio) 1072 return -EINVAL; 1073 bindex = offset >> 3; 1074 1075 raw_spin_lock_irqsave(&gpio->lock, flags); 1076 1077 /* Sanity check, this shouldn't happen */ 1078 if (gpio->cf_copro_bankmap[bindex] == 0) { 1079 rc = -EIO; 1080 goto bail; 1081 } 1082 gpio->cf_copro_bankmap[bindex]--; 1083 1084 /* Switch command source */ 1085 if (gpio->cf_copro_bankmap[bindex] == 0) 1086 aspeed_gpio_change_cmd_source(gpio, bank, bindex, 1087 GPIO_CMDSRC_ARM); 1088 bail: 1089 raw_spin_unlock_irqrestore(&gpio->lock, flags); 1090 return rc; 1091 } 1092 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio); 1093 1094 static void aspeed_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p) 1095 { 1096 const struct aspeed_gpio_bank *bank; 1097 struct aspeed_gpio *gpio; 1098 u32 bit; 1099 int rc, offset; 1100 1101 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); 1102 if (rc) 1103 return; 1104 1105 seq_puts(p, dev_name(gpio->dev)); 1106 } 1107 1108 static const struct irq_chip aspeed_gpio_irq_chip = { 1109 .irq_ack = aspeed_gpio_irq_ack, 1110 .irq_mask = aspeed_gpio_irq_mask, 1111 .irq_unmask = aspeed_gpio_irq_unmask, 1112 .irq_set_type = aspeed_gpio_set_type, 1113 .irq_print_chip = aspeed_gpio_irq_print_chip, 1114 .flags = IRQCHIP_IMMUTABLE, 1115 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1116 }; 1117 1118 /* 1119 * Any banks not specified in a struct aspeed_bank_props array are assumed to 1120 * have the properties: 1121 * 1122 * { .input = 0xffffffff, .output = 0xffffffff } 1123 */ 1124 1125 static const struct aspeed_bank_props ast2400_bank_props[] = { 1126 /* input output */ 1127 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ 1128 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */ 1129 { }, 1130 }; 1131 1132 static const struct aspeed_gpio_config ast2400_config = 1133 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */ 1134 { .nr_gpios = 220, .props = ast2400_bank_props, }; 1135 1136 static const struct aspeed_bank_props ast2500_bank_props[] = { 1137 /* input output */ 1138 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ 1139 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */ 1140 { 7, 0x000000ff, 0x000000ff }, /* AC */ 1141 { }, 1142 }; 1143 1144 static const struct aspeed_gpio_config ast2500_config = 1145 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */ 1146 { .nr_gpios = 232, .props = ast2500_bank_props, }; 1147 1148 static const struct aspeed_bank_props ast2600_bank_props[] = { 1149 /* input output */ 1150 {4, 0xffffffff, 0x00ffffff}, /* Q/R/S/T */ 1151 {5, 0xffffffff, 0xffffff00}, /* U/V/W/X */ 1152 {6, 0x0000ffff, 0x0000ffff}, /* Y/Z */ 1153 { }, 1154 }; 1155 1156 static const struct aspeed_gpio_config ast2600_config = 1157 /* 1158 * ast2600 has two controllers one with 208 GPIOs and one with 36 GPIOs. 1159 * We expect ngpio being set in the device tree and this is a fallback 1160 * option. 1161 */ 1162 { .nr_gpios = 208, .props = ast2600_bank_props, }; 1163 1164 static const struct of_device_id aspeed_gpio_of_table[] = { 1165 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, }, 1166 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, }, 1167 { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, }, 1168 {} 1169 }; 1170 MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table); 1171 1172 static int __init aspeed_gpio_probe(struct platform_device *pdev) 1173 { 1174 const struct of_device_id *gpio_id; 1175 struct gpio_irq_chip *girq; 1176 struct aspeed_gpio *gpio; 1177 int rc, irq, i, banks, err; 1178 u32 ngpio; 1179 1180 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 1181 if (!gpio) 1182 return -ENOMEM; 1183 1184 gpio->base = devm_platform_ioremap_resource(pdev, 0); 1185 if (IS_ERR(gpio->base)) 1186 return PTR_ERR(gpio->base); 1187 1188 gpio->dev = &pdev->dev; 1189 1190 raw_spin_lock_init(&gpio->lock); 1191 1192 gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); 1193 if (!gpio_id) 1194 return -EINVAL; 1195 1196 gpio->clk = devm_clk_get_enabled(&pdev->dev, NULL); 1197 if (IS_ERR(gpio->clk)) { 1198 dev_warn(&pdev->dev, 1199 "Failed to get clock from devicetree, debouncing disabled\n"); 1200 gpio->clk = NULL; 1201 } 1202 1203 gpio->config = gpio_id->data; 1204 1205 gpio->chip.parent = &pdev->dev; 1206 err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio); 1207 gpio->chip.ngpio = (u16) ngpio; 1208 if (err) 1209 gpio->chip.ngpio = gpio->config->nr_gpios; 1210 gpio->chip.direction_input = aspeed_gpio_dir_in; 1211 gpio->chip.direction_output = aspeed_gpio_dir_out; 1212 gpio->chip.get_direction = aspeed_gpio_get_direction; 1213 gpio->chip.request = aspeed_gpio_request; 1214 gpio->chip.free = aspeed_gpio_free; 1215 gpio->chip.get = aspeed_gpio_get; 1216 gpio->chip.set = aspeed_gpio_set; 1217 gpio->chip.set_config = aspeed_gpio_set_config; 1218 gpio->chip.label = dev_name(&pdev->dev); 1219 gpio->chip.base = -1; 1220 1221 /* Allocate a cache of the output registers */ 1222 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); 1223 gpio->dcache = devm_kcalloc(&pdev->dev, 1224 banks, sizeof(u32), GFP_KERNEL); 1225 if (!gpio->dcache) 1226 return -ENOMEM; 1227 1228 /* 1229 * Populate it with initial values read from the HW and switch 1230 * all command sources to the ARM by default 1231 */ 1232 for (i = 0; i < banks; i++) { 1233 const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i]; 1234 void __iomem *addr = bank_reg(gpio, bank, reg_rdata); 1235 gpio->dcache[i] = ioread32(addr); 1236 aspeed_gpio_change_cmd_source(gpio, bank, 0, GPIO_CMDSRC_ARM); 1237 aspeed_gpio_change_cmd_source(gpio, bank, 1, GPIO_CMDSRC_ARM); 1238 aspeed_gpio_change_cmd_source(gpio, bank, 2, GPIO_CMDSRC_ARM); 1239 aspeed_gpio_change_cmd_source(gpio, bank, 3, GPIO_CMDSRC_ARM); 1240 } 1241 1242 /* Set up an irqchip */ 1243 irq = platform_get_irq(pdev, 0); 1244 if (irq < 0) 1245 return irq; 1246 gpio->irq = irq; 1247 girq = &gpio->chip.irq; 1248 gpio_irq_chip_set_chip(girq, &aspeed_gpio_irq_chip); 1249 1250 girq->parent_handler = aspeed_gpio_irq_handler; 1251 girq->num_parents = 1; 1252 girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), GFP_KERNEL); 1253 if (!girq->parents) 1254 return -ENOMEM; 1255 girq->parents[0] = gpio->irq; 1256 girq->default_type = IRQ_TYPE_NONE; 1257 girq->handler = handle_bad_irq; 1258 girq->init_valid_mask = aspeed_init_irq_valid_mask; 1259 1260 gpio->offset_timer = 1261 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL); 1262 if (!gpio->offset_timer) 1263 return -ENOMEM; 1264 1265 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); 1266 if (rc < 0) 1267 return rc; 1268 1269 return 0; 1270 } 1271 1272 static struct platform_driver aspeed_gpio_driver = { 1273 .driver = { 1274 .name = KBUILD_MODNAME, 1275 .of_match_table = aspeed_gpio_of_table, 1276 }, 1277 }; 1278 1279 module_platform_driver_probe(aspeed_gpio_driver, aspeed_gpio_probe); 1280 1281 MODULE_DESCRIPTION("Aspeed GPIO Driver"); 1282 MODULE_LICENSE("GPL"); 1283