1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2015 IBM Corp. 4 * 5 * Joel Stanley <joel@jms.id.au> 6 */ 7 8 #include <linux/cleanup.h> 9 #include <linux/clk.h> 10 #include <linux/gpio/aspeed.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/hashtable.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/platform_device.h> 19 #include <linux/seq_file.h> 20 #include <linux/spinlock.h> 21 #include <linux/string.h> 22 23 #include <asm/div64.h> 24 25 /* 26 * These two headers aren't meant to be used by GPIO drivers. We need 27 * them in order to access gpio_chip_hwgpio() which we need to implement 28 * the aspeed specific API which allows the coprocessor to request 29 * access to some GPIOs and to arbitrate between coprocessor and ARM. 30 */ 31 #include <linux/gpio/consumer.h> 32 #include "gpiolib.h" 33 34 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ 35 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) 36 #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) 37 38 #define GPIO_G7_IRQ_STS_BASE 0x100 39 #define GPIO_G7_IRQ_STS_OFFSET(x) (GPIO_G7_IRQ_STS_BASE + (x) * 0x4) 40 #define GPIO_G7_CTRL_REG_BASE 0x180 41 #define GPIO_G7_CTRL_REG_OFFSET(x) (GPIO_G7_CTRL_REG_BASE + (x) * 0x4) 42 #define GPIO_G7_CTRL_OUT_DATA BIT(0) 43 #define GPIO_G7_CTRL_DIR BIT(1) 44 #define GPIO_G7_CTRL_IRQ_EN BIT(2) 45 #define GPIO_G7_CTRL_IRQ_TYPE0 BIT(3) 46 #define GPIO_G7_CTRL_IRQ_TYPE1 BIT(4) 47 #define GPIO_G7_CTRL_IRQ_TYPE2 BIT(5) 48 #define GPIO_G7_CTRL_RST_TOLERANCE BIT(6) 49 #define GPIO_G7_CTRL_DEBOUNCE_SEL1 BIT(7) 50 #define GPIO_G7_CTRL_DEBOUNCE_SEL2 BIT(8) 51 #define GPIO_G7_CTRL_INPUT_MASK BIT(9) 52 #define GPIO_G7_CTRL_IRQ_STS BIT(12) 53 #define GPIO_G7_CTRL_IN_DATA BIT(13) 54 55 struct aspeed_bank_props { 56 unsigned int bank; 57 u32 input; 58 u32 output; 59 }; 60 61 struct aspeed_gpio_config { 62 unsigned int nr_gpios; 63 const struct aspeed_bank_props *props; 64 const struct aspeed_gpio_llops *llops; 65 const int *debounce_timers_array; 66 int debounce_timers_num; 67 bool require_dcache; 68 }; 69 70 /* 71 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled 72 * @timer_users: Tracks the number of users for each timer 73 * 74 * The @timer_users has four elements but the first element is unused. This is 75 * to simplify accounting and indexing, as a zero value in @offset_timer 76 * represents disabled debouncing for the GPIO. Any other value for an element 77 * of @offset_timer is used as an index into @timer_users. This behaviour of 78 * the zero value aligns with the behaviour of zero built from the timer 79 * configuration registers (i.e. debouncing is disabled). 80 */ 81 struct aspeed_gpio { 82 struct gpio_chip chip; 83 struct device *dev; 84 raw_spinlock_t lock; 85 void __iomem *base; 86 int irq; 87 const struct aspeed_gpio_config *config; 88 89 u8 *offset_timer; 90 unsigned int timer_users[4]; 91 struct clk *clk; 92 93 u32 *dcache; 94 u8 *cf_copro_bankmap; 95 }; 96 97 struct aspeed_gpio_bank { 98 uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch 99 * +4: Rd/Wr: Direction (0=in, 1=out) 100 */ 101 uint16_t rdata_reg; /* Rd: read write latch, Wr: <none> */ 102 uint16_t irq_regs; 103 uint16_t debounce_regs; 104 uint16_t tolerance_regs; 105 uint16_t cmdsrc_regs; 106 }; 107 108 /* 109 * Note: The "value" register returns the input value sampled on the 110 * line even when the GPIO is configured as an output. Since 111 * that input goes through synchronizers, writing, then reading 112 * back may not return the written value right away. 113 * 114 * The "rdata" register returns the content of the write latch 115 * and thus can be used to read back what was last written 116 * reliably. 117 */ 118 119 static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 }; 120 static const int g7_debounce_timers[4] = { 0x00, 0x00, 0x04, 0x08 }; 121 122 /* 123 * The debounce timers array is used to configure the debounce timer settings.Here’s how it works: 124 * Array Value: Indicates the offset for configuring the debounce timer. 125 * Array Index: Corresponds to the debounce setting register. 126 * The debounce timers array follows this pattern for configuring the debounce setting registers: 127 * Array Index 0: No debounce timer is set; 128 * Array Value is irrelevant (don’t care). 129 * Array Index 1: Debounce setting #2 is set to 1, and debounce setting #1 is set to 0. 130 * Array Value: offset for configuring debounce timer 0 (g4: 0x50, g7: 0x00) 131 * Array Index 2: Debounce setting #2 is set to 0, and debounce setting #1 is set to 1. 132 * Array Value: offset for configuring debounce timer 1 (g4: 0x54, g7: 0x04) 133 * Array Index 3: Debounce setting #2 is set to 1, and debounce setting #1 is set to 1. 134 * Array Value: offset for configuring debounce timer 2 (g4: 0x58, g7: 0x8) 135 */ 136 137 static const struct aspeed_gpio_copro_ops *copro_ops; 138 static void *copro_data; 139 140 static const struct aspeed_gpio_bank aspeed_gpio_banks[] = { 141 { 142 .val_regs = 0x0000, 143 .rdata_reg = 0x00c0, 144 .irq_regs = 0x0008, 145 .debounce_regs = 0x0040, 146 .tolerance_regs = 0x001c, 147 .cmdsrc_regs = 0x0060, 148 }, 149 { 150 .val_regs = 0x0020, 151 .rdata_reg = 0x00c4, 152 .irq_regs = 0x0028, 153 .debounce_regs = 0x0048, 154 .tolerance_regs = 0x003c, 155 .cmdsrc_regs = 0x0068, 156 }, 157 { 158 .val_regs = 0x0070, 159 .rdata_reg = 0x00c8, 160 .irq_regs = 0x0098, 161 .debounce_regs = 0x00b0, 162 .tolerance_regs = 0x00ac, 163 .cmdsrc_regs = 0x0090, 164 }, 165 { 166 .val_regs = 0x0078, 167 .rdata_reg = 0x00cc, 168 .irq_regs = 0x00e8, 169 .debounce_regs = 0x0100, 170 .tolerance_regs = 0x00fc, 171 .cmdsrc_regs = 0x00e0, 172 }, 173 { 174 .val_regs = 0x0080, 175 .rdata_reg = 0x00d0, 176 .irq_regs = 0x0118, 177 .debounce_regs = 0x0130, 178 .tolerance_regs = 0x012c, 179 .cmdsrc_regs = 0x0110, 180 }, 181 { 182 .val_regs = 0x0088, 183 .rdata_reg = 0x00d4, 184 .irq_regs = 0x0148, 185 .debounce_regs = 0x0160, 186 .tolerance_regs = 0x015c, 187 .cmdsrc_regs = 0x0140, 188 }, 189 { 190 .val_regs = 0x01E0, 191 .rdata_reg = 0x00d8, 192 .irq_regs = 0x0178, 193 .debounce_regs = 0x0190, 194 .tolerance_regs = 0x018c, 195 .cmdsrc_regs = 0x0170, 196 }, 197 { 198 .val_regs = 0x01e8, 199 .rdata_reg = 0x00dc, 200 .irq_regs = 0x01a8, 201 .debounce_regs = 0x01c0, 202 .tolerance_regs = 0x01bc, 203 .cmdsrc_regs = 0x01a0, 204 }, 205 }; 206 207 enum aspeed_gpio_reg { 208 reg_val, 209 reg_rdata, 210 reg_dir, 211 reg_irq_enable, 212 reg_irq_type0, 213 reg_irq_type1, 214 reg_irq_type2, 215 reg_irq_status, 216 reg_debounce_sel1, 217 reg_debounce_sel2, 218 reg_tolerance, 219 reg_cmdsrc0, 220 reg_cmdsrc1, 221 }; 222 223 struct aspeed_gpio_llops { 224 void (*reg_bit_set)(struct aspeed_gpio *gpio, unsigned int offset, 225 const enum aspeed_gpio_reg reg, bool val); 226 bool (*reg_bit_get)(struct aspeed_gpio *gpio, unsigned int offset, 227 const enum aspeed_gpio_reg reg); 228 int (*reg_bank_get)(struct aspeed_gpio *gpio, unsigned int offset, 229 const enum aspeed_gpio_reg reg); 230 void (*privilege_ctrl)(struct aspeed_gpio *gpio, unsigned int offset, int owner); 231 void (*privilege_init)(struct aspeed_gpio *gpio); 232 bool (*copro_request)(struct aspeed_gpio *gpio, unsigned int offset); 233 void (*copro_release)(struct aspeed_gpio *gpio, unsigned int offset); 234 }; 235 236 #define GPIO_VAL_VALUE 0x00 237 #define GPIO_VAL_DIR 0x04 238 239 #define GPIO_IRQ_ENABLE 0x00 240 #define GPIO_IRQ_TYPE0 0x04 241 #define GPIO_IRQ_TYPE1 0x08 242 #define GPIO_IRQ_TYPE2 0x0c 243 #define GPIO_IRQ_STATUS 0x10 244 245 #define GPIO_DEBOUNCE_SEL1 0x00 246 #define GPIO_DEBOUNCE_SEL2 0x04 247 248 #define GPIO_CMDSRC_0 0x00 249 #define GPIO_CMDSRC_1 0x04 250 #define GPIO_CMDSRC_ARM 0 251 #define GPIO_CMDSRC_LPC 1 252 #define GPIO_CMDSRC_COLDFIRE 2 253 #define GPIO_CMDSRC_RESERVED 3 254 255 /* This will be resolved at compile time */ 256 static void __iomem *aspeed_gpio_g4_bank_reg(struct aspeed_gpio *gpio, 257 const struct aspeed_gpio_bank *bank, 258 const enum aspeed_gpio_reg reg) 259 { 260 switch (reg) { 261 case reg_val: 262 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; 263 case reg_rdata: 264 return gpio->base + bank->rdata_reg; 265 case reg_dir: 266 return gpio->base + bank->val_regs + GPIO_VAL_DIR; 267 case reg_irq_enable: 268 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; 269 case reg_irq_type0: 270 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; 271 case reg_irq_type1: 272 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; 273 case reg_irq_type2: 274 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; 275 case reg_irq_status: 276 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; 277 case reg_debounce_sel1: 278 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1; 279 case reg_debounce_sel2: 280 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2; 281 case reg_tolerance: 282 return gpio->base + bank->tolerance_regs; 283 case reg_cmdsrc0: 284 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0; 285 case reg_cmdsrc1: 286 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1; 287 } 288 BUG(); 289 } 290 291 static u32 aspeed_gpio_g7_reg_mask(const enum aspeed_gpio_reg reg) 292 { 293 switch (reg) { 294 case reg_val: 295 return GPIO_G7_CTRL_OUT_DATA; 296 case reg_dir: 297 return GPIO_G7_CTRL_DIR; 298 case reg_irq_enable: 299 return GPIO_G7_CTRL_IRQ_EN; 300 case reg_irq_type0: 301 return GPIO_G7_CTRL_IRQ_TYPE0; 302 case reg_irq_type1: 303 return GPIO_G7_CTRL_IRQ_TYPE1; 304 case reg_irq_type2: 305 return GPIO_G7_CTRL_IRQ_TYPE2; 306 case reg_tolerance: 307 return GPIO_G7_CTRL_RST_TOLERANCE; 308 case reg_debounce_sel1: 309 return GPIO_G7_CTRL_DEBOUNCE_SEL1; 310 case reg_debounce_sel2: 311 return GPIO_G7_CTRL_DEBOUNCE_SEL2; 312 case reg_rdata: 313 return GPIO_G7_CTRL_OUT_DATA; 314 case reg_irq_status: 315 return GPIO_G7_CTRL_IRQ_STS; 316 case reg_cmdsrc0: 317 case reg_cmdsrc1: 318 default: 319 WARN_ON_ONCE(1); 320 return 0; 321 } 322 } 323 324 #define GPIO_BANK(x) ((x) >> 5) 325 #define GPIO_OFFSET(x) ((x) & 0x1f) 326 #define GPIO_BIT(x) BIT(GPIO_OFFSET(x)) 327 328 static const struct aspeed_gpio_bank *to_bank(unsigned int offset) 329 { 330 unsigned int bank = GPIO_BANK(offset); 331 332 WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks)); 333 return &aspeed_gpio_banks[bank]; 334 } 335 336 static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props) 337 { 338 return !(props->input || props->output); 339 } 340 341 static inline const struct aspeed_bank_props *find_bank_props( 342 struct aspeed_gpio *gpio, unsigned int offset) 343 { 344 const struct aspeed_bank_props *props = gpio->config->props; 345 346 while (!is_bank_props_sentinel(props)) { 347 if (props->bank == GPIO_BANK(offset)) 348 return props; 349 props++; 350 } 351 352 return NULL; 353 } 354 355 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset) 356 { 357 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 358 359 if (offset >= gpio->chip.ngpio) 360 return false; 361 362 return (!props || ((props->input | props->output) & GPIO_BIT(offset))); 363 } 364 365 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset) 366 { 367 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 368 369 return !props || (props->input & GPIO_BIT(offset)); 370 } 371 372 #define have_irq(g, o) have_input((g), (o)) 373 #define have_debounce(g, o) have_input((g), (o)) 374 375 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset) 376 { 377 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 378 379 return !props || (props->output & GPIO_BIT(offset)); 380 } 381 382 static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio, unsigned int offset, int cmdsrc) 383 { 384 if (gpio->config->llops->privilege_ctrl) 385 gpio->config->llops->privilege_ctrl(gpio, offset, cmdsrc); 386 } 387 388 static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio, 389 unsigned int offset) 390 { 391 if (gpio->config->llops->copro_request) 392 return gpio->config->llops->copro_request(gpio, offset); 393 394 return false; 395 } 396 397 static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio, 398 unsigned int offset) 399 { 400 if (gpio->config->llops->copro_release) 401 gpio->config->llops->copro_release(gpio, offset); 402 } 403 404 static bool aspeed_gpio_support_copro(struct aspeed_gpio *gpio) 405 { 406 return gpio->config->llops->copro_request && gpio->config->llops->copro_release && 407 gpio->config->llops->privilege_ctrl && gpio->config->llops->privilege_init; 408 } 409 410 static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset) 411 { 412 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 413 414 return gpio->config->llops->reg_bit_get(gpio, offset, reg_val); 415 } 416 417 static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, 418 int val) 419 { 420 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 421 422 gpio->config->llops->reg_bit_set(gpio, offset, reg_val, val); 423 /* Flush write */ 424 gpio->config->llops->reg_bit_get(gpio, offset, reg_val); 425 } 426 427 static int aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, int val) 428 { 429 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 430 bool copro = false; 431 432 guard(raw_spinlock_irqsave)(&gpio->lock); 433 434 copro = aspeed_gpio_copro_request(gpio, offset); 435 436 __aspeed_gpio_set(gc, offset, val); 437 438 if (copro) 439 aspeed_gpio_copro_release(gpio, offset); 440 441 return 0; 442 } 443 444 static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset) 445 { 446 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 447 bool copro = false; 448 449 if (!have_input(gpio, offset)) 450 return -ENOTSUPP; 451 452 guard(raw_spinlock_irqsave)(&gpio->lock); 453 454 copro = aspeed_gpio_copro_request(gpio, offset); 455 gpio->config->llops->reg_bit_set(gpio, offset, reg_dir, 0); 456 if (copro) 457 aspeed_gpio_copro_release(gpio, offset); 458 459 return 0; 460 } 461 462 static int aspeed_gpio_dir_out(struct gpio_chip *gc, 463 unsigned int offset, int val) 464 { 465 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 466 bool copro = false; 467 468 if (!have_output(gpio, offset)) 469 return -ENOTSUPP; 470 471 guard(raw_spinlock_irqsave)(&gpio->lock); 472 473 copro = aspeed_gpio_copro_request(gpio, offset); 474 __aspeed_gpio_set(gc, offset, val); 475 gpio->config->llops->reg_bit_set(gpio, offset, reg_dir, 1); 476 477 if (copro) 478 aspeed_gpio_copro_release(gpio, offset); 479 480 return 0; 481 } 482 483 static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 484 { 485 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 486 u32 val; 487 488 if (!have_input(gpio, offset)) 489 return GPIO_LINE_DIRECTION_OUT; 490 491 if (!have_output(gpio, offset)) 492 return GPIO_LINE_DIRECTION_IN; 493 494 guard(raw_spinlock_irqsave)(&gpio->lock); 495 496 val = gpio->config->llops->reg_bit_get(gpio, offset, reg_dir); 497 498 return val ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 499 } 500 501 static inline int irqd_to_aspeed_gpio_data(struct irq_data *d, 502 struct aspeed_gpio **gpio, 503 int *offset) 504 { 505 struct aspeed_gpio *internal; 506 507 *offset = irqd_to_hwirq(d); 508 509 internal = irq_data_get_irq_chip_data(d); 510 511 /* This might be a bit of a questionable place to check */ 512 if (!have_irq(internal, *offset)) 513 return -ENOTSUPP; 514 515 *gpio = internal; 516 517 return 0; 518 } 519 520 static void aspeed_gpio_irq_ack(struct irq_data *d) 521 { 522 struct aspeed_gpio *gpio; 523 int rc, offset; 524 bool copro = false; 525 526 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset); 527 if (rc) 528 return; 529 530 guard(raw_spinlock_irqsave)(&gpio->lock); 531 532 copro = aspeed_gpio_copro_request(gpio, offset); 533 534 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_status, 1); 535 536 if (copro) 537 aspeed_gpio_copro_release(gpio, offset); 538 } 539 540 static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set) 541 { 542 struct aspeed_gpio *gpio; 543 int rc, offset; 544 bool copro = false; 545 546 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset); 547 if (rc) 548 return; 549 550 /* Unmasking the IRQ */ 551 if (set) 552 gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d)); 553 554 guard(raw_spinlock_irqsave)(&gpio->lock); 555 556 copro = aspeed_gpio_copro_request(gpio, offset); 557 558 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_enable, set); 559 560 if (copro) 561 aspeed_gpio_copro_release(gpio, offset); 562 563 /* Masking the IRQ */ 564 if (!set) 565 gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(d)); 566 } 567 568 static void aspeed_gpio_irq_mask(struct irq_data *d) 569 { 570 aspeed_gpio_irq_set_mask(d, false); 571 } 572 573 static void aspeed_gpio_irq_unmask(struct irq_data *d) 574 { 575 aspeed_gpio_irq_set_mask(d, true); 576 } 577 578 static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type) 579 { 580 u32 type0 = 0; 581 u32 type1 = 0; 582 u32 type2 = 0; 583 irq_flow_handler_t handler; 584 struct aspeed_gpio *gpio; 585 int rc, offset; 586 bool copro = false; 587 588 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset); 589 if (rc) 590 return -EINVAL; 591 592 switch (type & IRQ_TYPE_SENSE_MASK) { 593 case IRQ_TYPE_EDGE_BOTH: 594 type2 = 1; 595 fallthrough; 596 case IRQ_TYPE_EDGE_RISING: 597 type0 = 1; 598 fallthrough; 599 case IRQ_TYPE_EDGE_FALLING: 600 handler = handle_edge_irq; 601 break; 602 case IRQ_TYPE_LEVEL_HIGH: 603 type0 = 1; 604 fallthrough; 605 case IRQ_TYPE_LEVEL_LOW: 606 type1 = 1; 607 handler = handle_level_irq; 608 break; 609 default: 610 return -EINVAL; 611 } 612 613 scoped_guard(raw_spinlock_irqsave, &gpio->lock) { 614 copro = aspeed_gpio_copro_request(gpio, offset); 615 616 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type0, 617 type0); 618 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type1, 619 type1); 620 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type2, 621 type2); 622 623 if (copro) 624 aspeed_gpio_copro_release(gpio, offset); 625 } 626 627 irq_set_handler_locked(d, handler); 628 629 return 0; 630 } 631 632 static void aspeed_gpio_irq_handler(struct irq_desc *desc) 633 { 634 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 635 struct irq_chip *ic = irq_desc_get_chip(desc); 636 unsigned int i, p, banks; 637 unsigned long reg; 638 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 639 640 chained_irq_enter(ic, desc); 641 642 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); 643 for (i = 0; i < banks; i++) { 644 reg = gpio->config->llops->reg_bank_get(gpio, i * 32, reg_irq_status); 645 646 for_each_set_bit(p, ®, 32) 647 generic_handle_domain_irq(gc->irq.domain, i * 32 + p); 648 } 649 650 chained_irq_exit(ic, desc); 651 } 652 653 static void aspeed_init_irq_valid_mask(struct gpio_chip *gc, 654 unsigned long *valid_mask, 655 unsigned int ngpios) 656 { 657 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 658 const struct aspeed_bank_props *props = gpio->config->props; 659 660 while (!is_bank_props_sentinel(props)) { 661 unsigned int offset; 662 const unsigned long int input = props->input; 663 664 /* Pretty crummy approach, but similar to GPIO core */ 665 for_each_clear_bit(offset, &input, 32) { 666 unsigned int i = props->bank * 32 + offset; 667 668 if (i >= gpio->chip.ngpio) 669 break; 670 671 clear_bit(i, valid_mask); 672 } 673 674 props++; 675 } 676 } 677 678 static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip, 679 unsigned int offset, bool enable) 680 { 681 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 682 bool copro = false; 683 684 guard(raw_spinlock_irqsave)(&gpio->lock); 685 686 copro = aspeed_gpio_copro_request(gpio, offset); 687 688 gpio->config->llops->reg_bit_set(gpio, offset, reg_tolerance, enable); 689 690 if (copro) 691 aspeed_gpio_copro_release(gpio, offset); 692 693 return 0; 694 } 695 696 static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset) 697 { 698 if (!have_gpio(gpiochip_get_data(chip), offset)) 699 return -ENODEV; 700 701 return pinctrl_gpio_request(chip, offset); 702 } 703 704 static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset) 705 { 706 pinctrl_gpio_free(chip, offset); 707 } 708 709 static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs, 710 u32 *cycles) 711 { 712 u64 rate; 713 u64 n; 714 u32 r; 715 716 rate = clk_get_rate(gpio->clk); 717 if (!rate) 718 return -ENOTSUPP; 719 720 n = rate * usecs; 721 r = do_div(n, 1000000); 722 723 if (n >= U32_MAX) 724 return -ERANGE; 725 726 /* At least as long as the requested time */ 727 *cycles = n + (!!r); 728 729 return 0; 730 } 731 732 /* Call under gpio->lock */ 733 static int register_allocated_timer(struct aspeed_gpio *gpio, 734 unsigned int offset, unsigned int timer) 735 { 736 if (WARN(gpio->offset_timer[offset] != 0, 737 "Offset %d already allocated timer %d\n", 738 offset, gpio->offset_timer[offset])) 739 return -EINVAL; 740 741 if (WARN(gpio->timer_users[timer] == UINT_MAX, 742 "Timer user count would overflow\n")) 743 return -EPERM; 744 745 gpio->offset_timer[offset] = timer; 746 gpio->timer_users[timer]++; 747 748 return 0; 749 } 750 751 /* Call under gpio->lock */ 752 static int unregister_allocated_timer(struct aspeed_gpio *gpio, 753 unsigned int offset) 754 { 755 if (WARN(gpio->offset_timer[offset] == 0, 756 "No timer allocated to offset %d\n", offset)) 757 return -EINVAL; 758 759 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0, 760 "No users recorded for timer %d\n", 761 gpio->offset_timer[offset])) 762 return -EINVAL; 763 764 gpio->timer_users[gpio->offset_timer[offset]]--; 765 gpio->offset_timer[offset] = 0; 766 767 return 0; 768 } 769 770 /* Call under gpio->lock */ 771 static inline bool timer_allocation_registered(struct aspeed_gpio *gpio, 772 unsigned int offset) 773 { 774 return gpio->offset_timer[offset] > 0; 775 } 776 777 /* Call under gpio->lock */ 778 static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset, 779 unsigned int timer) 780 { 781 /* Note: Debounce timer isn't under control of the command 782 * source registers, so no need to sync with the coprocessor 783 */ 784 gpio->config->llops->reg_bit_set(gpio, offset, reg_debounce_sel1, !!(timer & BIT(1))); 785 gpio->config->llops->reg_bit_set(gpio, offset, reg_debounce_sel2, !!(timer & BIT(0))); 786 } 787 788 static int enable_debounce(struct gpio_chip *chip, unsigned int offset, 789 unsigned long usecs) 790 { 791 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 792 u32 requested_cycles; 793 int rc; 794 int i; 795 796 if (!gpio->clk) 797 return -EINVAL; 798 799 rc = usecs_to_cycles(gpio, usecs, &requested_cycles); 800 if (rc < 0) { 801 dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n", 802 usecs, clk_get_rate(gpio->clk), rc); 803 return rc; 804 } 805 806 guard(raw_spinlock_irqsave)(&gpio->lock); 807 808 if (timer_allocation_registered(gpio, offset)) { 809 rc = unregister_allocated_timer(gpio, offset); 810 if (rc < 0) 811 return rc; 812 } 813 814 /* Try to find a timer already configured for the debounce period */ 815 for (i = 1; i < gpio->config->debounce_timers_num; i++) { 816 u32 cycles; 817 818 cycles = ioread32(gpio->base + gpio->config->debounce_timers_array[i]); 819 if (requested_cycles == cycles) 820 break; 821 } 822 823 if (i == gpio->config->debounce_timers_num) { 824 int j; 825 826 /* 827 * As there are no timers configured for the requested debounce 828 * period, find an unused timer instead 829 */ 830 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) { 831 if (gpio->timer_users[j] == 0) 832 break; 833 } 834 835 if (j == ARRAY_SIZE(gpio->timer_users)) { 836 dev_warn(chip->parent, 837 "Debounce timers exhausted, cannot debounce for period %luus\n", 838 usecs); 839 840 rc = -EPERM; 841 842 /* 843 * We already adjusted the accounting to remove @offset 844 * as a user of its previous timer, so also configure 845 * the hardware so @offset has timers disabled for 846 * consistency. 847 */ 848 configure_timer(gpio, offset, 0); 849 return rc; 850 } 851 852 i = j; 853 854 iowrite32(requested_cycles, gpio->base + gpio->config->debounce_timers_array[i]); 855 } 856 857 if (WARN(i == 0, "Cannot register index of disabled timer\n")) 858 return -EINVAL; 859 860 register_allocated_timer(gpio, offset, i); 861 configure_timer(gpio, offset, i); 862 863 return rc; 864 } 865 866 static int disable_debounce(struct gpio_chip *chip, unsigned int offset) 867 { 868 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 869 int rc; 870 871 guard(raw_spinlock_irqsave)(&gpio->lock); 872 873 rc = unregister_allocated_timer(gpio, offset); 874 if (!rc) 875 configure_timer(gpio, offset, 0); 876 877 return rc; 878 } 879 880 static int set_debounce(struct gpio_chip *chip, unsigned int offset, 881 unsigned long usecs) 882 { 883 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 884 885 if (!have_debounce(gpio, offset)) 886 return -ENOTSUPP; 887 888 if (usecs) 889 return enable_debounce(chip, offset, usecs); 890 891 return disable_debounce(chip, offset); 892 } 893 894 static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 895 unsigned long config) 896 { 897 unsigned long param = pinconf_to_config_param(config); 898 u32 arg = pinconf_to_config_argument(config); 899 900 if (param == PIN_CONFIG_INPUT_DEBOUNCE) 901 return set_debounce(chip, offset, arg); 902 else if (param == PIN_CONFIG_BIAS_DISABLE || 903 param == PIN_CONFIG_BIAS_PULL_DOWN || 904 param == PIN_CONFIG_DRIVE_STRENGTH) 905 return pinctrl_gpio_set_config(chip, offset, config); 906 else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN || 907 param == PIN_CONFIG_DRIVE_OPEN_SOURCE) 908 /* Return -ENOTSUPP to trigger emulation, as per datasheet */ 909 return -ENOTSUPP; 910 else if (param == PIN_CONFIG_PERSIST_STATE) 911 return aspeed_gpio_reset_tolerance(chip, offset, arg); 912 913 return -ENOTSUPP; 914 } 915 916 /** 917 * aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with 918 * the coprocessor for shared GPIO banks 919 * @ops: The callbacks 920 * @data: Pointer passed back to the callbacks 921 */ 922 int aspeed_gpio_copro_set_ops(const struct aspeed_gpio_copro_ops *ops, void *data) 923 { 924 copro_data = data; 925 copro_ops = ops; 926 927 return 0; 928 } 929 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_set_ops); 930 931 /** 932 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire 933 * bank gets marked and any access from the ARM will 934 * result in handshaking via callbacks. 935 * @desc: The GPIO to be marked 936 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space 937 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space 938 * @bit: If non-NULL, returns the bit number of the GPIO in the registers 939 */ 940 int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc, 941 u16 *vreg_offset, u16 *dreg_offset, u8 *bit) 942 { 943 struct gpio_chip *chip = gpiod_to_chip(desc); 944 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 945 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc); 946 const struct aspeed_gpio_bank *bank = to_bank(offset); 947 948 if (!aspeed_gpio_support_copro(gpio)) 949 return -EOPNOTSUPP; 950 951 if (!gpio->cf_copro_bankmap) 952 gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL); 953 if (!gpio->cf_copro_bankmap) 954 return -ENOMEM; 955 if (offset < 0 || offset > gpio->chip.ngpio) 956 return -EINVAL; 957 bindex = offset >> 3; 958 959 guard(raw_spinlock_irqsave)(&gpio->lock); 960 961 /* Sanity check, this shouldn't happen */ 962 if (gpio->cf_copro_bankmap[bindex] == 0xff) 963 return -EIO; 964 965 gpio->cf_copro_bankmap[bindex]++; 966 967 /* Switch command source */ 968 if (gpio->cf_copro_bankmap[bindex] == 1) 969 aspeed_gpio_change_cmd_source(gpio, offset, 970 GPIO_CMDSRC_COLDFIRE); 971 972 if (vreg_offset) 973 *vreg_offset = bank->val_regs; 974 if (dreg_offset) 975 *dreg_offset = bank->rdata_reg; 976 if (bit) 977 *bit = GPIO_OFFSET(offset); 978 return rc; 979 } 980 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio); 981 982 /** 983 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor. 984 * @desc: The GPIO to be marked 985 */ 986 int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc) 987 { 988 struct gpio_chip *chip = gpiod_to_chip(desc); 989 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 990 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc); 991 992 if (!aspeed_gpio_support_copro(gpio)) 993 return -EOPNOTSUPP; 994 995 if (!gpio->cf_copro_bankmap) 996 return -ENXIO; 997 998 if (offset < 0 || offset > gpio->chip.ngpio) 999 return -EINVAL; 1000 bindex = offset >> 3; 1001 1002 guard(raw_spinlock_irqsave)(&gpio->lock); 1003 1004 /* Sanity check, this shouldn't happen */ 1005 if (gpio->cf_copro_bankmap[bindex] == 0) 1006 return -EIO; 1007 1008 gpio->cf_copro_bankmap[bindex]--; 1009 1010 /* Switch command source */ 1011 if (gpio->cf_copro_bankmap[bindex] == 0) 1012 aspeed_gpio_change_cmd_source(gpio, offset, 1013 GPIO_CMDSRC_ARM); 1014 1015 return rc; 1016 } 1017 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio); 1018 1019 static void aspeed_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p) 1020 { 1021 struct aspeed_gpio *gpio; 1022 int rc, offset; 1023 1024 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset); 1025 if (rc) 1026 return; 1027 1028 seq_puts(p, dev_name(gpio->dev)); 1029 } 1030 1031 static const struct irq_chip aspeed_gpio_irq_chip = { 1032 .irq_ack = aspeed_gpio_irq_ack, 1033 .irq_mask = aspeed_gpio_irq_mask, 1034 .irq_unmask = aspeed_gpio_irq_unmask, 1035 .irq_set_type = aspeed_gpio_set_type, 1036 .irq_print_chip = aspeed_gpio_irq_print_chip, 1037 .flags = IRQCHIP_IMMUTABLE, 1038 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1039 }; 1040 1041 static void aspeed_g4_reg_bit_set(struct aspeed_gpio *gpio, unsigned int offset, 1042 const enum aspeed_gpio_reg reg, bool val) 1043 { 1044 const struct aspeed_gpio_bank *bank = to_bank(offset); 1045 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg); 1046 u32 temp; 1047 1048 if (reg == reg_val) 1049 temp = gpio->dcache[GPIO_BANK(offset)]; 1050 else 1051 temp = ioread32(addr); 1052 1053 if (val) 1054 temp |= GPIO_BIT(offset); 1055 else 1056 temp &= ~GPIO_BIT(offset); 1057 1058 if (reg == reg_val) 1059 gpio->dcache[GPIO_BANK(offset)] = temp; 1060 iowrite32(temp, addr); 1061 } 1062 1063 static bool aspeed_g4_reg_bit_get(struct aspeed_gpio *gpio, unsigned int offset, 1064 const enum aspeed_gpio_reg reg) 1065 { 1066 const struct aspeed_gpio_bank *bank = to_bank(offset); 1067 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg); 1068 1069 return !!(ioread32(addr) & GPIO_BIT(offset)); 1070 } 1071 1072 static int aspeed_g4_reg_bank_get(struct aspeed_gpio *gpio, unsigned int offset, 1073 const enum aspeed_gpio_reg reg) 1074 { 1075 const struct aspeed_gpio_bank *bank = to_bank(offset); 1076 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg); 1077 1078 if (reg == reg_rdata || reg == reg_irq_status) 1079 return ioread32(addr); 1080 else 1081 return -EOPNOTSUPP; 1082 } 1083 1084 static void aspeed_g4_privilege_ctrl(struct aspeed_gpio *gpio, unsigned int offset, int cmdsrc) 1085 { 1086 /* 1087 * The command source register is only valid in bits 0, 8, 16, and 24, so we use 1088 * (offset & ~(0x7)) to ensure that reg_bits_set always targets a valid bit. 1089 */ 1090 /* Source 1 first to avoid illegal 11 combination */ 1091 aspeed_g4_reg_bit_set(gpio, offset & ~(0x7), reg_cmdsrc1, !!(cmdsrc & BIT(1))); 1092 /* Then Source 0 */ 1093 aspeed_g4_reg_bit_set(gpio, offset & ~(0x7), reg_cmdsrc0, !!(cmdsrc & BIT(0))); 1094 } 1095 1096 static void aspeed_g4_privilege_init(struct aspeed_gpio *gpio) 1097 { 1098 u32 i; 1099 1100 /* Switch all command sources to the ARM by default */ 1101 for (i = 0; i < DIV_ROUND_UP(gpio->chip.ngpio, 32); i++) { 1102 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 0, GPIO_CMDSRC_ARM); 1103 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 8, GPIO_CMDSRC_ARM); 1104 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 16, GPIO_CMDSRC_ARM); 1105 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 24, GPIO_CMDSRC_ARM); 1106 } 1107 } 1108 1109 static bool aspeed_g4_copro_request(struct aspeed_gpio *gpio, unsigned int offset) 1110 { 1111 if (!copro_ops || !gpio->cf_copro_bankmap) 1112 return false; 1113 if (!gpio->cf_copro_bankmap[offset >> 3]) 1114 return false; 1115 if (!copro_ops->request_access) 1116 return false; 1117 1118 /* Pause the coprocessor */ 1119 copro_ops->request_access(copro_data); 1120 1121 /* Change command source back to ARM */ 1122 aspeed_g4_privilege_ctrl(gpio, offset, GPIO_CMDSRC_ARM); 1123 1124 /* Update cache */ 1125 gpio->dcache[GPIO_BANK(offset)] = aspeed_g4_reg_bank_get(gpio, offset, reg_rdata); 1126 1127 return true; 1128 } 1129 1130 static void aspeed_g4_copro_release(struct aspeed_gpio *gpio, unsigned int offset) 1131 { 1132 if (!copro_ops || !gpio->cf_copro_bankmap) 1133 return; 1134 if (!gpio->cf_copro_bankmap[offset >> 3]) 1135 return; 1136 if (!copro_ops->release_access) 1137 return; 1138 1139 /* Change command source back to ColdFire */ 1140 aspeed_g4_privilege_ctrl(gpio, offset, GPIO_CMDSRC_COLDFIRE); 1141 1142 /* Restart the coprocessor */ 1143 copro_ops->release_access(copro_data); 1144 } 1145 1146 static const struct aspeed_gpio_llops aspeed_g4_llops = { 1147 .reg_bit_set = aspeed_g4_reg_bit_set, 1148 .reg_bit_get = aspeed_g4_reg_bit_get, 1149 .reg_bank_get = aspeed_g4_reg_bank_get, 1150 .privilege_ctrl = aspeed_g4_privilege_ctrl, 1151 .privilege_init = aspeed_g4_privilege_init, 1152 .copro_request = aspeed_g4_copro_request, 1153 .copro_release = aspeed_g4_copro_release, 1154 }; 1155 1156 static void aspeed_g7_reg_bit_set(struct aspeed_gpio *gpio, unsigned int offset, 1157 const enum aspeed_gpio_reg reg, bool val) 1158 { 1159 u32 mask = aspeed_gpio_g7_reg_mask(reg); 1160 void __iomem *addr = gpio->base + GPIO_G7_CTRL_REG_OFFSET(offset); 1161 u32 write_val; 1162 1163 if (mask) { 1164 write_val = (ioread32(addr) & ~(mask)) | field_prep(mask, val); 1165 iowrite32(write_val, addr); 1166 } 1167 } 1168 1169 static bool aspeed_g7_reg_bit_get(struct aspeed_gpio *gpio, unsigned int offset, 1170 const enum aspeed_gpio_reg reg) 1171 { 1172 u32 mask = aspeed_gpio_g7_reg_mask(reg); 1173 void __iomem *addr; 1174 1175 addr = gpio->base + GPIO_G7_CTRL_REG_OFFSET(offset); 1176 if (reg == reg_val) 1177 mask = GPIO_G7_CTRL_IN_DATA; 1178 1179 if (mask) 1180 return field_get(mask, ioread32(addr)); 1181 else 1182 return 0; 1183 } 1184 1185 static int aspeed_g7_reg_bank_get(struct aspeed_gpio *gpio, unsigned int offset, 1186 const enum aspeed_gpio_reg reg) 1187 { 1188 void __iomem *addr; 1189 1190 if (reg == reg_irq_status) { 1191 addr = gpio->base + GPIO_G7_IRQ_STS_OFFSET(offset >> 5); 1192 return ioread32(addr); 1193 } else { 1194 return -EOPNOTSUPP; 1195 } 1196 } 1197 1198 static const struct aspeed_gpio_llops aspeed_g7_llops = { 1199 .reg_bit_set = aspeed_g7_reg_bit_set, 1200 .reg_bit_get = aspeed_g7_reg_bit_get, 1201 .reg_bank_get = aspeed_g7_reg_bank_get, 1202 .privilege_ctrl = NULL, 1203 .privilege_init = NULL, 1204 .copro_request = NULL, 1205 .copro_release = NULL, 1206 }; 1207 1208 /* 1209 * Any banks not specified in a struct aspeed_bank_props array are assumed to 1210 * have the properties: 1211 * 1212 * { .input = 0xffffffff, .output = 0xffffffff } 1213 */ 1214 1215 static const struct aspeed_bank_props ast2400_bank_props[] = { 1216 /* input output */ 1217 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ 1218 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */ 1219 { }, 1220 }; 1221 1222 static const struct aspeed_gpio_config ast2400_config = 1223 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */ 1224 { 1225 .nr_gpios = 220, 1226 .props = ast2400_bank_props, 1227 .llops = &aspeed_g4_llops, 1228 .debounce_timers_array = debounce_timers, 1229 .debounce_timers_num = ARRAY_SIZE(debounce_timers), 1230 .require_dcache = true, 1231 }; 1232 1233 static const struct aspeed_bank_props ast2500_bank_props[] = { 1234 /* input output */ 1235 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ 1236 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */ 1237 { 7, 0x000000ff, 0x000000ff }, /* AC */ 1238 { }, 1239 }; 1240 1241 static const struct aspeed_gpio_config ast2500_config = 1242 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */ 1243 { 1244 .nr_gpios = 232, 1245 .props = ast2500_bank_props, 1246 .llops = &aspeed_g4_llops, 1247 .debounce_timers_array = debounce_timers, 1248 .debounce_timers_num = ARRAY_SIZE(debounce_timers), 1249 .require_dcache = true, 1250 }; 1251 1252 static const struct aspeed_bank_props ast2600_bank_props[] = { 1253 /* input output */ 1254 {4, 0xffffffff, 0x00ffffff}, /* Q/R/S/T */ 1255 {5, 0xffffffff, 0xffffff00}, /* U/V/W/X */ 1256 {6, 0x0000ffff, 0x0000ffff}, /* Y/Z */ 1257 { }, 1258 }; 1259 1260 static const struct aspeed_gpio_config ast2600_config = 1261 /* 1262 * ast2600 has two controllers one with 208 GPIOs and one with 36 GPIOs. 1263 * We expect ngpio being set in the device tree and this is a fallback 1264 * option. 1265 */ 1266 { 1267 .nr_gpios = 208, 1268 .props = ast2600_bank_props, 1269 .llops = &aspeed_g4_llops, 1270 .debounce_timers_array = debounce_timers, 1271 .debounce_timers_num = ARRAY_SIZE(debounce_timers), 1272 .require_dcache = true, 1273 }; 1274 1275 static const struct aspeed_bank_props ast2700_bank_props[] = { 1276 /* input output */ 1277 { 1, 0x0fffffff, 0x0fffffff }, /* E/F/G/H, 4-GPIO hole */ 1278 { 6, 0x00ffffff, 0x00ff0000 }, /* Y/Z/AA */ 1279 {}, 1280 }; 1281 1282 static const struct aspeed_gpio_config ast2700_config = 1283 /* 1284 * ast2700 has two controllers one with 212 GPIOs and one with 16 GPIOs. 1285 * 216 for simplicity, actual number is 212 (4-GPIO hole in GPIOH) 1286 * We expect ngpio being set in the device tree and this is a fallback 1287 * option. 1288 */ 1289 { 1290 .nr_gpios = 216, 1291 .props = ast2700_bank_props, 1292 .llops = &aspeed_g7_llops, 1293 .debounce_timers_array = g7_debounce_timers, 1294 .debounce_timers_num = ARRAY_SIZE(g7_debounce_timers), 1295 .require_dcache = false, 1296 }; 1297 1298 static const struct of_device_id aspeed_gpio_of_table[] = { 1299 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, }, 1300 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, }, 1301 { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, }, 1302 { .compatible = "aspeed,ast2700-gpio", .data = &ast2700_config, }, 1303 {} 1304 }; 1305 MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table); 1306 1307 static int aspeed_gpio_probe(struct platform_device *pdev) 1308 { 1309 const struct of_device_id *gpio_id; 1310 struct gpio_irq_chip *girq; 1311 struct aspeed_gpio *gpio; 1312 int rc, irq, i, banks, err; 1313 u32 ngpio; 1314 1315 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 1316 if (!gpio) 1317 return -ENOMEM; 1318 1319 gpio->base = devm_platform_ioremap_resource(pdev, 0); 1320 if (IS_ERR(gpio->base)) 1321 return PTR_ERR(gpio->base); 1322 1323 gpio->dev = &pdev->dev; 1324 1325 raw_spin_lock_init(&gpio->lock); 1326 1327 gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); 1328 if (!gpio_id) 1329 return -EINVAL; 1330 1331 gpio->clk = devm_clk_get_enabled(&pdev->dev, NULL); 1332 if (IS_ERR(gpio->clk)) { 1333 dev_warn(&pdev->dev, 1334 "Failed to get clock from devicetree, debouncing disabled\n"); 1335 gpio->clk = NULL; 1336 } 1337 1338 gpio->config = gpio_id->data; 1339 1340 if (!gpio->config->llops->reg_bit_set || !gpio->config->llops->reg_bit_get || 1341 !gpio->config->llops->reg_bank_get) 1342 return -EINVAL; 1343 1344 gpio->chip.parent = &pdev->dev; 1345 err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio); 1346 gpio->chip.ngpio = (u16) ngpio; 1347 if (err) 1348 gpio->chip.ngpio = gpio->config->nr_gpios; 1349 gpio->chip.direction_input = aspeed_gpio_dir_in; 1350 gpio->chip.direction_output = aspeed_gpio_dir_out; 1351 gpio->chip.get_direction = aspeed_gpio_get_direction; 1352 gpio->chip.request = aspeed_gpio_request; 1353 gpio->chip.free = aspeed_gpio_free; 1354 gpio->chip.get = aspeed_gpio_get; 1355 gpio->chip.set_rv = aspeed_gpio_set; 1356 gpio->chip.set_config = aspeed_gpio_set_config; 1357 gpio->chip.label = dev_name(&pdev->dev); 1358 gpio->chip.base = -1; 1359 1360 if (gpio->config->require_dcache) { 1361 /* Allocate a cache of the output registers */ 1362 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); 1363 gpio->dcache = devm_kcalloc(&pdev->dev, banks, sizeof(u32), GFP_KERNEL); 1364 if (!gpio->dcache) 1365 return -ENOMEM; 1366 /* 1367 * Populate it with initial values read from the HW 1368 */ 1369 for (i = 0; i < banks; i++) 1370 gpio->dcache[i] = 1371 gpio->config->llops->reg_bank_get(gpio, (i << 5), reg_rdata); 1372 } 1373 1374 if (gpio->config->llops->privilege_init) 1375 gpio->config->llops->privilege_init(gpio); 1376 1377 /* Set up an irqchip */ 1378 irq = platform_get_irq(pdev, 0); 1379 if (irq < 0) 1380 return irq; 1381 gpio->irq = irq; 1382 girq = &gpio->chip.irq; 1383 gpio_irq_chip_set_chip(girq, &aspeed_gpio_irq_chip); 1384 1385 girq->parent_handler = aspeed_gpio_irq_handler; 1386 girq->num_parents = 1; 1387 girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), GFP_KERNEL); 1388 if (!girq->parents) 1389 return -ENOMEM; 1390 girq->parents[0] = gpio->irq; 1391 girq->default_type = IRQ_TYPE_NONE; 1392 girq->handler = handle_bad_irq; 1393 girq->init_valid_mask = aspeed_init_irq_valid_mask; 1394 1395 gpio->offset_timer = 1396 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL); 1397 if (!gpio->offset_timer) 1398 return -ENOMEM; 1399 1400 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); 1401 if (rc < 0) 1402 return rc; 1403 1404 return 0; 1405 } 1406 1407 static struct platform_driver aspeed_gpio_driver = { 1408 .probe = aspeed_gpio_probe, 1409 .driver = { 1410 .name = KBUILD_MODNAME, 1411 .of_match_table = aspeed_gpio_of_table, 1412 }, 1413 }; 1414 1415 module_platform_driver(aspeed_gpio_driver); 1416 1417 MODULE_DESCRIPTION("Aspeed GPIO Driver"); 1418 MODULE_LICENSE("GPL"); 1419