1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2015 IBM Corp. 4 * 5 * Joel Stanley <joel@jms.id.au> 6 */ 7 8 #include <linux/cleanup.h> 9 #include <linux/clk.h> 10 #include <linux/gpio/aspeed.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/hashtable.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/platform_device.h> 19 #include <linux/seq_file.h> 20 #include <linux/spinlock.h> 21 #include <linux/string.h> 22 23 #include <asm/div64.h> 24 25 /* 26 * These two headers aren't meant to be used by GPIO drivers. We need 27 * them in order to access gpiod_hwgpio() which we need to implement 28 * the aspeed specific API which allows the coprocessor to request 29 * access to some GPIOs and to arbitrate between coprocessor and ARM. 30 */ 31 #include <linux/gpio/consumer.h> 32 33 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ 34 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) 35 #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) 36 37 #define GPIO_G7_IRQ_STS_BASE 0x100 38 #define GPIO_G7_IRQ_STS_OFFSET(x) (GPIO_G7_IRQ_STS_BASE + (x) * 0x4) 39 #define GPIO_G7_CTRL_REG_BASE 0x180 40 #define GPIO_G7_CTRL_REG_OFFSET(x) (GPIO_G7_CTRL_REG_BASE + (x) * 0x4) 41 #define GPIO_G7_CTRL_OUT_DATA BIT(0) 42 #define GPIO_G7_CTRL_DIR BIT(1) 43 #define GPIO_G7_CTRL_IRQ_EN BIT(2) 44 #define GPIO_G7_CTRL_IRQ_TYPE0 BIT(3) 45 #define GPIO_G7_CTRL_IRQ_TYPE1 BIT(4) 46 #define GPIO_G7_CTRL_IRQ_TYPE2 BIT(5) 47 #define GPIO_G7_CTRL_RST_TOLERANCE BIT(6) 48 #define GPIO_G7_CTRL_DEBOUNCE_SEL1 BIT(7) 49 #define GPIO_G7_CTRL_DEBOUNCE_SEL2 BIT(8) 50 #define GPIO_G7_CTRL_INPUT_MASK BIT(9) 51 #define GPIO_G7_CTRL_IRQ_STS BIT(12) 52 #define GPIO_G7_CTRL_IN_DATA BIT(13) 53 54 struct aspeed_bank_props { 55 unsigned int bank; 56 u32 input; 57 u32 output; 58 }; 59 60 struct aspeed_gpio_config { 61 unsigned int nr_gpios; 62 const struct aspeed_bank_props *props; 63 const struct aspeed_gpio_llops *llops; 64 const int *debounce_timers_array; 65 int debounce_timers_num; 66 bool require_dcache; 67 }; 68 69 /* 70 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled 71 * @timer_users: Tracks the number of users for each timer 72 * 73 * The @timer_users has four elements but the first element is unused. This is 74 * to simplify accounting and indexing, as a zero value in @offset_timer 75 * represents disabled debouncing for the GPIO. Any other value for an element 76 * of @offset_timer is used as an index into @timer_users. This behaviour of 77 * the zero value aligns with the behaviour of zero built from the timer 78 * configuration registers (i.e. debouncing is disabled). 79 */ 80 struct aspeed_gpio { 81 struct gpio_chip chip; 82 struct device *dev; 83 raw_spinlock_t lock; 84 void __iomem *base; 85 int irq; 86 const struct aspeed_gpio_config *config; 87 88 u8 *offset_timer; 89 unsigned int timer_users[4]; 90 struct clk *clk; 91 92 u32 *dcache; 93 u8 *cf_copro_bankmap; 94 }; 95 96 struct aspeed_gpio_bank { 97 uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch 98 * +4: Rd/Wr: Direction (0=in, 1=out) 99 */ 100 uint16_t rdata_reg; /* Rd: read write latch, Wr: <none> */ 101 uint16_t irq_regs; 102 uint16_t debounce_regs; 103 uint16_t tolerance_regs; 104 uint16_t cmdsrc_regs; 105 }; 106 107 /* 108 * Note: The "value" register returns the input value sampled on the 109 * line even when the GPIO is configured as an output. Since 110 * that input goes through synchronizers, writing, then reading 111 * back may not return the written value right away. 112 * 113 * The "rdata" register returns the content of the write latch 114 * and thus can be used to read back what was last written 115 * reliably. 116 */ 117 118 static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 }; 119 static const int g7_debounce_timers[4] = { 0x00, 0x00, 0x04, 0x08 }; 120 121 /* 122 * The debounce timers array is used to configure the debounce timer settings.Here’s how it works: 123 * Array Value: Indicates the offset for configuring the debounce timer. 124 * Array Index: Corresponds to the debounce setting register. 125 * The debounce timers array follows this pattern for configuring the debounce setting registers: 126 * Array Index 0: No debounce timer is set; 127 * Array Value is irrelevant (don’t care). 128 * Array Index 1: Debounce setting #2 is set to 1, and debounce setting #1 is set to 0. 129 * Array Value: offset for configuring debounce timer 0 (g4: 0x50, g7: 0x00) 130 * Array Index 2: Debounce setting #2 is set to 0, and debounce setting #1 is set to 1. 131 * Array Value: offset for configuring debounce timer 1 (g4: 0x54, g7: 0x04) 132 * Array Index 3: Debounce setting #2 is set to 1, and debounce setting #1 is set to 1. 133 * Array Value: offset for configuring debounce timer 2 (g4: 0x58, g7: 0x8) 134 */ 135 136 static const struct aspeed_gpio_copro_ops *copro_ops; 137 static void *copro_data; 138 139 static const struct aspeed_gpio_bank aspeed_gpio_banks[] = { 140 { 141 .val_regs = 0x0000, 142 .rdata_reg = 0x00c0, 143 .irq_regs = 0x0008, 144 .debounce_regs = 0x0040, 145 .tolerance_regs = 0x001c, 146 .cmdsrc_regs = 0x0060, 147 }, 148 { 149 .val_regs = 0x0020, 150 .rdata_reg = 0x00c4, 151 .irq_regs = 0x0028, 152 .debounce_regs = 0x0048, 153 .tolerance_regs = 0x003c, 154 .cmdsrc_regs = 0x0068, 155 }, 156 { 157 .val_regs = 0x0070, 158 .rdata_reg = 0x00c8, 159 .irq_regs = 0x0098, 160 .debounce_regs = 0x00b0, 161 .tolerance_regs = 0x00ac, 162 .cmdsrc_regs = 0x0090, 163 }, 164 { 165 .val_regs = 0x0078, 166 .rdata_reg = 0x00cc, 167 .irq_regs = 0x00e8, 168 .debounce_regs = 0x0100, 169 .tolerance_regs = 0x00fc, 170 .cmdsrc_regs = 0x00e0, 171 }, 172 { 173 .val_regs = 0x0080, 174 .rdata_reg = 0x00d0, 175 .irq_regs = 0x0118, 176 .debounce_regs = 0x0130, 177 .tolerance_regs = 0x012c, 178 .cmdsrc_regs = 0x0110, 179 }, 180 { 181 .val_regs = 0x0088, 182 .rdata_reg = 0x00d4, 183 .irq_regs = 0x0148, 184 .debounce_regs = 0x0160, 185 .tolerance_regs = 0x015c, 186 .cmdsrc_regs = 0x0140, 187 }, 188 { 189 .val_regs = 0x01E0, 190 .rdata_reg = 0x00d8, 191 .irq_regs = 0x0178, 192 .debounce_regs = 0x0190, 193 .tolerance_regs = 0x018c, 194 .cmdsrc_regs = 0x0170, 195 }, 196 { 197 .val_regs = 0x01e8, 198 .rdata_reg = 0x00dc, 199 .irq_regs = 0x01a8, 200 .debounce_regs = 0x01c0, 201 .tolerance_regs = 0x01bc, 202 .cmdsrc_regs = 0x01a0, 203 }, 204 }; 205 206 enum aspeed_gpio_reg { 207 reg_val, 208 reg_rdata, 209 reg_dir, 210 reg_irq_enable, 211 reg_irq_type0, 212 reg_irq_type1, 213 reg_irq_type2, 214 reg_irq_status, 215 reg_debounce_sel1, 216 reg_debounce_sel2, 217 reg_tolerance, 218 reg_cmdsrc0, 219 reg_cmdsrc1, 220 }; 221 222 struct aspeed_gpio_llops { 223 void (*reg_bit_set)(struct aspeed_gpio *gpio, unsigned int offset, 224 const enum aspeed_gpio_reg reg, bool val); 225 bool (*reg_bit_get)(struct aspeed_gpio *gpio, unsigned int offset, 226 const enum aspeed_gpio_reg reg); 227 int (*reg_bank_get)(struct aspeed_gpio *gpio, unsigned int offset, 228 const enum aspeed_gpio_reg reg); 229 void (*privilege_ctrl)(struct aspeed_gpio *gpio, unsigned int offset, int owner); 230 void (*privilege_init)(struct aspeed_gpio *gpio); 231 bool (*copro_request)(struct aspeed_gpio *gpio, unsigned int offset); 232 void (*copro_release)(struct aspeed_gpio *gpio, unsigned int offset); 233 }; 234 235 #define GPIO_VAL_VALUE 0x00 236 #define GPIO_VAL_DIR 0x04 237 238 #define GPIO_IRQ_ENABLE 0x00 239 #define GPIO_IRQ_TYPE0 0x04 240 #define GPIO_IRQ_TYPE1 0x08 241 #define GPIO_IRQ_TYPE2 0x0c 242 #define GPIO_IRQ_STATUS 0x10 243 244 #define GPIO_DEBOUNCE_SEL1 0x00 245 #define GPIO_DEBOUNCE_SEL2 0x04 246 247 #define GPIO_CMDSRC_0 0x00 248 #define GPIO_CMDSRC_1 0x04 249 #define GPIO_CMDSRC_ARM 0 250 #define GPIO_CMDSRC_LPC 1 251 #define GPIO_CMDSRC_COLDFIRE 2 252 #define GPIO_CMDSRC_RESERVED 3 253 254 /* This will be resolved at compile time */ 255 static void __iomem *aspeed_gpio_g4_bank_reg(struct aspeed_gpio *gpio, 256 const struct aspeed_gpio_bank *bank, 257 const enum aspeed_gpio_reg reg) 258 { 259 switch (reg) { 260 case reg_val: 261 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; 262 case reg_rdata: 263 return gpio->base + bank->rdata_reg; 264 case reg_dir: 265 return gpio->base + bank->val_regs + GPIO_VAL_DIR; 266 case reg_irq_enable: 267 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; 268 case reg_irq_type0: 269 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; 270 case reg_irq_type1: 271 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; 272 case reg_irq_type2: 273 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; 274 case reg_irq_status: 275 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; 276 case reg_debounce_sel1: 277 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1; 278 case reg_debounce_sel2: 279 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2; 280 case reg_tolerance: 281 return gpio->base + bank->tolerance_regs; 282 case reg_cmdsrc0: 283 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0; 284 case reg_cmdsrc1: 285 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1; 286 } 287 BUG(); 288 } 289 290 static u32 aspeed_gpio_g7_reg_mask(const enum aspeed_gpio_reg reg) 291 { 292 switch (reg) { 293 case reg_val: 294 return GPIO_G7_CTRL_OUT_DATA; 295 case reg_dir: 296 return GPIO_G7_CTRL_DIR; 297 case reg_irq_enable: 298 return GPIO_G7_CTRL_IRQ_EN; 299 case reg_irq_type0: 300 return GPIO_G7_CTRL_IRQ_TYPE0; 301 case reg_irq_type1: 302 return GPIO_G7_CTRL_IRQ_TYPE1; 303 case reg_irq_type2: 304 return GPIO_G7_CTRL_IRQ_TYPE2; 305 case reg_tolerance: 306 return GPIO_G7_CTRL_RST_TOLERANCE; 307 case reg_debounce_sel1: 308 return GPIO_G7_CTRL_DEBOUNCE_SEL1; 309 case reg_debounce_sel2: 310 return GPIO_G7_CTRL_DEBOUNCE_SEL2; 311 case reg_rdata: 312 return GPIO_G7_CTRL_OUT_DATA; 313 case reg_irq_status: 314 return GPIO_G7_CTRL_IRQ_STS; 315 case reg_cmdsrc0: 316 case reg_cmdsrc1: 317 default: 318 WARN_ON_ONCE(1); 319 return 0; 320 } 321 } 322 323 #define GPIO_BANK(x) ((x) >> 5) 324 #define GPIO_OFFSET(x) ((x) & 0x1f) 325 #define GPIO_BIT(x) BIT(GPIO_OFFSET(x)) 326 327 static const struct aspeed_gpio_bank *to_bank(unsigned int offset) 328 { 329 unsigned int bank = GPIO_BANK(offset); 330 331 WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks)); 332 return &aspeed_gpio_banks[bank]; 333 } 334 335 static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props) 336 { 337 return !(props->input || props->output); 338 } 339 340 static inline const struct aspeed_bank_props *find_bank_props( 341 struct aspeed_gpio *gpio, unsigned int offset) 342 { 343 const struct aspeed_bank_props *props = gpio->config->props; 344 345 while (!is_bank_props_sentinel(props)) { 346 if (props->bank == GPIO_BANK(offset)) 347 return props; 348 props++; 349 } 350 351 return NULL; 352 } 353 354 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset) 355 { 356 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 357 358 if (offset >= gpio->chip.ngpio) 359 return false; 360 361 return (!props || ((props->input | props->output) & GPIO_BIT(offset))); 362 } 363 364 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset) 365 { 366 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 367 368 return !props || (props->input & GPIO_BIT(offset)); 369 } 370 371 #define have_irq(g, o) have_input((g), (o)) 372 #define have_debounce(g, o) have_input((g), (o)) 373 374 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset) 375 { 376 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 377 378 return !props || (props->output & GPIO_BIT(offset)); 379 } 380 381 static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio, unsigned int offset, int cmdsrc) 382 { 383 if (gpio->config->llops->privilege_ctrl) 384 gpio->config->llops->privilege_ctrl(gpio, offset, cmdsrc); 385 } 386 387 static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio, 388 unsigned int offset) 389 { 390 if (gpio->config->llops->copro_request) 391 return gpio->config->llops->copro_request(gpio, offset); 392 393 return false; 394 } 395 396 static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio, 397 unsigned int offset) 398 { 399 if (gpio->config->llops->copro_release) 400 gpio->config->llops->copro_release(gpio, offset); 401 } 402 403 static bool aspeed_gpio_support_copro(struct aspeed_gpio *gpio) 404 { 405 return gpio->config->llops->copro_request && gpio->config->llops->copro_release && 406 gpio->config->llops->privilege_ctrl && gpio->config->llops->privilege_init; 407 } 408 409 static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset) 410 { 411 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 412 413 return gpio->config->llops->reg_bit_get(gpio, offset, reg_val); 414 } 415 416 static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, 417 int val) 418 { 419 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 420 421 gpio->config->llops->reg_bit_set(gpio, offset, reg_val, val); 422 /* Flush write */ 423 gpio->config->llops->reg_bit_get(gpio, offset, reg_val); 424 } 425 426 static int aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, int val) 427 { 428 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 429 bool copro = false; 430 431 guard(raw_spinlock_irqsave)(&gpio->lock); 432 433 copro = aspeed_gpio_copro_request(gpio, offset); 434 435 __aspeed_gpio_set(gc, offset, val); 436 437 if (copro) 438 aspeed_gpio_copro_release(gpio, offset); 439 440 return 0; 441 } 442 443 static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset) 444 { 445 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 446 bool copro = false; 447 448 if (!have_input(gpio, offset)) 449 return -ENOTSUPP; 450 451 guard(raw_spinlock_irqsave)(&gpio->lock); 452 453 copro = aspeed_gpio_copro_request(gpio, offset); 454 gpio->config->llops->reg_bit_set(gpio, offset, reg_dir, 0); 455 if (copro) 456 aspeed_gpio_copro_release(gpio, offset); 457 458 return 0; 459 } 460 461 static int aspeed_gpio_dir_out(struct gpio_chip *gc, 462 unsigned int offset, int val) 463 { 464 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 465 bool copro = false; 466 467 if (!have_output(gpio, offset)) 468 return -ENOTSUPP; 469 470 guard(raw_spinlock_irqsave)(&gpio->lock); 471 472 copro = aspeed_gpio_copro_request(gpio, offset); 473 __aspeed_gpio_set(gc, offset, val); 474 gpio->config->llops->reg_bit_set(gpio, offset, reg_dir, 1); 475 476 if (copro) 477 aspeed_gpio_copro_release(gpio, offset); 478 479 return 0; 480 } 481 482 static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 483 { 484 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 485 u32 val; 486 487 if (!have_input(gpio, offset)) 488 return GPIO_LINE_DIRECTION_OUT; 489 490 if (!have_output(gpio, offset)) 491 return GPIO_LINE_DIRECTION_IN; 492 493 guard(raw_spinlock_irqsave)(&gpio->lock); 494 495 val = gpio->config->llops->reg_bit_get(gpio, offset, reg_dir); 496 497 return val ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 498 } 499 500 static inline int irqd_to_aspeed_gpio_data(struct irq_data *d, 501 struct aspeed_gpio **gpio, 502 int *offset) 503 { 504 struct aspeed_gpio *internal; 505 506 *offset = irqd_to_hwirq(d); 507 508 internal = irq_data_get_irq_chip_data(d); 509 510 /* This might be a bit of a questionable place to check */ 511 if (!have_irq(internal, *offset)) 512 return -ENOTSUPP; 513 514 *gpio = internal; 515 516 return 0; 517 } 518 519 static void aspeed_gpio_irq_ack(struct irq_data *d) 520 { 521 struct aspeed_gpio *gpio; 522 int rc, offset; 523 bool copro = false; 524 525 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset); 526 if (rc) 527 return; 528 529 guard(raw_spinlock_irqsave)(&gpio->lock); 530 531 copro = aspeed_gpio_copro_request(gpio, offset); 532 533 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_status, 1); 534 535 if (copro) 536 aspeed_gpio_copro_release(gpio, offset); 537 } 538 539 static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set) 540 { 541 struct aspeed_gpio *gpio; 542 int rc, offset; 543 bool copro = false; 544 545 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset); 546 if (rc) 547 return; 548 549 /* Unmasking the IRQ */ 550 if (set) 551 gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d)); 552 553 guard(raw_spinlock_irqsave)(&gpio->lock); 554 555 copro = aspeed_gpio_copro_request(gpio, offset); 556 557 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_enable, set); 558 559 if (copro) 560 aspeed_gpio_copro_release(gpio, offset); 561 562 /* Masking the IRQ */ 563 if (!set) 564 gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(d)); 565 } 566 567 static void aspeed_gpio_irq_mask(struct irq_data *d) 568 { 569 aspeed_gpio_irq_set_mask(d, false); 570 } 571 572 static void aspeed_gpio_irq_unmask(struct irq_data *d) 573 { 574 aspeed_gpio_irq_set_mask(d, true); 575 } 576 577 static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type) 578 { 579 u32 type0 = 0; 580 u32 type1 = 0; 581 u32 type2 = 0; 582 irq_flow_handler_t handler; 583 struct aspeed_gpio *gpio; 584 int rc, offset; 585 bool copro = false; 586 587 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset); 588 if (rc) 589 return -EINVAL; 590 591 switch (type & IRQ_TYPE_SENSE_MASK) { 592 case IRQ_TYPE_EDGE_BOTH: 593 type2 = 1; 594 fallthrough; 595 case IRQ_TYPE_EDGE_RISING: 596 type0 = 1; 597 fallthrough; 598 case IRQ_TYPE_EDGE_FALLING: 599 handler = handle_edge_irq; 600 break; 601 case IRQ_TYPE_LEVEL_HIGH: 602 type0 = 1; 603 fallthrough; 604 case IRQ_TYPE_LEVEL_LOW: 605 type1 = 1; 606 handler = handle_level_irq; 607 break; 608 default: 609 return -EINVAL; 610 } 611 612 scoped_guard(raw_spinlock_irqsave, &gpio->lock) { 613 copro = aspeed_gpio_copro_request(gpio, offset); 614 615 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type0, 616 type0); 617 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type1, 618 type1); 619 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type2, 620 type2); 621 622 if (copro) 623 aspeed_gpio_copro_release(gpio, offset); 624 } 625 626 irq_set_handler_locked(d, handler); 627 628 return 0; 629 } 630 631 static void aspeed_gpio_irq_handler(struct irq_desc *desc) 632 { 633 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 634 struct irq_chip *ic = irq_desc_get_chip(desc); 635 unsigned int i, p, banks; 636 unsigned long reg; 637 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 638 639 chained_irq_enter(ic, desc); 640 641 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); 642 for (i = 0; i < banks; i++) { 643 reg = gpio->config->llops->reg_bank_get(gpio, i * 32, reg_irq_status); 644 645 for_each_set_bit(p, ®, 32) 646 generic_handle_domain_irq(gc->irq.domain, i * 32 + p); 647 } 648 649 chained_irq_exit(ic, desc); 650 } 651 652 static void aspeed_init_irq_valid_mask(struct gpio_chip *gc, 653 unsigned long *valid_mask, 654 unsigned int ngpios) 655 { 656 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 657 const struct aspeed_bank_props *props = gpio->config->props; 658 659 while (!is_bank_props_sentinel(props)) { 660 unsigned int offset; 661 const unsigned long int input = props->input; 662 663 /* Pretty crummy approach, but similar to GPIO core */ 664 for_each_clear_bit(offset, &input, 32) { 665 unsigned int i = props->bank * 32 + offset; 666 667 if (i >= gpio->chip.ngpio) 668 break; 669 670 clear_bit(i, valid_mask); 671 } 672 673 props++; 674 } 675 } 676 677 static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip, 678 unsigned int offset, bool enable) 679 { 680 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 681 bool copro = false; 682 683 guard(raw_spinlock_irqsave)(&gpio->lock); 684 685 copro = aspeed_gpio_copro_request(gpio, offset); 686 687 gpio->config->llops->reg_bit_set(gpio, offset, reg_tolerance, enable); 688 689 if (copro) 690 aspeed_gpio_copro_release(gpio, offset); 691 692 return 0; 693 } 694 695 static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset) 696 { 697 if (!have_gpio(gpiochip_get_data(chip), offset)) 698 return -ENODEV; 699 700 return pinctrl_gpio_request(chip, offset); 701 } 702 703 static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset) 704 { 705 pinctrl_gpio_free(chip, offset); 706 } 707 708 static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs, 709 u32 *cycles) 710 { 711 u64 rate; 712 u64 n; 713 u32 r; 714 715 rate = clk_get_rate(gpio->clk); 716 if (!rate) 717 return -ENOTSUPP; 718 719 n = rate * usecs; 720 r = do_div(n, 1000000); 721 722 if (n >= U32_MAX) 723 return -ERANGE; 724 725 /* At least as long as the requested time */ 726 *cycles = n + (!!r); 727 728 return 0; 729 } 730 731 /* Call under gpio->lock */ 732 static int register_allocated_timer(struct aspeed_gpio *gpio, 733 unsigned int offset, unsigned int timer) 734 { 735 if (WARN(gpio->offset_timer[offset] != 0, 736 "Offset %d already allocated timer %d\n", 737 offset, gpio->offset_timer[offset])) 738 return -EINVAL; 739 740 if (WARN(gpio->timer_users[timer] == UINT_MAX, 741 "Timer user count would overflow\n")) 742 return -EPERM; 743 744 gpio->offset_timer[offset] = timer; 745 gpio->timer_users[timer]++; 746 747 return 0; 748 } 749 750 /* Call under gpio->lock */ 751 static int unregister_allocated_timer(struct aspeed_gpio *gpio, 752 unsigned int offset) 753 { 754 if (WARN(gpio->offset_timer[offset] == 0, 755 "No timer allocated to offset %d\n", offset)) 756 return -EINVAL; 757 758 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0, 759 "No users recorded for timer %d\n", 760 gpio->offset_timer[offset])) 761 return -EINVAL; 762 763 gpio->timer_users[gpio->offset_timer[offset]]--; 764 gpio->offset_timer[offset] = 0; 765 766 return 0; 767 } 768 769 /* Call under gpio->lock */ 770 static inline bool timer_allocation_registered(struct aspeed_gpio *gpio, 771 unsigned int offset) 772 { 773 return gpio->offset_timer[offset] > 0; 774 } 775 776 /* Call under gpio->lock */ 777 static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset, 778 unsigned int timer) 779 { 780 /* Note: Debounce timer isn't under control of the command 781 * source registers, so no need to sync with the coprocessor 782 */ 783 gpio->config->llops->reg_bit_set(gpio, offset, reg_debounce_sel1, !!(timer & BIT(1))); 784 gpio->config->llops->reg_bit_set(gpio, offset, reg_debounce_sel2, !!(timer & BIT(0))); 785 } 786 787 static int enable_debounce(struct gpio_chip *chip, unsigned int offset, 788 unsigned long usecs) 789 { 790 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 791 u32 requested_cycles; 792 int rc; 793 int i; 794 795 if (!gpio->clk) 796 return -EINVAL; 797 798 rc = usecs_to_cycles(gpio, usecs, &requested_cycles); 799 if (rc < 0) { 800 dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n", 801 usecs, clk_get_rate(gpio->clk), rc); 802 return rc; 803 } 804 805 guard(raw_spinlock_irqsave)(&gpio->lock); 806 807 if (timer_allocation_registered(gpio, offset)) { 808 rc = unregister_allocated_timer(gpio, offset); 809 if (rc < 0) 810 return rc; 811 } 812 813 /* Try to find a timer already configured for the debounce period */ 814 for (i = 1; i < gpio->config->debounce_timers_num; i++) { 815 u32 cycles; 816 817 cycles = ioread32(gpio->base + gpio->config->debounce_timers_array[i]); 818 if (requested_cycles == cycles) 819 break; 820 } 821 822 if (i == gpio->config->debounce_timers_num) { 823 int j; 824 825 /* 826 * As there are no timers configured for the requested debounce 827 * period, find an unused timer instead 828 */ 829 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) { 830 if (gpio->timer_users[j] == 0) 831 break; 832 } 833 834 if (j == ARRAY_SIZE(gpio->timer_users)) { 835 dev_warn(chip->parent, 836 "Debounce timers exhausted, cannot debounce for period %luus\n", 837 usecs); 838 839 rc = -EPERM; 840 841 /* 842 * We already adjusted the accounting to remove @offset 843 * as a user of its previous timer, so also configure 844 * the hardware so @offset has timers disabled for 845 * consistency. 846 */ 847 configure_timer(gpio, offset, 0); 848 return rc; 849 } 850 851 i = j; 852 853 iowrite32(requested_cycles, gpio->base + gpio->config->debounce_timers_array[i]); 854 } 855 856 if (WARN(i == 0, "Cannot register index of disabled timer\n")) 857 return -EINVAL; 858 859 register_allocated_timer(gpio, offset, i); 860 configure_timer(gpio, offset, i); 861 862 return rc; 863 } 864 865 static int disable_debounce(struct gpio_chip *chip, unsigned int offset) 866 { 867 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 868 int rc; 869 870 guard(raw_spinlock_irqsave)(&gpio->lock); 871 872 rc = unregister_allocated_timer(gpio, offset); 873 if (!rc) 874 configure_timer(gpio, offset, 0); 875 876 return rc; 877 } 878 879 static int set_debounce(struct gpio_chip *chip, unsigned int offset, 880 unsigned long usecs) 881 { 882 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 883 884 if (!have_debounce(gpio, offset)) 885 return -ENOTSUPP; 886 887 if (usecs) 888 return enable_debounce(chip, offset, usecs); 889 890 return disable_debounce(chip, offset); 891 } 892 893 static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 894 unsigned long config) 895 { 896 unsigned long param = pinconf_to_config_param(config); 897 u32 arg = pinconf_to_config_argument(config); 898 899 if (param == PIN_CONFIG_INPUT_DEBOUNCE) 900 return set_debounce(chip, offset, arg); 901 else if (param == PIN_CONFIG_BIAS_DISABLE || 902 param == PIN_CONFIG_BIAS_PULL_DOWN || 903 param == PIN_CONFIG_DRIVE_STRENGTH) 904 return pinctrl_gpio_set_config(chip, offset, config); 905 else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN || 906 param == PIN_CONFIG_DRIVE_OPEN_SOURCE) 907 /* Return -ENOTSUPP to trigger emulation, as per datasheet */ 908 return -ENOTSUPP; 909 else if (param == PIN_CONFIG_PERSIST_STATE) 910 return aspeed_gpio_reset_tolerance(chip, offset, arg); 911 912 return -ENOTSUPP; 913 } 914 915 /** 916 * aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with 917 * the coprocessor for shared GPIO banks 918 * @ops: The callbacks 919 * @data: Pointer passed back to the callbacks 920 */ 921 int aspeed_gpio_copro_set_ops(const struct aspeed_gpio_copro_ops *ops, void *data) 922 { 923 copro_data = data; 924 copro_ops = ops; 925 926 return 0; 927 } 928 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_set_ops); 929 930 /** 931 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire 932 * bank gets marked and any access from the ARM will 933 * result in handshaking via callbacks. 934 * @desc: The GPIO to be marked 935 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space 936 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space 937 * @bit: If non-NULL, returns the bit number of the GPIO in the registers 938 */ 939 int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc, 940 u16 *vreg_offset, u16 *dreg_offset, u8 *bit) 941 { 942 struct gpio_chip *chip = gpiod_to_chip(desc); 943 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 944 int rc = 0, bindex, offset = gpiod_hwgpio(desc); 945 const struct aspeed_gpio_bank *bank = to_bank(offset); 946 947 if (!aspeed_gpio_support_copro(gpio)) 948 return -EOPNOTSUPP; 949 950 if (!gpio->cf_copro_bankmap) 951 gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL); 952 if (!gpio->cf_copro_bankmap) 953 return -ENOMEM; 954 if (offset < 0 || offset > gpio->chip.ngpio) 955 return -EINVAL; 956 bindex = offset >> 3; 957 958 guard(raw_spinlock_irqsave)(&gpio->lock); 959 960 /* Sanity check, this shouldn't happen */ 961 if (gpio->cf_copro_bankmap[bindex] == 0xff) 962 return -EIO; 963 964 gpio->cf_copro_bankmap[bindex]++; 965 966 /* Switch command source */ 967 if (gpio->cf_copro_bankmap[bindex] == 1) 968 aspeed_gpio_change_cmd_source(gpio, offset, 969 GPIO_CMDSRC_COLDFIRE); 970 971 if (vreg_offset) 972 *vreg_offset = bank->val_regs; 973 if (dreg_offset) 974 *dreg_offset = bank->rdata_reg; 975 if (bit) 976 *bit = GPIO_OFFSET(offset); 977 return rc; 978 } 979 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio); 980 981 /** 982 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor. 983 * @desc: The GPIO to be marked 984 */ 985 int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc) 986 { 987 struct gpio_chip *chip = gpiod_to_chip(desc); 988 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 989 int rc = 0, bindex, offset = gpiod_hwgpio(desc); 990 991 if (!aspeed_gpio_support_copro(gpio)) 992 return -EOPNOTSUPP; 993 994 if (!gpio->cf_copro_bankmap) 995 return -ENXIO; 996 997 if (offset < 0 || offset > gpio->chip.ngpio) 998 return -EINVAL; 999 bindex = offset >> 3; 1000 1001 guard(raw_spinlock_irqsave)(&gpio->lock); 1002 1003 /* Sanity check, this shouldn't happen */ 1004 if (gpio->cf_copro_bankmap[bindex] == 0) 1005 return -EIO; 1006 1007 gpio->cf_copro_bankmap[bindex]--; 1008 1009 /* Switch command source */ 1010 if (gpio->cf_copro_bankmap[bindex] == 0) 1011 aspeed_gpio_change_cmd_source(gpio, offset, 1012 GPIO_CMDSRC_ARM); 1013 1014 return rc; 1015 } 1016 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio); 1017 1018 static void aspeed_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p) 1019 { 1020 struct aspeed_gpio *gpio; 1021 int rc, offset; 1022 1023 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset); 1024 if (rc) 1025 return; 1026 1027 seq_puts(p, dev_name(gpio->dev)); 1028 } 1029 1030 static const struct irq_chip aspeed_gpio_irq_chip = { 1031 .irq_ack = aspeed_gpio_irq_ack, 1032 .irq_mask = aspeed_gpio_irq_mask, 1033 .irq_unmask = aspeed_gpio_irq_unmask, 1034 .irq_set_type = aspeed_gpio_set_type, 1035 .irq_print_chip = aspeed_gpio_irq_print_chip, 1036 .flags = IRQCHIP_IMMUTABLE, 1037 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1038 }; 1039 1040 static void aspeed_g4_reg_bit_set(struct aspeed_gpio *gpio, unsigned int offset, 1041 const enum aspeed_gpio_reg reg, bool val) 1042 { 1043 const struct aspeed_gpio_bank *bank = to_bank(offset); 1044 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg); 1045 u32 temp; 1046 1047 if (reg == reg_val) 1048 temp = gpio->dcache[GPIO_BANK(offset)]; 1049 else 1050 temp = ioread32(addr); 1051 1052 if (val) 1053 temp |= GPIO_BIT(offset); 1054 else 1055 temp &= ~GPIO_BIT(offset); 1056 1057 if (reg == reg_val) 1058 gpio->dcache[GPIO_BANK(offset)] = temp; 1059 iowrite32(temp, addr); 1060 } 1061 1062 static bool aspeed_g4_reg_bit_get(struct aspeed_gpio *gpio, unsigned int offset, 1063 const enum aspeed_gpio_reg reg) 1064 { 1065 const struct aspeed_gpio_bank *bank = to_bank(offset); 1066 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg); 1067 1068 return !!(ioread32(addr) & GPIO_BIT(offset)); 1069 } 1070 1071 static int aspeed_g4_reg_bank_get(struct aspeed_gpio *gpio, unsigned int offset, 1072 const enum aspeed_gpio_reg reg) 1073 { 1074 const struct aspeed_gpio_bank *bank = to_bank(offset); 1075 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg); 1076 1077 if (reg == reg_rdata || reg == reg_irq_status) 1078 return ioread32(addr); 1079 else 1080 return -EOPNOTSUPP; 1081 } 1082 1083 static void aspeed_g4_privilege_ctrl(struct aspeed_gpio *gpio, unsigned int offset, int cmdsrc) 1084 { 1085 /* 1086 * The command source register is only valid in bits 0, 8, 16, and 24, so we use 1087 * (offset & ~(0x7)) to ensure that reg_bits_set always targets a valid bit. 1088 */ 1089 /* Source 1 first to avoid illegal 11 combination */ 1090 aspeed_g4_reg_bit_set(gpio, offset & ~(0x7), reg_cmdsrc1, !!(cmdsrc & BIT(1))); 1091 /* Then Source 0 */ 1092 aspeed_g4_reg_bit_set(gpio, offset & ~(0x7), reg_cmdsrc0, !!(cmdsrc & BIT(0))); 1093 } 1094 1095 static void aspeed_g4_privilege_init(struct aspeed_gpio *gpio) 1096 { 1097 u32 i; 1098 1099 /* Switch all command sources to the ARM by default */ 1100 for (i = 0; i < DIV_ROUND_UP(gpio->chip.ngpio, 32); i++) { 1101 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 0, GPIO_CMDSRC_ARM); 1102 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 8, GPIO_CMDSRC_ARM); 1103 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 16, GPIO_CMDSRC_ARM); 1104 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 24, GPIO_CMDSRC_ARM); 1105 } 1106 } 1107 1108 static bool aspeed_g4_copro_request(struct aspeed_gpio *gpio, unsigned int offset) 1109 { 1110 if (!copro_ops || !gpio->cf_copro_bankmap) 1111 return false; 1112 if (!gpio->cf_copro_bankmap[offset >> 3]) 1113 return false; 1114 if (!copro_ops->request_access) 1115 return false; 1116 1117 /* Pause the coprocessor */ 1118 copro_ops->request_access(copro_data); 1119 1120 /* Change command source back to ARM */ 1121 aspeed_g4_privilege_ctrl(gpio, offset, GPIO_CMDSRC_ARM); 1122 1123 /* Update cache */ 1124 gpio->dcache[GPIO_BANK(offset)] = aspeed_g4_reg_bank_get(gpio, offset, reg_rdata); 1125 1126 return true; 1127 } 1128 1129 static void aspeed_g4_copro_release(struct aspeed_gpio *gpio, unsigned int offset) 1130 { 1131 if (!copro_ops || !gpio->cf_copro_bankmap) 1132 return; 1133 if (!gpio->cf_copro_bankmap[offset >> 3]) 1134 return; 1135 if (!copro_ops->release_access) 1136 return; 1137 1138 /* Change command source back to ColdFire */ 1139 aspeed_g4_privilege_ctrl(gpio, offset, GPIO_CMDSRC_COLDFIRE); 1140 1141 /* Restart the coprocessor */ 1142 copro_ops->release_access(copro_data); 1143 } 1144 1145 static const struct aspeed_gpio_llops aspeed_g4_llops = { 1146 .reg_bit_set = aspeed_g4_reg_bit_set, 1147 .reg_bit_get = aspeed_g4_reg_bit_get, 1148 .reg_bank_get = aspeed_g4_reg_bank_get, 1149 .privilege_ctrl = aspeed_g4_privilege_ctrl, 1150 .privilege_init = aspeed_g4_privilege_init, 1151 .copro_request = aspeed_g4_copro_request, 1152 .copro_release = aspeed_g4_copro_release, 1153 }; 1154 1155 static void aspeed_g7_reg_bit_set(struct aspeed_gpio *gpio, unsigned int offset, 1156 const enum aspeed_gpio_reg reg, bool val) 1157 { 1158 u32 mask = aspeed_gpio_g7_reg_mask(reg); 1159 void __iomem *addr = gpio->base + GPIO_G7_CTRL_REG_OFFSET(offset); 1160 u32 write_val; 1161 1162 if (mask) { 1163 write_val = (ioread32(addr) & ~(mask)) | field_prep(mask, val); 1164 iowrite32(write_val, addr); 1165 } 1166 } 1167 1168 static bool aspeed_g7_reg_bit_get(struct aspeed_gpio *gpio, unsigned int offset, 1169 const enum aspeed_gpio_reg reg) 1170 { 1171 u32 mask = aspeed_gpio_g7_reg_mask(reg); 1172 void __iomem *addr; 1173 1174 addr = gpio->base + GPIO_G7_CTRL_REG_OFFSET(offset); 1175 if (reg == reg_val) 1176 mask = GPIO_G7_CTRL_IN_DATA; 1177 1178 if (mask) 1179 return field_get(mask, ioread32(addr)); 1180 else 1181 return 0; 1182 } 1183 1184 static int aspeed_g7_reg_bank_get(struct aspeed_gpio *gpio, unsigned int offset, 1185 const enum aspeed_gpio_reg reg) 1186 { 1187 void __iomem *addr; 1188 1189 if (reg == reg_irq_status) { 1190 addr = gpio->base + GPIO_G7_IRQ_STS_OFFSET(offset >> 5); 1191 return ioread32(addr); 1192 } else { 1193 return -EOPNOTSUPP; 1194 } 1195 } 1196 1197 static const struct aspeed_gpio_llops aspeed_g7_llops = { 1198 .reg_bit_set = aspeed_g7_reg_bit_set, 1199 .reg_bit_get = aspeed_g7_reg_bit_get, 1200 .reg_bank_get = aspeed_g7_reg_bank_get, 1201 .privilege_ctrl = NULL, 1202 .privilege_init = NULL, 1203 .copro_request = NULL, 1204 .copro_release = NULL, 1205 }; 1206 1207 /* 1208 * Any banks not specified in a struct aspeed_bank_props array are assumed to 1209 * have the properties: 1210 * 1211 * { .input = 0xffffffff, .output = 0xffffffff } 1212 */ 1213 1214 static const struct aspeed_bank_props ast2400_bank_props[] = { 1215 /* input output */ 1216 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ 1217 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */ 1218 { }, 1219 }; 1220 1221 static const struct aspeed_gpio_config ast2400_config = 1222 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */ 1223 { 1224 .nr_gpios = 220, 1225 .props = ast2400_bank_props, 1226 .llops = &aspeed_g4_llops, 1227 .debounce_timers_array = debounce_timers, 1228 .debounce_timers_num = ARRAY_SIZE(debounce_timers), 1229 .require_dcache = true, 1230 }; 1231 1232 static const struct aspeed_bank_props ast2500_bank_props[] = { 1233 /* input output */ 1234 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ 1235 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */ 1236 { 7, 0x000000ff, 0x000000ff }, /* AC */ 1237 { }, 1238 }; 1239 1240 static const struct aspeed_gpio_config ast2500_config = 1241 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */ 1242 { 1243 .nr_gpios = 232, 1244 .props = ast2500_bank_props, 1245 .llops = &aspeed_g4_llops, 1246 .debounce_timers_array = debounce_timers, 1247 .debounce_timers_num = ARRAY_SIZE(debounce_timers), 1248 .require_dcache = true, 1249 }; 1250 1251 static const struct aspeed_bank_props ast2600_bank_props[] = { 1252 /* input output */ 1253 {4, 0xffffffff, 0x00ffffff}, /* Q/R/S/T */ 1254 {5, 0xffffffff, 0xffffff00}, /* U/V/W/X */ 1255 {6, 0x0000ffff, 0x0000ffff}, /* Y/Z */ 1256 { }, 1257 }; 1258 1259 static const struct aspeed_gpio_config ast2600_config = 1260 /* 1261 * ast2600 has two controllers one with 208 GPIOs and one with 36 GPIOs. 1262 * We expect ngpio being set in the device tree and this is a fallback 1263 * option. 1264 */ 1265 { 1266 .nr_gpios = 208, 1267 .props = ast2600_bank_props, 1268 .llops = &aspeed_g4_llops, 1269 .debounce_timers_array = debounce_timers, 1270 .debounce_timers_num = ARRAY_SIZE(debounce_timers), 1271 .require_dcache = true, 1272 }; 1273 1274 static const struct aspeed_bank_props ast2700_bank_props[] = { 1275 /* input output */ 1276 { 1, 0x0fffffff, 0x0fffffff }, /* E/F/G/H, 4-GPIO hole */ 1277 { 6, 0x00ffffff, 0x00ff0000 }, /* Y/Z/AA */ 1278 {}, 1279 }; 1280 1281 static const struct aspeed_gpio_config ast2700_config = 1282 /* 1283 * ast2700 has two controllers one with 212 GPIOs and one with 16 GPIOs. 1284 * 216 for simplicity, actual number is 212 (4-GPIO hole in GPIOH) 1285 * We expect ngpio being set in the device tree and this is a fallback 1286 * option. 1287 */ 1288 { 1289 .nr_gpios = 216, 1290 .props = ast2700_bank_props, 1291 .llops = &aspeed_g7_llops, 1292 .debounce_timers_array = g7_debounce_timers, 1293 .debounce_timers_num = ARRAY_SIZE(g7_debounce_timers), 1294 .require_dcache = false, 1295 }; 1296 1297 static const struct of_device_id aspeed_gpio_of_table[] = { 1298 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, }, 1299 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, }, 1300 { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, }, 1301 { .compatible = "aspeed,ast2700-gpio", .data = &ast2700_config, }, 1302 {} 1303 }; 1304 MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table); 1305 1306 static int aspeed_gpio_probe(struct platform_device *pdev) 1307 { 1308 const struct of_device_id *gpio_id; 1309 struct gpio_irq_chip *girq; 1310 struct aspeed_gpio *gpio; 1311 int rc, irq, i, banks, err; 1312 u32 ngpio; 1313 1314 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 1315 if (!gpio) 1316 return -ENOMEM; 1317 1318 gpio->base = devm_platform_ioremap_resource(pdev, 0); 1319 if (IS_ERR(gpio->base)) 1320 return PTR_ERR(gpio->base); 1321 1322 gpio->dev = &pdev->dev; 1323 1324 raw_spin_lock_init(&gpio->lock); 1325 1326 gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); 1327 if (!gpio_id) 1328 return -EINVAL; 1329 1330 gpio->clk = devm_clk_get_enabled(&pdev->dev, NULL); 1331 if (IS_ERR(gpio->clk)) { 1332 dev_warn(&pdev->dev, 1333 "Failed to get clock from devicetree, debouncing disabled\n"); 1334 gpio->clk = NULL; 1335 } 1336 1337 gpio->config = gpio_id->data; 1338 1339 if (!gpio->config->llops->reg_bit_set || !gpio->config->llops->reg_bit_get || 1340 !gpio->config->llops->reg_bank_get) 1341 return -EINVAL; 1342 1343 gpio->chip.parent = &pdev->dev; 1344 err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio); 1345 gpio->chip.ngpio = (u16) ngpio; 1346 if (err) 1347 gpio->chip.ngpio = gpio->config->nr_gpios; 1348 gpio->chip.direction_input = aspeed_gpio_dir_in; 1349 gpio->chip.direction_output = aspeed_gpio_dir_out; 1350 gpio->chip.get_direction = aspeed_gpio_get_direction; 1351 gpio->chip.request = aspeed_gpio_request; 1352 gpio->chip.free = aspeed_gpio_free; 1353 gpio->chip.get = aspeed_gpio_get; 1354 gpio->chip.set = aspeed_gpio_set; 1355 gpio->chip.set_config = aspeed_gpio_set_config; 1356 gpio->chip.label = dev_name(&pdev->dev); 1357 gpio->chip.base = -1; 1358 1359 if (gpio->config->require_dcache) { 1360 /* Allocate a cache of the output registers */ 1361 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); 1362 gpio->dcache = devm_kcalloc(&pdev->dev, banks, sizeof(u32), GFP_KERNEL); 1363 if (!gpio->dcache) 1364 return -ENOMEM; 1365 /* 1366 * Populate it with initial values read from the HW 1367 */ 1368 for (i = 0; i < banks; i++) 1369 gpio->dcache[i] = 1370 gpio->config->llops->reg_bank_get(gpio, (i << 5), reg_rdata); 1371 } 1372 1373 if (gpio->config->llops->privilege_init) 1374 gpio->config->llops->privilege_init(gpio); 1375 1376 /* Set up an irqchip */ 1377 irq = platform_get_irq(pdev, 0); 1378 if (irq < 0) 1379 return irq; 1380 gpio->irq = irq; 1381 girq = &gpio->chip.irq; 1382 gpio_irq_chip_set_chip(girq, &aspeed_gpio_irq_chip); 1383 1384 girq->parent_handler = aspeed_gpio_irq_handler; 1385 girq->num_parents = 1; 1386 girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), GFP_KERNEL); 1387 if (!girq->parents) 1388 return -ENOMEM; 1389 girq->parents[0] = gpio->irq; 1390 girq->default_type = IRQ_TYPE_NONE; 1391 girq->handler = handle_bad_irq; 1392 girq->init_valid_mask = aspeed_init_irq_valid_mask; 1393 1394 gpio->offset_timer = 1395 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL); 1396 if (!gpio->offset_timer) 1397 return -ENOMEM; 1398 1399 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); 1400 if (rc < 0) 1401 return rc; 1402 1403 return 0; 1404 } 1405 1406 static struct platform_driver aspeed_gpio_driver = { 1407 .probe = aspeed_gpio_probe, 1408 .driver = { 1409 .name = KBUILD_MODNAME, 1410 .of_match_table = aspeed_gpio_of_table, 1411 }, 1412 }; 1413 1414 module_platform_driver(aspeed_gpio_driver); 1415 1416 MODULE_DESCRIPTION("Aspeed GPIO Driver"); 1417 MODULE_LICENSE("GPL"); 1418