1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2019 American Megatrends International LLC. 4 * 5 * Author: Karthikeyan Mani <karthikeyanm@amiindia.co.in> 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/cleanup.h> 10 #include <linux/clk.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/hashtable.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/platform_device.h> 18 #include <linux/seq_file.h> 19 #include <linux/spinlock.h> 20 #include <linux/string.h> 21 22 #define SGPIO_G7_IRQ_STS_BASE 0x40 23 #define SGPIO_G7_IRQ_STS_OFFSET(x) (SGPIO_G7_IRQ_STS_BASE + (x) * 0x4) 24 #define SGPIO_G7_CTRL_REG_BASE 0x80 25 #define SGPIO_G7_CTRL_REG_OFFSET(x) (SGPIO_G7_CTRL_REG_BASE + (x) * 0x4) 26 #define SGPIO_G7_OUT_DATA BIT(0) 27 #define SGPIO_G7_PARALLEL_OUT_DATA BIT(1) 28 #define SGPIO_G7_IRQ_EN BIT(2) 29 #define SGPIO_G7_IRQ_TYPE0 BIT(3) 30 #define SGPIO_G7_IRQ_TYPE1 BIT(4) 31 #define SGPIO_G7_IRQ_TYPE2 BIT(5) 32 #define SGPIO_G7_RST_TOLERANCE BIT(6) 33 #define SGPIO_G7_INPUT_MASK BIT(9) 34 #define SGPIO_G7_HW_BYPASS_EN BIT(10) 35 #define SGPIO_G7_HW_IN_SEL BIT(11) 36 #define SGPIO_G7_IRQ_STS BIT(12) 37 #define SGPIO_G7_IN_DATA BIT(13) 38 #define SGPIO_G7_PARALLEL_IN_DATA BIT(14) 39 #define SGPIO_G7_SERIAL_OUT_SEL GENMASK(17, 16) 40 #define SGPIO_G7_PARALLEL_OUT_SEL GENMASK(19, 18) 41 #define SELECT_FROM_CSR 0 42 #define SELECT_FROM_PARALLEL_IN 1 43 #define SELECT_FROM_SERIAL_IN 2 44 45 #define ASPEED_SGPIO_G4_CFG_OFFSET 0x54 46 #define ASPEED_SGPIO_G7_CFG_OFFSET 0x0 47 48 #define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16) 49 #define ASPEED_SGPIO_ENABLE BIT(0) 50 #define ASPEED_SGPIO_PINS_SHIFT 6 51 52 struct aspeed_sgpio_pdata { 53 const u32 pin_mask; 54 const struct aspeed_sgpio_llops *llops; 55 const u32 cfg_offset; 56 }; 57 58 struct aspeed_sgpio { 59 struct gpio_chip chip; 60 struct device *dev; 61 struct clk *pclk; 62 raw_spinlock_t lock; 63 void __iomem *base; 64 int irq; 65 const struct aspeed_sgpio_pdata *pdata; 66 }; 67 68 struct aspeed_sgpio_bank { 69 u16 val_regs; 70 u16 rdata_reg; 71 u16 irq_regs; 72 u16 tolerance_regs; 73 }; 74 75 /* 76 * Note: The "value" register returns the input value when the GPIO is 77 * configured as an input. 78 * 79 * The "rdata" register returns the output value when the GPIO is 80 * configured as an output. 81 */ 82 static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = { 83 { 84 .val_regs = 0x0000, 85 .rdata_reg = 0x0070, 86 .irq_regs = 0x0004, 87 .tolerance_regs = 0x0018, 88 }, 89 { 90 .val_regs = 0x001C, 91 .rdata_reg = 0x0074, 92 .irq_regs = 0x0020, 93 .tolerance_regs = 0x0034, 94 }, 95 { 96 .val_regs = 0x0038, 97 .rdata_reg = 0x0078, 98 .irq_regs = 0x003C, 99 .tolerance_regs = 0x0050, 100 }, 101 { 102 .val_regs = 0x0090, 103 .rdata_reg = 0x007C, 104 .irq_regs = 0x0094, 105 .tolerance_regs = 0x00A8, 106 }, 107 }; 108 109 enum aspeed_sgpio_reg { 110 reg_val, 111 reg_rdata, 112 reg_irq_enable, 113 reg_irq_type0, 114 reg_irq_type1, 115 reg_irq_type2, 116 reg_irq_status, 117 reg_tolerance, 118 }; 119 120 struct aspeed_sgpio_llops { 121 void (*reg_bit_set)(struct aspeed_sgpio *gpio, unsigned int offset, 122 const enum aspeed_sgpio_reg reg, bool val); 123 bool (*reg_bit_get)(struct aspeed_sgpio *gpio, unsigned int offset, 124 const enum aspeed_sgpio_reg reg); 125 int (*reg_bank_get)(struct aspeed_sgpio *gpio, unsigned int offset, 126 const enum aspeed_sgpio_reg reg); 127 }; 128 129 #define GPIO_VAL_VALUE 0x00 130 #define GPIO_IRQ_ENABLE 0x00 131 #define GPIO_IRQ_TYPE0 0x04 132 #define GPIO_IRQ_TYPE1 0x08 133 #define GPIO_IRQ_TYPE2 0x0C 134 #define GPIO_IRQ_STATUS 0x10 135 136 static void __iomem *aspeed_sgpio_g4_bank_reg(struct aspeed_sgpio *gpio, 137 const struct aspeed_sgpio_bank *bank, 138 const enum aspeed_sgpio_reg reg) 139 { 140 switch (reg) { 141 case reg_val: 142 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; 143 case reg_rdata: 144 return gpio->base + bank->rdata_reg; 145 case reg_irq_enable: 146 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; 147 case reg_irq_type0: 148 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; 149 case reg_irq_type1: 150 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; 151 case reg_irq_type2: 152 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; 153 case reg_irq_status: 154 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; 155 case reg_tolerance: 156 return gpio->base + bank->tolerance_regs; 157 default: 158 /* acturally if code runs to here, it's an error case */ 159 BUG(); 160 } 161 } 162 163 static u32 aspeed_sgpio_g7_reg_mask(const enum aspeed_sgpio_reg reg) 164 { 165 switch (reg) { 166 case reg_val: 167 case reg_rdata: 168 return SGPIO_G7_OUT_DATA; 169 case reg_irq_enable: 170 return SGPIO_G7_IRQ_EN; 171 case reg_irq_type0: 172 return SGPIO_G7_IRQ_TYPE0; 173 case reg_irq_type1: 174 return SGPIO_G7_IRQ_TYPE1; 175 case reg_irq_type2: 176 return SGPIO_G7_IRQ_TYPE2; 177 case reg_irq_status: 178 return SGPIO_G7_IRQ_STS; 179 case reg_tolerance: 180 return SGPIO_G7_RST_TOLERANCE; 181 default: 182 WARN_ON_ONCE(1); 183 return 0; 184 } 185 } 186 187 #define GPIO_BANK(x) ((x) >> 6) 188 #define GPIO_OFFSET(x) ((x) & GENMASK(5, 0)) 189 #define GPIO_BIT(x) BIT(GPIO_OFFSET(x) >> 1) 190 191 static const struct aspeed_sgpio_bank *to_bank(unsigned int offset) 192 { 193 unsigned int bank; 194 195 bank = GPIO_BANK(offset); 196 197 WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks)); 198 return &aspeed_sgpio_banks[bank]; 199 } 200 201 static int aspeed_sgpio_init_valid_mask(struct gpio_chip *gc, 202 unsigned long *valid_mask, unsigned int ngpios) 203 { 204 bitmap_set(valid_mask, 0, ngpios); 205 return 0; 206 } 207 208 static void aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc, 209 unsigned long *valid_mask, unsigned int ngpios) 210 { 211 unsigned int i; 212 213 /* input GPIOs are even bits */ 214 for (i = 0; i < ngpios; i++) { 215 if (i % 2) 216 clear_bit(i, valid_mask); 217 } 218 } 219 220 static bool aspeed_sgpio_is_input(unsigned int offset) 221 { 222 return !(offset % 2); 223 } 224 225 static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset) 226 { 227 struct aspeed_sgpio *gpio = gpiochip_get_data(gc); 228 enum aspeed_sgpio_reg reg; 229 int rc = 0; 230 231 guard(raw_spinlock_irqsave)(&gpio->lock); 232 233 reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata; 234 rc = gpio->pdata->llops->reg_bit_get(gpio, offset, reg); 235 236 return rc; 237 } 238 239 static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val) 240 { 241 struct aspeed_sgpio *gpio = gpiochip_get_data(gc); 242 243 if (aspeed_sgpio_is_input(offset)) 244 return -EINVAL; 245 246 gpio->pdata->llops->reg_bit_set(gpio, offset, reg_val, val); 247 248 return 0; 249 } 250 251 static int aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val) 252 { 253 struct aspeed_sgpio *gpio = gpiochip_get_data(gc); 254 255 guard(raw_spinlock_irqsave)(&gpio->lock); 256 257 return sgpio_set_value(gc, offset, val); 258 } 259 260 static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset) 261 { 262 return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL; 263 } 264 265 static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val) 266 { 267 struct aspeed_sgpio *gpio = gpiochip_get_data(gc); 268 int rc; 269 270 /* No special action is required for setting the direction; we'll 271 * error-out in sgpio_set_value if this isn't an output GPIO */ 272 273 guard(raw_spinlock_irqsave)(&gpio->lock); 274 275 rc = sgpio_set_value(gc, offset, val); 276 277 return rc; 278 } 279 280 static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset) 281 { 282 return !!aspeed_sgpio_is_input(offset); 283 } 284 285 286 static void aspeed_sgpio_irq_ack(struct irq_data *d) 287 { 288 struct aspeed_sgpio *gpio = irq_data_get_irq_chip_data(d); 289 int offset = irqd_to_hwirq(d); 290 291 guard(raw_spinlock_irqsave)(&gpio->lock); 292 293 gpio->pdata->llops->reg_bit_set(gpio, offset, reg_irq_status, 1); 294 } 295 296 static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set) 297 { 298 struct aspeed_sgpio *gpio = irq_data_get_irq_chip_data(d); 299 int offset = irqd_to_hwirq(d); 300 301 /* Unmasking the IRQ */ 302 if (set) 303 gpiochip_enable_irq(&gpio->chip, offset); 304 scoped_guard(raw_spinlock_irqsave, &gpio->lock) 305 { 306 gpio->pdata->llops->reg_bit_set(gpio, offset, reg_irq_enable, 307 set); 308 } 309 310 /* Masking the IRQ */ 311 if (!set) 312 gpiochip_disable_irq(&gpio->chip, offset); 313 } 314 315 static void aspeed_sgpio_irq_mask(struct irq_data *d) 316 { 317 aspeed_sgpio_irq_set_mask(d, false); 318 } 319 320 static void aspeed_sgpio_irq_unmask(struct irq_data *d) 321 { 322 aspeed_sgpio_irq_set_mask(d, true); 323 } 324 325 static int aspeed_sgpio_set_type(struct irq_data *d, unsigned int type) 326 { 327 u32 type0 = 0; 328 u32 type1 = 0; 329 u32 type2 = 0; 330 irq_flow_handler_t handler; 331 struct aspeed_sgpio *gpio = irq_data_get_irq_chip_data(d); 332 int offset = irqd_to_hwirq(d); 333 334 switch (type & IRQ_TYPE_SENSE_MASK) { 335 case IRQ_TYPE_EDGE_BOTH: 336 type2 = 1; 337 fallthrough; 338 case IRQ_TYPE_EDGE_RISING: 339 type0 = 1; 340 fallthrough; 341 case IRQ_TYPE_EDGE_FALLING: 342 handler = handle_edge_irq; 343 break; 344 case IRQ_TYPE_LEVEL_HIGH: 345 type0 = 1; 346 fallthrough; 347 case IRQ_TYPE_LEVEL_LOW: 348 type1 = 1; 349 handler = handle_level_irq; 350 break; 351 default: 352 return -EINVAL; 353 } 354 355 scoped_guard(raw_spinlock_irqsave, &gpio->lock) { 356 gpio->pdata->llops->reg_bit_set(gpio, offset, reg_irq_type0, type0); 357 gpio->pdata->llops->reg_bit_set(gpio, offset, reg_irq_type1, type1); 358 gpio->pdata->llops->reg_bit_set(gpio, offset, reg_irq_type2, type2); 359 } 360 361 irq_set_handler_locked(d, handler); 362 363 return 0; 364 } 365 366 static void aspeed_sgpio_irq_handler(struct irq_desc *desc) 367 { 368 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 369 struct irq_chip *ic = irq_desc_get_chip(desc); 370 struct aspeed_sgpio *data = gpiochip_get_data(gc); 371 unsigned int i, p, banks; 372 unsigned long reg; 373 374 chained_irq_enter(ic, desc); 375 376 banks = DIV_ROUND_UP(gc->ngpio, 64); 377 for (i = 0; i < banks; i++) { 378 reg = data->pdata->llops->reg_bank_get(data, i << 6, reg_irq_status); 379 380 for_each_set_bit(p, ®, 32) 381 generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2); 382 } 383 384 chained_irq_exit(ic, desc); 385 } 386 387 static void aspeed_sgpio_irq_print_chip(struct irq_data *d, struct seq_file *p) 388 { 389 struct aspeed_sgpio *gpio = irq_data_get_irq_chip_data(d); 390 391 seq_puts(p, dev_name(gpio->dev)); 392 } 393 394 static const struct irq_chip aspeed_sgpio_irq_chip = { 395 .irq_ack = aspeed_sgpio_irq_ack, 396 .irq_mask = aspeed_sgpio_irq_mask, 397 .irq_unmask = aspeed_sgpio_irq_unmask, 398 .irq_set_type = aspeed_sgpio_set_type, 399 .irq_print_chip = aspeed_sgpio_irq_print_chip, 400 .flags = IRQCHIP_IMMUTABLE, 401 GPIOCHIP_IRQ_RESOURCE_HELPERS, 402 }; 403 404 static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio, 405 struct platform_device *pdev) 406 { 407 int rc, i; 408 struct gpio_irq_chip *irq; 409 410 rc = platform_get_irq(pdev, 0); 411 if (rc < 0) 412 return rc; 413 414 gpio->irq = rc; 415 416 /* Disable IRQ and clear Interrupt status registers for all SGPIO Pins. */ 417 for (i = 0; i < gpio->chip.ngpio; i += 2) { 418 /* disable irq enable bits */ 419 gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_enable, 0); 420 /* clear status bits */ 421 gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_status, 1); 422 } 423 424 irq = &gpio->chip.irq; 425 gpio_irq_chip_set_chip(irq, &aspeed_sgpio_irq_chip); 426 irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask; 427 irq->handler = handle_bad_irq; 428 irq->default_type = IRQ_TYPE_NONE; 429 irq->parent_handler = aspeed_sgpio_irq_handler; 430 irq->parent_handler_data = gpio; 431 irq->parents = &gpio->irq; 432 irq->num_parents = 1; 433 434 /* Apply default IRQ settings */ 435 for (i = 0; i < gpio->chip.ngpio; i += 2) { 436 /* set falling or level-low irq */ 437 gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_type0, 0); 438 /* trigger type is edge */ 439 gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_type1, 0); 440 /* single edge trigger */ 441 gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_type2, 0); 442 } 443 444 return 0; 445 } 446 447 static void aspeed_sgpio_g4_reg_bit_set(struct aspeed_sgpio *gpio, unsigned int offset, 448 const enum aspeed_sgpio_reg reg, bool val) 449 { 450 const struct aspeed_sgpio_bank *bank = to_bank(offset); 451 void __iomem *addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg); 452 u32 temp; 453 454 if (reg == reg_val) { 455 /* Since this is an output, read the cached value from rdata, then update val. */ 456 addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg_rdata); 457 temp = ioread32(addr); 458 if (val) 459 temp |= GPIO_BIT(offset); 460 else 461 temp &= ~GPIO_BIT(offset); 462 463 addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg_val); 464 iowrite32(temp, addr); 465 } else if (reg == reg_irq_status) { 466 if (val) 467 iowrite32(GPIO_BIT(offset), addr); 468 } else { 469 /* When setting other registers, we read from the register itself */ 470 temp = ioread32(addr); 471 if (val) 472 temp |= GPIO_BIT(offset); 473 else 474 temp &= ~GPIO_BIT(offset); 475 iowrite32(temp, addr); 476 } 477 } 478 479 static bool aspeed_sgpio_g4_reg_bit_get(struct aspeed_sgpio *gpio, unsigned int offset, 480 const enum aspeed_sgpio_reg reg) 481 { 482 const struct aspeed_sgpio_bank *bank = to_bank(offset); 483 void __iomem *addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg); 484 485 return !!(ioread32(addr) & GPIO_BIT(offset)); 486 } 487 488 static int aspeed_sgpio_g4_reg_bank_get(struct aspeed_sgpio *gpio, unsigned int offset, 489 const enum aspeed_sgpio_reg reg) 490 { 491 const struct aspeed_sgpio_bank *bank = to_bank(offset); 492 void __iomem *addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg); 493 494 if (reg == reg_irq_status) 495 return ioread32(addr); 496 else 497 return -EOPNOTSUPP; 498 } 499 500 static const struct aspeed_sgpio_llops aspeed_sgpio_g4_llops = { 501 .reg_bit_set = aspeed_sgpio_g4_reg_bit_set, 502 .reg_bit_get = aspeed_sgpio_g4_reg_bit_get, 503 .reg_bank_get = aspeed_sgpio_g4_reg_bank_get, 504 }; 505 506 static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = { 507 .pin_mask = GENMASK(9, 6), 508 .llops = &aspeed_sgpio_g4_llops, 509 .cfg_offset = ASPEED_SGPIO_G4_CFG_OFFSET, 510 }; 511 512 static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip, 513 unsigned int offset, bool enable) 514 { 515 struct aspeed_sgpio *gpio = gpiochip_get_data(chip); 516 517 guard(raw_spinlock_irqsave)(&gpio->lock); 518 519 gpio->pdata->llops->reg_bit_set(gpio, offset, reg_tolerance, enable); 520 521 return 0; 522 } 523 524 static int aspeed_sgpio_set_config(struct gpio_chip *chip, unsigned int offset, 525 unsigned long config) 526 { 527 unsigned long param = pinconf_to_config_param(config); 528 u32 arg = pinconf_to_config_argument(config); 529 530 if (param == PIN_CONFIG_PERSIST_STATE) 531 return aspeed_sgpio_reset_tolerance(chip, offset, arg); 532 533 return -ENOTSUPP; 534 } 535 536 static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata = { 537 .pin_mask = GENMASK(10, 6), 538 .llops = &aspeed_sgpio_g4_llops, 539 .cfg_offset = ASPEED_SGPIO_G4_CFG_OFFSET, 540 }; 541 542 static void aspeed_sgpio_g7_reg_bit_set(struct aspeed_sgpio *gpio, unsigned int offset, 543 const enum aspeed_sgpio_reg reg, bool val) 544 { 545 u32 mask = aspeed_sgpio_g7_reg_mask(reg); 546 void __iomem *addr = gpio->base + SGPIO_G7_CTRL_REG_OFFSET(offset >> 1); 547 u32 write_val; 548 549 if (mask) { 550 write_val = (ioread32(addr) & ~(mask)) | field_prep(mask, val); 551 iowrite32(write_val, addr); 552 } 553 } 554 555 static bool aspeed_sgpio_g7_reg_bit_get(struct aspeed_sgpio *gpio, unsigned int offset, 556 const enum aspeed_sgpio_reg reg) 557 { 558 u32 mask = aspeed_sgpio_g7_reg_mask(reg); 559 void __iomem *addr; 560 561 addr = gpio->base + SGPIO_G7_CTRL_REG_OFFSET(offset >> 1); 562 if (reg == reg_val) 563 mask = SGPIO_G7_IN_DATA; 564 565 if (mask) 566 return field_get(mask, ioread32(addr)); 567 else 568 return 0; 569 } 570 571 static int aspeed_sgpio_g7_reg_bank_get(struct aspeed_sgpio *gpio, unsigned int offset, 572 const enum aspeed_sgpio_reg reg) 573 { 574 void __iomem *addr; 575 576 if (reg == reg_irq_status) { 577 addr = gpio->base + SGPIO_G7_IRQ_STS_OFFSET(offset >> 6); 578 return ioread32(addr); 579 } else { 580 return -EOPNOTSUPP; 581 } 582 } 583 584 static const struct aspeed_sgpio_llops aspeed_sgpio_g7_llops = { 585 .reg_bit_set = aspeed_sgpio_g7_reg_bit_set, 586 .reg_bit_get = aspeed_sgpio_g7_reg_bit_get, 587 .reg_bank_get = aspeed_sgpio_g7_reg_bank_get, 588 }; 589 590 static const struct aspeed_sgpio_pdata ast2700_sgpiom_pdata = { 591 .pin_mask = GENMASK(11, 6), 592 .llops = &aspeed_sgpio_g7_llops, 593 .cfg_offset = ASPEED_SGPIO_G7_CFG_OFFSET, 594 }; 595 596 static const struct of_device_id aspeed_sgpio_of_table[] = { 597 { .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata, }, 598 { .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata, }, 599 { .compatible = "aspeed,ast2600-sgpiom", .data = &ast2600_sgpiom_pdata, }, 600 { .compatible = "aspeed,ast2700-sgpiom", .data = &ast2700_sgpiom_pdata, }, 601 {} 602 }; 603 604 MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table); 605 606 static int aspeed_sgpio_probe(struct platform_device *pdev) 607 { 608 u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask; 609 struct aspeed_sgpio *gpio; 610 unsigned long apb_freq; 611 int rc; 612 613 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 614 if (!gpio) 615 return -ENOMEM; 616 617 gpio->base = devm_platform_ioremap_resource(pdev, 0); 618 if (IS_ERR(gpio->base)) 619 return PTR_ERR(gpio->base); 620 621 gpio->dev = &pdev->dev; 622 623 gpio->pdata = device_get_match_data(&pdev->dev); 624 if (!gpio->pdata) 625 return -EINVAL; 626 627 pin_mask = gpio->pdata->pin_mask; 628 rc = device_property_read_u32(&pdev->dev, "ngpios", &nr_gpios); 629 if (rc < 0) { 630 dev_err(&pdev->dev, "Could not read ngpios property\n"); 631 return -EINVAL; 632 } else if (nr_gpios % 8) { 633 dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n", 634 nr_gpios); 635 return -EINVAL; 636 } 637 638 rc = device_property_read_u32(&pdev->dev, "bus-frequency", &sgpio_freq); 639 if (rc < 0) { 640 dev_err(&pdev->dev, "Could not read bus-frequency property\n"); 641 return -EINVAL; 642 } 643 644 gpio->pclk = devm_clk_get(&pdev->dev, NULL); 645 if (IS_ERR(gpio->pclk)) { 646 dev_err(&pdev->dev, "devm_clk_get failed\n"); 647 return PTR_ERR(gpio->pclk); 648 } 649 650 apb_freq = clk_get_rate(gpio->pclk); 651 652 /* 653 * From the datasheet, 654 * SGPIO period = 1/PCLK * 2 * (GPIO254[31:16] + 1) 655 * period = 2 * (GPIO254[31:16] + 1) / PCLK 656 * frequency = 1 / (2 * (GPIO254[31:16] + 1) / PCLK) 657 * frequency = PCLK / (2 * (GPIO254[31:16] + 1)) 658 * frequency * 2 * (GPIO254[31:16] + 1) = PCLK 659 * GPIO254[31:16] = PCLK / (frequency * 2) - 1 660 */ 661 if (sgpio_freq == 0) 662 return -EINVAL; 663 664 sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1; 665 666 if (sgpio_clk_div > (1 << 16) - 1) 667 return -EINVAL; 668 669 gpio_cnt_regval = ((nr_gpios / 8) << ASPEED_SGPIO_PINS_SHIFT) & pin_mask; 670 iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) | gpio_cnt_regval | 671 ASPEED_SGPIO_ENABLE, gpio->base + gpio->pdata->cfg_offset); 672 673 raw_spin_lock_init(&gpio->lock); 674 675 gpio->chip.parent = &pdev->dev; 676 gpio->chip.ngpio = nr_gpios * 2; 677 gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask; 678 gpio->chip.direction_input = aspeed_sgpio_dir_in; 679 gpio->chip.direction_output = aspeed_sgpio_dir_out; 680 gpio->chip.get_direction = aspeed_sgpio_get_direction; 681 gpio->chip.request = NULL; 682 gpio->chip.free = NULL; 683 gpio->chip.get = aspeed_sgpio_get; 684 gpio->chip.set = aspeed_sgpio_set; 685 gpio->chip.set_config = aspeed_sgpio_set_config; 686 gpio->chip.label = dev_name(&pdev->dev); 687 gpio->chip.base = -1; 688 689 aspeed_sgpio_setup_irqs(gpio, pdev); 690 691 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); 692 if (rc < 0) 693 return rc; 694 695 return 0; 696 } 697 698 static struct platform_driver aspeed_sgpio_driver = { 699 .probe = aspeed_sgpio_probe, 700 .driver = { 701 .name = KBUILD_MODNAME, 702 .of_match_table = aspeed_sgpio_of_table, 703 }, 704 }; 705 706 module_platform_driver(aspeed_sgpio_driver); 707 MODULE_DESCRIPTION("Aspeed Serial GPIO Driver"); 708