1 // SPDX-License-Identifier: GPL-2.0+ 2 3 /* 4 * GPIO driver for the AMD G series FCH (eg. GX-412TC) 5 * 6 * Copyright (C) 2018 metux IT consult 7 * Author: Enrico Weigelt, metux IT consult <info@metux.net> 8 * 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/platform_data/gpio/gpio-amd-fch.h> 19 #include <linux/spinlock.h> 20 21 #define AMD_FCH_MMIO_BASE 0xFED80000 22 #define AMD_FCH_GPIO_BANK0_BASE 0x1500 23 #define AMD_FCH_GPIO_SIZE 0x0300 24 25 #define AMD_FCH_GPIO_FLAG_DIRECTION BIT(23) 26 #define AMD_FCH_GPIO_FLAG_WRITE BIT(22) 27 #define AMD_FCH_GPIO_FLAG_READ BIT(16) 28 29 static const struct resource amd_fch_gpio_iores = 30 DEFINE_RES_MEM_NAMED( 31 AMD_FCH_MMIO_BASE + AMD_FCH_GPIO_BANK0_BASE, 32 AMD_FCH_GPIO_SIZE, 33 "amd-fch-gpio-iomem"); 34 35 struct amd_fch_gpio_priv { 36 struct gpio_chip gc; 37 void __iomem *base; 38 struct amd_fch_gpio_pdata *pdata; 39 spinlock_t lock; 40 }; 41 42 static void __iomem *amd_fch_gpio_addr(struct amd_fch_gpio_priv *priv, 43 unsigned int gpio) 44 { 45 return priv->base + priv->pdata->gpio_reg[gpio]*sizeof(u32); 46 } 47 48 static int amd_fch_gpio_direction_input(struct gpio_chip *gc, 49 unsigned int offset) 50 { 51 struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc); 52 void __iomem *ptr = amd_fch_gpio_addr(priv, offset); 53 54 guard(spinlock_irqsave)(&priv->lock); 55 writel_relaxed(readl_relaxed(ptr) & ~AMD_FCH_GPIO_FLAG_DIRECTION, ptr); 56 57 return 0; 58 } 59 60 static int amd_fch_gpio_direction_output(struct gpio_chip *gc, 61 unsigned int gpio, int value) 62 { 63 struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc); 64 void __iomem *ptr = amd_fch_gpio_addr(priv, gpio); 65 u32 val; 66 67 guard(spinlock_irqsave)(&priv->lock); 68 69 val = readl_relaxed(ptr); 70 if (value) 71 val |= AMD_FCH_GPIO_FLAG_WRITE; 72 else 73 val &= ~AMD_FCH_GPIO_FLAG_WRITE; 74 75 writel_relaxed(val | AMD_FCH_GPIO_FLAG_DIRECTION, ptr); 76 77 return 0; 78 } 79 80 static int amd_fch_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio) 81 { 82 int ret; 83 struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc); 84 void __iomem *ptr = amd_fch_gpio_addr(priv, gpio); 85 86 guard(spinlock_irqsave)(&priv->lock); 87 ret = (readl_relaxed(ptr) & AMD_FCH_GPIO_FLAG_DIRECTION); 88 89 return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 90 } 91 92 static int amd_fch_gpio_set(struct gpio_chip *gc, unsigned int gpio, int value) 93 { 94 struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc); 95 void __iomem *ptr = amd_fch_gpio_addr(priv, gpio); 96 u32 mask; 97 98 guard(spinlock_irqsave)(&priv->lock); 99 100 mask = readl_relaxed(ptr); 101 if (value) 102 mask |= AMD_FCH_GPIO_FLAG_WRITE; 103 else 104 mask &= ~AMD_FCH_GPIO_FLAG_WRITE; 105 writel_relaxed(mask, ptr); 106 107 return 0; 108 } 109 110 static int amd_fch_gpio_get(struct gpio_chip *gc, 111 unsigned int offset) 112 { 113 u32 val; 114 struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc); 115 void __iomem *ptr = amd_fch_gpio_addr(priv, offset); 116 117 guard(spinlock_irqsave)(&priv->lock); 118 val = readl_relaxed(ptr); 119 120 return FIELD_GET(AMD_FCH_GPIO_FLAG_READ, val); 121 } 122 123 static int amd_fch_gpio_request(struct gpio_chip *chip, 124 unsigned int gpio_pin) 125 { 126 return 0; 127 } 128 129 static int amd_fch_gpio_probe(struct platform_device *pdev) 130 { 131 struct amd_fch_gpio_priv *priv; 132 struct amd_fch_gpio_pdata *pdata; 133 134 pdata = dev_get_platdata(&pdev->dev); 135 if (!pdata) { 136 dev_err(&pdev->dev, "no platform_data\n"); 137 return -ENOENT; 138 } 139 140 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 141 if (!priv) 142 return -ENOMEM; 143 144 priv->pdata = pdata; 145 146 priv->gc.owner = THIS_MODULE; 147 priv->gc.parent = &pdev->dev; 148 priv->gc.label = dev_name(&pdev->dev); 149 priv->gc.ngpio = priv->pdata->gpio_num; 150 priv->gc.names = priv->pdata->gpio_names; 151 priv->gc.base = -1; 152 priv->gc.request = amd_fch_gpio_request; 153 priv->gc.direction_input = amd_fch_gpio_direction_input; 154 priv->gc.direction_output = amd_fch_gpio_direction_output; 155 priv->gc.get_direction = amd_fch_gpio_get_direction; 156 priv->gc.get = amd_fch_gpio_get; 157 priv->gc.set = amd_fch_gpio_set; 158 159 spin_lock_init(&priv->lock); 160 161 priv->base = devm_ioremap_resource(&pdev->dev, &amd_fch_gpio_iores); 162 if (IS_ERR(priv->base)) 163 return PTR_ERR(priv->base); 164 165 platform_set_drvdata(pdev, priv); 166 167 return devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv); 168 } 169 170 static struct platform_driver amd_fch_gpio_driver = { 171 .driver = { 172 .name = AMD_FCH_GPIO_DRIVER_NAME, 173 }, 174 .probe = amd_fch_gpio_probe, 175 }; 176 177 module_platform_driver(amd_fch_gpio_driver); 178 179 MODULE_AUTHOR("Enrico Weigelt, metux IT consult <info@metux.net>"); 180 MODULE_DESCRIPTION("AMD G-series FCH GPIO driver"); 181 MODULE_LICENSE("GPL"); 182 MODULE_ALIAS("platform:" AMD_FCH_GPIO_DRIVER_NAME); 183