1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2011-2012 Avionic Design GmbH 4 */ 5 6 #include <linux/cleanup.h> 7 #include <linux/gpio/driver.h> 8 #include <linux/i2c.h> 9 #include <linux/interrupt.h> 10 #include <linux/module.h> 11 #include <linux/mutex.h> 12 #include <linux/property.h> 13 #include <linux/seq_file.h> 14 #include <linux/slab.h> 15 16 #define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift) 17 #define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift) 18 #define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift) 19 #define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift) 20 #define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift) 21 22 struct adnp { 23 struct i2c_client *client; 24 struct gpio_chip gpio; 25 unsigned int reg_shift; 26 27 struct mutex i2c_lock; 28 struct mutex irq_lock; 29 30 u8 *irq_enable; 31 u8 *irq_level; 32 u8 *irq_rise; 33 u8 *irq_fall; 34 u8 *irq_high; 35 u8 *irq_low; 36 }; 37 38 static int adnp_read(struct adnp *adnp, unsigned offset, uint8_t *value) 39 { 40 int err; 41 42 err = i2c_smbus_read_byte_data(adnp->client, offset); 43 if (err < 0) { 44 dev_err(adnp->gpio.parent, "%s failed: %d\n", 45 "i2c_smbus_read_byte_data()", err); 46 return err; 47 } 48 49 *value = err; 50 return 0; 51 } 52 53 static int adnp_write(struct adnp *adnp, unsigned offset, uint8_t value) 54 { 55 int err; 56 57 err = i2c_smbus_write_byte_data(adnp->client, offset, value); 58 if (err < 0) { 59 dev_err(adnp->gpio.parent, "%s failed: %d\n", 60 "i2c_smbus_write_byte_data()", err); 61 return err; 62 } 63 64 return 0; 65 } 66 67 static int adnp_gpio_get(struct gpio_chip *chip, unsigned offset) 68 { 69 struct adnp *adnp = gpiochip_get_data(chip); 70 unsigned int reg = offset >> adnp->reg_shift; 71 unsigned int pos = offset & 7; 72 u8 value; 73 int err; 74 75 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &value); 76 if (err < 0) 77 return err; 78 79 return (value & BIT(pos)) ? 1 : 0; 80 } 81 82 static int __adnp_gpio_set(struct adnp *adnp, unsigned int offset, int value) 83 { 84 unsigned int reg = offset >> adnp->reg_shift; 85 unsigned int pos = offset & 7; 86 int err; 87 u8 val; 88 89 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val); 90 if (err < 0) 91 return err; 92 93 if (value) 94 val |= BIT(pos); 95 else 96 val &= ~BIT(pos); 97 98 return adnp_write(adnp, GPIO_PLR(adnp) + reg, val); 99 } 100 101 static int adnp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 102 { 103 struct adnp *adnp = gpiochip_get_data(chip); 104 105 guard(mutex)(&adnp->i2c_lock); 106 107 return __adnp_gpio_set(adnp, offset, value); 108 } 109 110 static int adnp_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 111 { 112 struct adnp *adnp = gpiochip_get_data(chip); 113 unsigned int reg = offset >> adnp->reg_shift; 114 unsigned int pos = offset & 7; 115 u8 value; 116 int err; 117 118 guard(mutex)(&adnp->i2c_lock); 119 120 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value); 121 if (err < 0) 122 return err; 123 124 value &= ~BIT(pos); 125 126 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value); 127 if (err < 0) 128 return err; 129 130 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value); 131 if (err < 0) 132 return err; 133 134 if (value & BIT(pos)) 135 return -EPERM; 136 137 return 0; 138 } 139 140 static int adnp_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 141 int value) 142 { 143 struct adnp *adnp = gpiochip_get_data(chip); 144 unsigned int reg = offset >> adnp->reg_shift; 145 unsigned int pos = offset & 7; 146 int err; 147 u8 val; 148 149 guard(mutex)(&adnp->i2c_lock); 150 151 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val); 152 if (err < 0) 153 return err; 154 155 val |= BIT(pos); 156 157 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val); 158 if (err < 0) 159 return err; 160 161 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val); 162 if (err < 0) 163 return err; 164 165 if (!(val & BIT(pos))) 166 return -EPERM; 167 168 __adnp_gpio_set(adnp, offset, value); 169 170 return 0; 171 } 172 173 static void adnp_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 174 { 175 struct adnp *adnp = gpiochip_get_data(chip); 176 unsigned int num_regs = 1 << adnp->reg_shift, i, j; 177 int err; 178 179 for (i = 0; i < num_regs; i++) { 180 u8 ddr = 0, plr = 0, ier = 0, isr = 0; 181 182 scoped_guard(mutex, &adnp->i2c_lock) { 183 err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr); 184 if (err < 0) 185 return; 186 187 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr); 188 if (err < 0) 189 return; 190 191 err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier); 192 if (err < 0) 193 return; 194 195 err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr); 196 if (err < 0) 197 return; 198 199 } 200 201 for (j = 0; j < 8; j++) { 202 unsigned int bit = (i << adnp->reg_shift) + j; 203 const char *direction = "input "; 204 const char *level = "low "; 205 const char *interrupt = "disabled"; 206 const char *pending = ""; 207 208 if (ddr & BIT(j)) 209 direction = "output"; 210 211 if (plr & BIT(j)) 212 level = "high"; 213 214 if (ier & BIT(j)) 215 interrupt = "enabled "; 216 217 if (isr & BIT(j)) 218 pending = "pending"; 219 220 seq_printf(s, "%2u: %s %s IRQ %s %s\n", bit, 221 direction, level, interrupt, pending); 222 } 223 } 224 } 225 226 static irqreturn_t adnp_irq(int irq, void *data) 227 { 228 struct adnp *adnp = data; 229 unsigned int num_regs, i; 230 231 num_regs = 1 << adnp->reg_shift; 232 233 for (i = 0; i < num_regs; i++) { 234 unsigned int base = i << adnp->reg_shift, bit; 235 u8 changed, level = 0, isr = 0, ier = 0; 236 unsigned long pending; 237 int err; 238 239 { 240 guard(mutex)(&adnp->i2c_lock); 241 242 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level); 243 if (err < 0) 244 continue; 245 246 err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr); 247 if (err < 0) 248 continue; 249 250 err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier); 251 if (err < 0) 252 continue; 253 } 254 255 /* determine pins that changed levels */ 256 changed = level ^ adnp->irq_level[i]; 257 258 /* compute edge-triggered interrupts */ 259 pending = changed & ((adnp->irq_fall[i] & ~level) | 260 (adnp->irq_rise[i] & level)); 261 262 /* add in level-triggered interrupts */ 263 pending |= (adnp->irq_high[i] & level) | 264 (adnp->irq_low[i] & ~level); 265 266 /* mask out non-pending and disabled interrupts */ 267 pending &= isr & ier; 268 269 for_each_set_bit(bit, &pending, 8) { 270 unsigned int child_irq; 271 child_irq = irq_find_mapping(adnp->gpio.irq.domain, 272 base + bit); 273 handle_nested_irq(child_irq); 274 } 275 } 276 277 return IRQ_HANDLED; 278 } 279 280 static void adnp_irq_mask(struct irq_data *d) 281 { 282 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 283 struct adnp *adnp = gpiochip_get_data(gc); 284 unsigned int reg = d->hwirq >> adnp->reg_shift; 285 unsigned int pos = d->hwirq & 7; 286 287 adnp->irq_enable[reg] &= ~BIT(pos); 288 gpiochip_disable_irq(gc, irqd_to_hwirq(d)); 289 } 290 291 static void adnp_irq_unmask(struct irq_data *d) 292 { 293 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 294 struct adnp *adnp = gpiochip_get_data(gc); 295 unsigned int reg = d->hwirq >> adnp->reg_shift; 296 unsigned int pos = d->hwirq & 7; 297 298 gpiochip_enable_irq(gc, irqd_to_hwirq(d)); 299 adnp->irq_enable[reg] |= BIT(pos); 300 } 301 302 static int adnp_irq_set_type(struct irq_data *d, unsigned int type) 303 { 304 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 305 struct adnp *adnp = gpiochip_get_data(gc); 306 unsigned int reg = d->hwirq >> adnp->reg_shift; 307 unsigned int pos = d->hwirq & 7; 308 309 if (type & IRQ_TYPE_EDGE_RISING) 310 adnp->irq_rise[reg] |= BIT(pos); 311 else 312 adnp->irq_rise[reg] &= ~BIT(pos); 313 314 if (type & IRQ_TYPE_EDGE_FALLING) 315 adnp->irq_fall[reg] |= BIT(pos); 316 else 317 adnp->irq_fall[reg] &= ~BIT(pos); 318 319 if (type & IRQ_TYPE_LEVEL_HIGH) 320 adnp->irq_high[reg] |= BIT(pos); 321 else 322 adnp->irq_high[reg] &= ~BIT(pos); 323 324 if (type & IRQ_TYPE_LEVEL_LOW) 325 adnp->irq_low[reg] |= BIT(pos); 326 else 327 adnp->irq_low[reg] &= ~BIT(pos); 328 329 return 0; 330 } 331 332 static void adnp_irq_bus_lock(struct irq_data *d) 333 { 334 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 335 struct adnp *adnp = gpiochip_get_data(gc); 336 337 mutex_lock(&adnp->irq_lock); 338 } 339 340 static void adnp_irq_bus_unlock(struct irq_data *d) 341 { 342 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 343 struct adnp *adnp = gpiochip_get_data(gc); 344 unsigned int num_regs = 1 << adnp->reg_shift, i; 345 346 scoped_guard(mutex, &adnp->i2c_lock) { 347 for (i = 0; i < num_regs; i++) 348 adnp_write(adnp, GPIO_IER(adnp) + i, 349 adnp->irq_enable[i]); 350 } 351 352 mutex_unlock(&adnp->irq_lock); 353 } 354 355 static const struct irq_chip adnp_irq_chip = { 356 .name = "gpio-adnp", 357 .irq_mask = adnp_irq_mask, 358 .irq_unmask = adnp_irq_unmask, 359 .irq_set_type = adnp_irq_set_type, 360 .irq_bus_lock = adnp_irq_bus_lock, 361 .irq_bus_sync_unlock = adnp_irq_bus_unlock, 362 .flags = IRQCHIP_IMMUTABLE, 363 GPIOCHIP_IRQ_RESOURCE_HELPERS, 364 }; 365 366 static int adnp_irq_setup(struct adnp *adnp) 367 { 368 unsigned int num_regs = 1 << adnp->reg_shift, i; 369 struct gpio_chip *chip = &adnp->gpio; 370 int err; 371 372 mutex_init(&adnp->irq_lock); 373 374 /* 375 * Allocate memory to keep track of the current level and trigger 376 * modes of the interrupts. To avoid multiple allocations, a single 377 * large buffer is allocated and pointers are setup to point at the 378 * corresponding offsets. For consistency, the layout of the buffer 379 * is chosen to match the register layout of the hardware in that 380 * each segment contains the corresponding bits for all interrupts. 381 */ 382 adnp->irq_enable = devm_kcalloc(chip->parent, num_regs, 6, 383 GFP_KERNEL); 384 if (!adnp->irq_enable) 385 return -ENOMEM; 386 387 adnp->irq_level = adnp->irq_enable + (num_regs * 1); 388 adnp->irq_rise = adnp->irq_enable + (num_regs * 2); 389 adnp->irq_fall = adnp->irq_enable + (num_regs * 3); 390 adnp->irq_high = adnp->irq_enable + (num_regs * 4); 391 adnp->irq_low = adnp->irq_enable + (num_regs * 5); 392 393 for (i = 0; i < num_regs; i++) { 394 /* 395 * Read the initial level of all pins to allow the emulation 396 * of edge triggered interrupts. 397 */ 398 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &adnp->irq_level[i]); 399 if (err < 0) 400 return err; 401 402 /* disable all interrupts */ 403 err = adnp_write(adnp, GPIO_IER(adnp) + i, 0); 404 if (err < 0) 405 return err; 406 407 adnp->irq_enable[i] = 0x00; 408 } 409 410 err = devm_request_threaded_irq(chip->parent, adnp->client->irq, 411 NULL, adnp_irq, 412 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 413 dev_name(chip->parent), adnp); 414 if (err != 0) { 415 dev_err(chip->parent, "can't request IRQ#%d: %d\n", 416 adnp->client->irq, err); 417 return err; 418 } 419 420 return 0; 421 } 422 423 static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios, 424 bool is_irq_controller) 425 { 426 struct gpio_chip *chip = &adnp->gpio; 427 int err; 428 429 adnp->reg_shift = get_count_order(num_gpios) - 3; 430 431 chip->direction_input = adnp_gpio_direction_input; 432 chip->direction_output = adnp_gpio_direction_output; 433 chip->get = adnp_gpio_get; 434 chip->set = adnp_gpio_set; 435 chip->can_sleep = true; 436 437 if (IS_ENABLED(CONFIG_DEBUG_FS)) 438 chip->dbg_show = adnp_gpio_dbg_show; 439 440 chip->base = -1; 441 chip->ngpio = num_gpios; 442 chip->label = adnp->client->name; 443 chip->parent = &adnp->client->dev; 444 chip->owner = THIS_MODULE; 445 446 if (is_irq_controller) { 447 struct gpio_irq_chip *girq; 448 449 err = adnp_irq_setup(adnp); 450 if (err) 451 return err; 452 453 girq = &chip->irq; 454 gpio_irq_chip_set_chip(girq, &adnp_irq_chip); 455 456 /* This will let us handle the parent IRQ in the driver */ 457 girq->parent_handler = NULL; 458 girq->num_parents = 0; 459 girq->parents = NULL; 460 girq->default_type = IRQ_TYPE_NONE; 461 girq->handler = handle_simple_irq; 462 girq->threaded = true; 463 } 464 465 err = devm_gpiochip_add_data(&adnp->client->dev, chip, adnp); 466 if (err) 467 return err; 468 469 return 0; 470 } 471 472 static int adnp_i2c_probe(struct i2c_client *client) 473 { 474 struct device *dev = &client->dev; 475 struct adnp *adnp; 476 u32 num_gpios; 477 int err; 478 479 err = device_property_read_u32(dev, "nr-gpios", &num_gpios); 480 if (err < 0) 481 return err; 482 483 adnp = devm_kzalloc(&client->dev, sizeof(*adnp), GFP_KERNEL); 484 if (!adnp) 485 return -ENOMEM; 486 487 err = devm_mutex_init(&client->dev, &adnp->i2c_lock); 488 if (err) 489 return err; 490 491 adnp->client = client; 492 493 err = adnp_gpio_setup(adnp, num_gpios, device_property_read_bool(dev, "interrupt-controller")); 494 if (err) 495 return err; 496 497 i2c_set_clientdata(client, adnp); 498 499 return 0; 500 } 501 502 static const struct i2c_device_id adnp_i2c_id[] = { 503 { .name = "gpio-adnp" }, 504 { } 505 }; 506 MODULE_DEVICE_TABLE(i2c, adnp_i2c_id); 507 508 static const struct of_device_id adnp_of_match[] = { 509 { .compatible = "ad,gpio-adnp", }, 510 { }, 511 }; 512 MODULE_DEVICE_TABLE(of, adnp_of_match); 513 514 static struct i2c_driver adnp_i2c_driver = { 515 .driver = { 516 .name = "gpio-adnp", 517 .of_match_table = adnp_of_match, 518 }, 519 .probe = adnp_i2c_probe, 520 .id_table = adnp_i2c_id, 521 }; 522 module_i2c_driver(adnp_i2c_driver); 523 524 MODULE_DESCRIPTION("Avionic Design N-bit GPIO expander"); 525 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); 526 MODULE_LICENSE("GPL"); 527