1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2011-2012 Avionic Design GmbH 4 */ 5 6 #include <linux/cleanup.h> 7 #include <linux/gpio/driver.h> 8 #include <linux/i2c.h> 9 #include <linux/interrupt.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/mutex.h> 13 #include <linux/property.h> 14 #include <linux/seq_file.h> 15 #include <linux/slab.h> 16 17 #define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift) 18 #define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift) 19 #define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift) 20 #define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift) 21 #define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift) 22 23 struct adnp { 24 struct i2c_client *client; 25 struct gpio_chip gpio; 26 unsigned int reg_shift; 27 28 struct mutex i2c_lock; 29 struct mutex irq_lock; 30 31 u8 *irq_enable; 32 u8 *irq_level; 33 u8 *irq_rise; 34 u8 *irq_fall; 35 u8 *irq_high; 36 u8 *irq_low; 37 }; 38 39 static int adnp_read(struct adnp *adnp, unsigned offset, uint8_t *value) 40 { 41 int err; 42 43 err = i2c_smbus_read_byte_data(adnp->client, offset); 44 if (err < 0) { 45 dev_err(adnp->gpio.parent, "%s failed: %d\n", 46 "i2c_smbus_read_byte_data()", err); 47 return err; 48 } 49 50 *value = err; 51 return 0; 52 } 53 54 static int adnp_write(struct adnp *adnp, unsigned offset, uint8_t value) 55 { 56 int err; 57 58 err = i2c_smbus_write_byte_data(adnp->client, offset, value); 59 if (err < 0) { 60 dev_err(adnp->gpio.parent, "%s failed: %d\n", 61 "i2c_smbus_write_byte_data()", err); 62 return err; 63 } 64 65 return 0; 66 } 67 68 static int adnp_gpio_get(struct gpio_chip *chip, unsigned offset) 69 { 70 struct adnp *adnp = gpiochip_get_data(chip); 71 unsigned int reg = offset >> adnp->reg_shift; 72 unsigned int pos = offset & 7; 73 u8 value; 74 int err; 75 76 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &value); 77 if (err < 0) 78 return err; 79 80 return (value & BIT(pos)) ? 1 : 0; 81 } 82 83 static int __adnp_gpio_set(struct adnp *adnp, unsigned int offset, int value) 84 { 85 unsigned int reg = offset >> adnp->reg_shift; 86 unsigned int pos = offset & 7; 87 int err; 88 u8 val; 89 90 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val); 91 if (err < 0) 92 return err; 93 94 if (value) 95 val |= BIT(pos); 96 else 97 val &= ~BIT(pos); 98 99 return adnp_write(adnp, GPIO_PLR(adnp) + reg, val); 100 } 101 102 static int adnp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 103 { 104 struct adnp *adnp = gpiochip_get_data(chip); 105 106 guard(mutex)(&adnp->i2c_lock); 107 108 return __adnp_gpio_set(adnp, offset, value); 109 } 110 111 static int adnp_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 112 { 113 struct adnp *adnp = gpiochip_get_data(chip); 114 unsigned int reg = offset >> adnp->reg_shift; 115 unsigned int pos = offset & 7; 116 u8 value; 117 int err; 118 119 guard(mutex)(&adnp->i2c_lock); 120 121 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value); 122 if (err < 0) 123 return err; 124 125 value &= ~BIT(pos); 126 127 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value); 128 if (err < 0) 129 return err; 130 131 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value); 132 if (err < 0) 133 return err; 134 135 if (value & BIT(pos)) 136 return -EPERM; 137 138 return 0; 139 } 140 141 static int adnp_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 142 int value) 143 { 144 struct adnp *adnp = gpiochip_get_data(chip); 145 unsigned int reg = offset >> adnp->reg_shift; 146 unsigned int pos = offset & 7; 147 int err; 148 u8 val; 149 150 guard(mutex)(&adnp->i2c_lock); 151 152 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val); 153 if (err < 0) 154 return err; 155 156 val |= BIT(pos); 157 158 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val); 159 if (err < 0) 160 return err; 161 162 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val); 163 if (err < 0) 164 return err; 165 166 if (!(val & BIT(pos))) 167 return -EPERM; 168 169 __adnp_gpio_set(adnp, offset, value); 170 171 return 0; 172 } 173 174 static void adnp_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 175 { 176 struct adnp *adnp = gpiochip_get_data(chip); 177 unsigned int num_regs = 1 << adnp->reg_shift, i, j; 178 int err; 179 180 for (i = 0; i < num_regs; i++) { 181 u8 ddr = 0, plr = 0, ier = 0, isr = 0; 182 183 scoped_guard(mutex, &adnp->i2c_lock) { 184 err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr); 185 if (err < 0) 186 return; 187 188 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr); 189 if (err < 0) 190 return; 191 192 err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier); 193 if (err < 0) 194 return; 195 196 err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr); 197 if (err < 0) 198 return; 199 200 } 201 202 for (j = 0; j < 8; j++) { 203 unsigned int bit = (i << adnp->reg_shift) + j; 204 const char *direction = "input "; 205 const char *level = "low "; 206 const char *interrupt = "disabled"; 207 const char *pending = ""; 208 209 if (ddr & BIT(j)) 210 direction = "output"; 211 212 if (plr & BIT(j)) 213 level = "high"; 214 215 if (ier & BIT(j)) 216 interrupt = "enabled "; 217 218 if (isr & BIT(j)) 219 pending = "pending"; 220 221 seq_printf(s, "%2u: %s %s IRQ %s %s\n", bit, 222 direction, level, interrupt, pending); 223 } 224 } 225 } 226 227 static irqreturn_t adnp_irq(int irq, void *data) 228 { 229 struct adnp *adnp = data; 230 unsigned int num_regs, i; 231 232 num_regs = 1 << adnp->reg_shift; 233 234 for (i = 0; i < num_regs; i++) { 235 unsigned int base = i << adnp->reg_shift, bit; 236 u8 changed, level = 0, isr = 0, ier = 0; 237 unsigned long pending; 238 int err; 239 240 { 241 guard(mutex)(&adnp->i2c_lock); 242 243 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level); 244 if (err < 0) 245 continue; 246 247 err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr); 248 if (err < 0) 249 continue; 250 251 err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier); 252 if (err < 0) 253 continue; 254 } 255 256 /* determine pins that changed levels */ 257 changed = level ^ adnp->irq_level[i]; 258 259 /* compute edge-triggered interrupts */ 260 pending = changed & ((adnp->irq_fall[i] & ~level) | 261 (adnp->irq_rise[i] & level)); 262 263 /* add in level-triggered interrupts */ 264 pending |= (adnp->irq_high[i] & level) | 265 (adnp->irq_low[i] & ~level); 266 267 /* mask out non-pending and disabled interrupts */ 268 pending &= isr & ier; 269 270 for_each_set_bit(bit, &pending, 8) { 271 unsigned int child_irq; 272 child_irq = irq_find_mapping(adnp->gpio.irq.domain, 273 base + bit); 274 handle_nested_irq(child_irq); 275 } 276 } 277 278 return IRQ_HANDLED; 279 } 280 281 static void adnp_irq_mask(struct irq_data *d) 282 { 283 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 284 struct adnp *adnp = gpiochip_get_data(gc); 285 unsigned int reg = d->hwirq >> adnp->reg_shift; 286 unsigned int pos = d->hwirq & 7; 287 288 adnp->irq_enable[reg] &= ~BIT(pos); 289 gpiochip_disable_irq(gc, irqd_to_hwirq(d)); 290 } 291 292 static void adnp_irq_unmask(struct irq_data *d) 293 { 294 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 295 struct adnp *adnp = gpiochip_get_data(gc); 296 unsigned int reg = d->hwirq >> adnp->reg_shift; 297 unsigned int pos = d->hwirq & 7; 298 299 gpiochip_enable_irq(gc, irqd_to_hwirq(d)); 300 adnp->irq_enable[reg] |= BIT(pos); 301 } 302 303 static int adnp_irq_set_type(struct irq_data *d, unsigned int type) 304 { 305 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 306 struct adnp *adnp = gpiochip_get_data(gc); 307 unsigned int reg = d->hwirq >> adnp->reg_shift; 308 unsigned int pos = d->hwirq & 7; 309 310 if (type & IRQ_TYPE_EDGE_RISING) 311 adnp->irq_rise[reg] |= BIT(pos); 312 else 313 adnp->irq_rise[reg] &= ~BIT(pos); 314 315 if (type & IRQ_TYPE_EDGE_FALLING) 316 adnp->irq_fall[reg] |= BIT(pos); 317 else 318 adnp->irq_fall[reg] &= ~BIT(pos); 319 320 if (type & IRQ_TYPE_LEVEL_HIGH) 321 adnp->irq_high[reg] |= BIT(pos); 322 else 323 adnp->irq_high[reg] &= ~BIT(pos); 324 325 if (type & IRQ_TYPE_LEVEL_LOW) 326 adnp->irq_low[reg] |= BIT(pos); 327 else 328 adnp->irq_low[reg] &= ~BIT(pos); 329 330 return 0; 331 } 332 333 static void adnp_irq_bus_lock(struct irq_data *d) 334 { 335 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 336 struct adnp *adnp = gpiochip_get_data(gc); 337 338 mutex_lock(&adnp->irq_lock); 339 } 340 341 static void adnp_irq_bus_unlock(struct irq_data *d) 342 { 343 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 344 struct adnp *adnp = gpiochip_get_data(gc); 345 unsigned int num_regs = 1 << adnp->reg_shift, i; 346 347 scoped_guard(mutex, &adnp->i2c_lock) { 348 for (i = 0; i < num_regs; i++) 349 adnp_write(adnp, GPIO_IER(adnp) + i, 350 adnp->irq_enable[i]); 351 } 352 353 mutex_unlock(&adnp->irq_lock); 354 } 355 356 static const struct irq_chip adnp_irq_chip = { 357 .name = "gpio-adnp", 358 .irq_mask = adnp_irq_mask, 359 .irq_unmask = adnp_irq_unmask, 360 .irq_set_type = adnp_irq_set_type, 361 .irq_bus_lock = adnp_irq_bus_lock, 362 .irq_bus_sync_unlock = adnp_irq_bus_unlock, 363 .flags = IRQCHIP_IMMUTABLE, 364 GPIOCHIP_IRQ_RESOURCE_HELPERS, 365 }; 366 367 static int adnp_irq_setup(struct adnp *adnp) 368 { 369 unsigned int num_regs = 1 << adnp->reg_shift, i; 370 struct gpio_chip *chip = &adnp->gpio; 371 int err; 372 373 mutex_init(&adnp->irq_lock); 374 375 /* 376 * Allocate memory to keep track of the current level and trigger 377 * modes of the interrupts. To avoid multiple allocations, a single 378 * large buffer is allocated and pointers are setup to point at the 379 * corresponding offsets. For consistency, the layout of the buffer 380 * is chosen to match the register layout of the hardware in that 381 * each segment contains the corresponding bits for all interrupts. 382 */ 383 adnp->irq_enable = devm_kcalloc(chip->parent, num_regs, 6, 384 GFP_KERNEL); 385 if (!adnp->irq_enable) 386 return -ENOMEM; 387 388 adnp->irq_level = adnp->irq_enable + (num_regs * 1); 389 adnp->irq_rise = adnp->irq_enable + (num_regs * 2); 390 adnp->irq_fall = adnp->irq_enable + (num_regs * 3); 391 adnp->irq_high = adnp->irq_enable + (num_regs * 4); 392 adnp->irq_low = adnp->irq_enable + (num_regs * 5); 393 394 for (i = 0; i < num_regs; i++) { 395 /* 396 * Read the initial level of all pins to allow the emulation 397 * of edge triggered interrupts. 398 */ 399 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &adnp->irq_level[i]); 400 if (err < 0) 401 return err; 402 403 /* disable all interrupts */ 404 err = adnp_write(adnp, GPIO_IER(adnp) + i, 0); 405 if (err < 0) 406 return err; 407 408 adnp->irq_enable[i] = 0x00; 409 } 410 411 err = devm_request_threaded_irq(chip->parent, adnp->client->irq, 412 NULL, adnp_irq, 413 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 414 dev_name(chip->parent), adnp); 415 if (err != 0) { 416 dev_err(chip->parent, "can't request IRQ#%d: %d\n", 417 adnp->client->irq, err); 418 return err; 419 } 420 421 return 0; 422 } 423 424 static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios, 425 bool is_irq_controller) 426 { 427 struct gpio_chip *chip = &adnp->gpio; 428 int err; 429 430 adnp->reg_shift = get_count_order(num_gpios) - 3; 431 432 chip->direction_input = adnp_gpio_direction_input; 433 chip->direction_output = adnp_gpio_direction_output; 434 chip->get = adnp_gpio_get; 435 chip->set = adnp_gpio_set; 436 chip->can_sleep = true; 437 438 if (IS_ENABLED(CONFIG_DEBUG_FS)) 439 chip->dbg_show = adnp_gpio_dbg_show; 440 441 chip->base = -1; 442 chip->ngpio = num_gpios; 443 chip->label = adnp->client->name; 444 chip->parent = &adnp->client->dev; 445 chip->owner = THIS_MODULE; 446 447 if (is_irq_controller) { 448 struct gpio_irq_chip *girq; 449 450 err = adnp_irq_setup(adnp); 451 if (err) 452 return err; 453 454 girq = &chip->irq; 455 gpio_irq_chip_set_chip(girq, &adnp_irq_chip); 456 457 /* This will let us handle the parent IRQ in the driver */ 458 girq->parent_handler = NULL; 459 girq->num_parents = 0; 460 girq->parents = NULL; 461 girq->default_type = IRQ_TYPE_NONE; 462 girq->handler = handle_simple_irq; 463 girq->threaded = true; 464 } 465 466 err = devm_gpiochip_add_data(&adnp->client->dev, chip, adnp); 467 if (err) 468 return err; 469 470 return 0; 471 } 472 473 static int adnp_i2c_probe(struct i2c_client *client) 474 { 475 struct device *dev = &client->dev; 476 struct adnp *adnp; 477 u32 num_gpios; 478 int err; 479 480 err = device_property_read_u32(dev, "nr-gpios", &num_gpios); 481 if (err < 0) 482 return err; 483 484 adnp = devm_kzalloc(&client->dev, sizeof(*adnp), GFP_KERNEL); 485 if (!adnp) 486 return -ENOMEM; 487 488 err = devm_mutex_init(&client->dev, &adnp->i2c_lock); 489 if (err) 490 return err; 491 492 adnp->client = client; 493 494 err = adnp_gpio_setup(adnp, num_gpios, device_property_read_bool(dev, "interrupt-controller")); 495 if (err) 496 return err; 497 498 i2c_set_clientdata(client, adnp); 499 500 return 0; 501 } 502 503 static const struct i2c_device_id adnp_i2c_id[] = { 504 { "gpio-adnp" }, 505 { }, 506 }; 507 MODULE_DEVICE_TABLE(i2c, adnp_i2c_id); 508 509 static const struct of_device_id adnp_of_match[] = { 510 { .compatible = "ad,gpio-adnp", }, 511 { }, 512 }; 513 MODULE_DEVICE_TABLE(of, adnp_of_match); 514 515 static struct i2c_driver adnp_i2c_driver = { 516 .driver = { 517 .name = "gpio-adnp", 518 .of_match_table = adnp_of_match, 519 }, 520 .probe = adnp_i2c_probe, 521 .id_table = adnp_i2c_id, 522 }; 523 module_i2c_driver(adnp_i2c_driver); 524 525 MODULE_DESCRIPTION("Avionic Design N-bit GPIO expander"); 526 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); 527 MODULE_LICENSE("GPL"); 528