1 /* 2 * Copyright (C) 2011-2012 Avionic Design GmbH 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/gpio/driver.h> 10 #include <linux/i2c.h> 11 #include <linux/interrupt.h> 12 #include <linux/module.h> 13 #include <linux/of_irq.h> 14 #include <linux/seq_file.h> 15 #include <linux/slab.h> 16 17 #define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift) 18 #define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift) 19 #define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift) 20 #define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift) 21 #define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift) 22 23 struct adnp { 24 struct i2c_client *client; 25 struct gpio_chip gpio; 26 unsigned int reg_shift; 27 28 struct mutex i2c_lock; 29 struct mutex irq_lock; 30 31 u8 *irq_enable; 32 u8 *irq_level; 33 u8 *irq_rise; 34 u8 *irq_fall; 35 u8 *irq_high; 36 u8 *irq_low; 37 }; 38 39 static inline struct adnp *to_adnp(struct gpio_chip *chip) 40 { 41 return container_of(chip, struct adnp, gpio); 42 } 43 44 static int adnp_read(struct adnp *adnp, unsigned offset, uint8_t *value) 45 { 46 int err; 47 48 err = i2c_smbus_read_byte_data(adnp->client, offset); 49 if (err < 0) { 50 dev_err(adnp->gpio.dev, "%s failed: %d\n", 51 "i2c_smbus_read_byte_data()", err); 52 return err; 53 } 54 55 *value = err; 56 return 0; 57 } 58 59 static int adnp_write(struct adnp *adnp, unsigned offset, uint8_t value) 60 { 61 int err; 62 63 err = i2c_smbus_write_byte_data(adnp->client, offset, value); 64 if (err < 0) { 65 dev_err(adnp->gpio.dev, "%s failed: %d\n", 66 "i2c_smbus_write_byte_data()", err); 67 return err; 68 } 69 70 return 0; 71 } 72 73 static int adnp_gpio_get(struct gpio_chip *chip, unsigned offset) 74 { 75 struct adnp *adnp = to_adnp(chip); 76 unsigned int reg = offset >> adnp->reg_shift; 77 unsigned int pos = offset & 7; 78 u8 value; 79 int err; 80 81 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &value); 82 if (err < 0) 83 return err; 84 85 return (value & BIT(pos)) ? 1 : 0; 86 } 87 88 static void __adnp_gpio_set(struct adnp *adnp, unsigned offset, int value) 89 { 90 unsigned int reg = offset >> adnp->reg_shift; 91 unsigned int pos = offset & 7; 92 int err; 93 u8 val; 94 95 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val); 96 if (err < 0) 97 return; 98 99 if (value) 100 val |= BIT(pos); 101 else 102 val &= ~BIT(pos); 103 104 adnp_write(adnp, GPIO_PLR(adnp) + reg, val); 105 } 106 107 static void adnp_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 108 { 109 struct adnp *adnp = to_adnp(chip); 110 111 mutex_lock(&adnp->i2c_lock); 112 __adnp_gpio_set(adnp, offset, value); 113 mutex_unlock(&adnp->i2c_lock); 114 } 115 116 static int adnp_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 117 { 118 struct adnp *adnp = to_adnp(chip); 119 unsigned int reg = offset >> adnp->reg_shift; 120 unsigned int pos = offset & 7; 121 u8 value; 122 int err; 123 124 mutex_lock(&adnp->i2c_lock); 125 126 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value); 127 if (err < 0) 128 goto out; 129 130 value &= ~BIT(pos); 131 132 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value); 133 if (err < 0) 134 goto out; 135 136 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value); 137 if (err < 0) 138 goto out; 139 140 if (err & BIT(pos)) 141 err = -EACCES; 142 143 err = 0; 144 145 out: 146 mutex_unlock(&adnp->i2c_lock); 147 return err; 148 } 149 150 static int adnp_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 151 int value) 152 { 153 struct adnp *adnp = to_adnp(chip); 154 unsigned int reg = offset >> adnp->reg_shift; 155 unsigned int pos = offset & 7; 156 int err; 157 u8 val; 158 159 mutex_lock(&adnp->i2c_lock); 160 161 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val); 162 if (err < 0) 163 goto out; 164 165 val |= BIT(pos); 166 167 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val); 168 if (err < 0) 169 goto out; 170 171 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val); 172 if (err < 0) 173 goto out; 174 175 if (!(val & BIT(pos))) { 176 err = -EPERM; 177 goto out; 178 } 179 180 __adnp_gpio_set(adnp, offset, value); 181 err = 0; 182 183 out: 184 mutex_unlock(&adnp->i2c_lock); 185 return err; 186 } 187 188 static void adnp_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 189 { 190 struct adnp *adnp = to_adnp(chip); 191 unsigned int num_regs = 1 << adnp->reg_shift, i, j; 192 int err; 193 194 for (i = 0; i < num_regs; i++) { 195 u8 ddr, plr, ier, isr; 196 197 mutex_lock(&adnp->i2c_lock); 198 199 err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr); 200 if (err < 0) { 201 mutex_unlock(&adnp->i2c_lock); 202 return; 203 } 204 205 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr); 206 if (err < 0) { 207 mutex_unlock(&adnp->i2c_lock); 208 return; 209 } 210 211 err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier); 212 if (err < 0) { 213 mutex_unlock(&adnp->i2c_lock); 214 return; 215 } 216 217 err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr); 218 if (err < 0) { 219 mutex_unlock(&adnp->i2c_lock); 220 return; 221 } 222 223 mutex_unlock(&adnp->i2c_lock); 224 225 for (j = 0; j < 8; j++) { 226 unsigned int bit = (i << adnp->reg_shift) + j; 227 const char *direction = "input "; 228 const char *level = "low "; 229 const char *interrupt = "disabled"; 230 const char *pending = ""; 231 232 if (ddr & BIT(j)) 233 direction = "output"; 234 235 if (plr & BIT(j)) 236 level = "high"; 237 238 if (ier & BIT(j)) 239 interrupt = "enabled "; 240 241 if (isr & BIT(j)) 242 pending = "pending"; 243 244 seq_printf(s, "%2u: %s %s IRQ %s %s\n", bit, 245 direction, level, interrupt, pending); 246 } 247 } 248 } 249 250 static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios) 251 { 252 struct gpio_chip *chip = &adnp->gpio; 253 int err; 254 255 adnp->reg_shift = get_count_order(num_gpios) - 3; 256 257 chip->direction_input = adnp_gpio_direction_input; 258 chip->direction_output = adnp_gpio_direction_output; 259 chip->get = adnp_gpio_get; 260 chip->set = adnp_gpio_set; 261 chip->can_sleep = true; 262 263 if (IS_ENABLED(CONFIG_DEBUG_FS)) 264 chip->dbg_show = adnp_gpio_dbg_show; 265 266 chip->base = -1; 267 chip->ngpio = num_gpios; 268 chip->label = adnp->client->name; 269 chip->dev = &adnp->client->dev; 270 chip->of_node = chip->dev->of_node; 271 chip->owner = THIS_MODULE; 272 273 err = gpiochip_add(chip); 274 if (err) 275 return err; 276 277 return 0; 278 } 279 280 static irqreturn_t adnp_irq(int irq, void *data) 281 { 282 struct adnp *adnp = data; 283 unsigned int num_regs, i; 284 285 num_regs = 1 << adnp->reg_shift; 286 287 for (i = 0; i < num_regs; i++) { 288 unsigned int base = i << adnp->reg_shift, bit; 289 u8 changed, level, isr, ier; 290 unsigned long pending; 291 int err; 292 293 mutex_lock(&adnp->i2c_lock); 294 295 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level); 296 if (err < 0) { 297 mutex_unlock(&adnp->i2c_lock); 298 continue; 299 } 300 301 err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr); 302 if (err < 0) { 303 mutex_unlock(&adnp->i2c_lock); 304 continue; 305 } 306 307 err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier); 308 if (err < 0) { 309 mutex_unlock(&adnp->i2c_lock); 310 continue; 311 } 312 313 mutex_unlock(&adnp->i2c_lock); 314 315 /* determine pins that changed levels */ 316 changed = level ^ adnp->irq_level[i]; 317 318 /* compute edge-triggered interrupts */ 319 pending = changed & ((adnp->irq_fall[i] & ~level) | 320 (adnp->irq_rise[i] & level)); 321 322 /* add in level-triggered interrupts */ 323 pending |= (adnp->irq_high[i] & level) | 324 (adnp->irq_low[i] & ~level); 325 326 /* mask out non-pending and disabled interrupts */ 327 pending &= isr & ier; 328 329 for_each_set_bit(bit, &pending, 8) { 330 unsigned int child_irq; 331 child_irq = irq_find_mapping(adnp->gpio.irqdomain, 332 base + bit); 333 handle_nested_irq(child_irq); 334 } 335 } 336 337 return IRQ_HANDLED; 338 } 339 340 static void adnp_irq_mask(struct irq_data *d) 341 { 342 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 343 struct adnp *adnp = to_adnp(gc); 344 unsigned int reg = d->hwirq >> adnp->reg_shift; 345 unsigned int pos = d->hwirq & 7; 346 347 adnp->irq_enable[reg] &= ~BIT(pos); 348 } 349 350 static void adnp_irq_unmask(struct irq_data *d) 351 { 352 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 353 struct adnp *adnp = to_adnp(gc); 354 unsigned int reg = d->hwirq >> adnp->reg_shift; 355 unsigned int pos = d->hwirq & 7; 356 357 adnp->irq_enable[reg] |= BIT(pos); 358 } 359 360 static int adnp_irq_set_type(struct irq_data *d, unsigned int type) 361 { 362 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 363 struct adnp *adnp = to_adnp(gc); 364 unsigned int reg = d->hwirq >> adnp->reg_shift; 365 unsigned int pos = d->hwirq & 7; 366 367 if (type & IRQ_TYPE_EDGE_RISING) 368 adnp->irq_rise[reg] |= BIT(pos); 369 else 370 adnp->irq_rise[reg] &= ~BIT(pos); 371 372 if (type & IRQ_TYPE_EDGE_FALLING) 373 adnp->irq_fall[reg] |= BIT(pos); 374 else 375 adnp->irq_fall[reg] &= ~BIT(pos); 376 377 if (type & IRQ_TYPE_LEVEL_HIGH) 378 adnp->irq_high[reg] |= BIT(pos); 379 else 380 adnp->irq_high[reg] &= ~BIT(pos); 381 382 if (type & IRQ_TYPE_LEVEL_LOW) 383 adnp->irq_low[reg] |= BIT(pos); 384 else 385 adnp->irq_low[reg] &= ~BIT(pos); 386 387 return 0; 388 } 389 390 static void adnp_irq_bus_lock(struct irq_data *d) 391 { 392 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 393 struct adnp *adnp = to_adnp(gc); 394 395 mutex_lock(&adnp->irq_lock); 396 } 397 398 static void adnp_irq_bus_unlock(struct irq_data *d) 399 { 400 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 401 struct adnp *adnp = to_adnp(gc); 402 unsigned int num_regs = 1 << adnp->reg_shift, i; 403 404 mutex_lock(&adnp->i2c_lock); 405 406 for (i = 0; i < num_regs; i++) 407 adnp_write(adnp, GPIO_IER(adnp) + i, adnp->irq_enable[i]); 408 409 mutex_unlock(&adnp->i2c_lock); 410 mutex_unlock(&adnp->irq_lock); 411 } 412 413 static struct irq_chip adnp_irq_chip = { 414 .name = "gpio-adnp", 415 .irq_mask = adnp_irq_mask, 416 .irq_unmask = adnp_irq_unmask, 417 .irq_set_type = adnp_irq_set_type, 418 .irq_bus_lock = adnp_irq_bus_lock, 419 .irq_bus_sync_unlock = adnp_irq_bus_unlock, 420 }; 421 422 static int adnp_irq_setup(struct adnp *adnp) 423 { 424 unsigned int num_regs = 1 << adnp->reg_shift, i; 425 struct gpio_chip *chip = &adnp->gpio; 426 int err; 427 428 mutex_init(&adnp->irq_lock); 429 430 /* 431 * Allocate memory to keep track of the current level and trigger 432 * modes of the interrupts. To avoid multiple allocations, a single 433 * large buffer is allocated and pointers are setup to point at the 434 * corresponding offsets. For consistency, the layout of the buffer 435 * is chosen to match the register layout of the hardware in that 436 * each segment contains the corresponding bits for all interrupts. 437 */ 438 adnp->irq_enable = devm_kzalloc(chip->dev, num_regs * 6, GFP_KERNEL); 439 if (!adnp->irq_enable) 440 return -ENOMEM; 441 442 adnp->irq_level = adnp->irq_enable + (num_regs * 1); 443 adnp->irq_rise = adnp->irq_enable + (num_regs * 2); 444 adnp->irq_fall = adnp->irq_enable + (num_regs * 3); 445 adnp->irq_high = adnp->irq_enable + (num_regs * 4); 446 adnp->irq_low = adnp->irq_enable + (num_regs * 5); 447 448 for (i = 0; i < num_regs; i++) { 449 /* 450 * Read the initial level of all pins to allow the emulation 451 * of edge triggered interrupts. 452 */ 453 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &adnp->irq_level[i]); 454 if (err < 0) 455 return err; 456 457 /* disable all interrupts */ 458 err = adnp_write(adnp, GPIO_IER(adnp) + i, 0); 459 if (err < 0) 460 return err; 461 462 adnp->irq_enable[i] = 0x00; 463 } 464 465 err = devm_request_threaded_irq(chip->dev, adnp->client->irq, 466 NULL, adnp_irq, 467 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 468 dev_name(chip->dev), adnp); 469 if (err != 0) { 470 dev_err(chip->dev, "can't request IRQ#%d: %d\n", 471 adnp->client->irq, err); 472 return err; 473 } 474 475 err = gpiochip_irqchip_add(chip, 476 &adnp_irq_chip, 477 0, 478 handle_simple_irq, 479 IRQ_TYPE_NONE); 480 if (err) { 481 dev_err(chip->dev, 482 "could not connect irqchip to gpiochip\n"); 483 return err; 484 } 485 486 return 0; 487 } 488 489 static int adnp_i2c_probe(struct i2c_client *client, 490 const struct i2c_device_id *id) 491 { 492 struct device_node *np = client->dev.of_node; 493 struct adnp *adnp; 494 u32 num_gpios; 495 int err; 496 497 err = of_property_read_u32(np, "nr-gpios", &num_gpios); 498 if (err < 0) 499 return err; 500 501 client->irq = irq_of_parse_and_map(np, 0); 502 if (!client->irq) 503 return -EPROBE_DEFER; 504 505 adnp = devm_kzalloc(&client->dev, sizeof(*adnp), GFP_KERNEL); 506 if (!adnp) 507 return -ENOMEM; 508 509 mutex_init(&adnp->i2c_lock); 510 adnp->client = client; 511 512 err = adnp_gpio_setup(adnp, num_gpios); 513 if (err) 514 return err; 515 516 if (of_find_property(np, "interrupt-controller", NULL)) { 517 err = adnp_irq_setup(adnp); 518 if (err) 519 return err; 520 } 521 522 i2c_set_clientdata(client, adnp); 523 524 return 0; 525 } 526 527 static int adnp_i2c_remove(struct i2c_client *client) 528 { 529 struct adnp *adnp = i2c_get_clientdata(client); 530 531 gpiochip_remove(&adnp->gpio); 532 return 0; 533 } 534 535 static const struct i2c_device_id adnp_i2c_id[] = { 536 { "gpio-adnp" }, 537 { }, 538 }; 539 MODULE_DEVICE_TABLE(i2c, adnp_i2c_id); 540 541 static const struct of_device_id adnp_of_match[] = { 542 { .compatible = "ad,gpio-adnp", }, 543 { }, 544 }; 545 MODULE_DEVICE_TABLE(of, adnp_of_match); 546 547 static struct i2c_driver adnp_i2c_driver = { 548 .driver = { 549 .name = "gpio-adnp", 550 .owner = THIS_MODULE, 551 .of_match_table = adnp_of_match, 552 }, 553 .probe = adnp_i2c_probe, 554 .remove = adnp_i2c_remove, 555 .id_table = adnp_i2c_id, 556 }; 557 module_i2c_driver(adnp_i2c_driver); 558 559 MODULE_DESCRIPTION("Avionic Design N-bit GPIO expander"); 560 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); 561 MODULE_LICENSE("GPL"); 562