1 // SPDX-License-Identifier: GPL-2.0 2 3 /*************************************************************************** 4 * copyright : (C) 2001, 2002 by Frank Mori Hess 5 ***************************************************************************/ 6 7 #define dev_fmt(fmt) KBUILD_MODNAME ": " fmt 8 9 #include "board.h" 10 #include <linux/ioport.h> 11 #include <linux/sched.h> 12 #include <linux/module.h> 13 #include <linux/slab.h> 14 #include <asm/dma.h> 15 #include <linux/bitops.h> 16 #include <linux/pci.h> 17 #include <linux/pci_ids.h> 18 #include <linux/string.h> 19 #include <linux/init.h> 20 #include <linux/spinlock.h> 21 #include <linux/delay.h> 22 23 MODULE_LICENSE("GPL"); 24 MODULE_DESCRIPTION("GPIB library code for NEC uPD7210"); 25 26 int nec7210_enable_eos(struct gpib_board *board, struct nec7210_priv *priv, u8 eos_byte, 27 int compare_8_bits) 28 { 29 write_byte(priv, eos_byte, EOSR); 30 priv->auxa_bits |= HR_REOS; 31 if (compare_8_bits) 32 priv->auxa_bits |= HR_BIN; 33 else 34 priv->auxa_bits &= ~HR_BIN; 35 write_byte(priv, priv->auxa_bits, AUXMR); 36 return 0; 37 } 38 EXPORT_SYMBOL(nec7210_enable_eos); 39 40 void nec7210_disable_eos(struct gpib_board *board, struct nec7210_priv *priv) 41 { 42 priv->auxa_bits &= ~HR_REOS; 43 write_byte(priv, priv->auxa_bits, AUXMR); 44 } 45 EXPORT_SYMBOL(nec7210_disable_eos); 46 47 int nec7210_parallel_poll(struct gpib_board *board, struct nec7210_priv *priv, u8 *result) 48 { 49 int ret; 50 51 clear_bit(COMMAND_READY_BN, &priv->state); 52 53 // execute parallel poll 54 write_byte(priv, AUX_EPP, AUXMR); 55 // wait for result FIXME: support timeouts 56 ret = wait_event_interruptible(board->wait, test_bit(COMMAND_READY_BN, &priv->state)); 57 if (ret) { 58 dev_dbg(board->gpib_dev, "gpib: parallel poll interrupted\n"); 59 return -ERESTARTSYS; 60 } 61 *result = read_byte(priv, CPTR); 62 63 return 0; 64 } 65 EXPORT_SYMBOL(nec7210_parallel_poll); 66 67 void nec7210_parallel_poll_configure(struct gpib_board *board, 68 struct nec7210_priv *priv, unsigned int configuration) 69 { 70 write_byte(priv, PPR | configuration, AUXMR); 71 } 72 EXPORT_SYMBOL(nec7210_parallel_poll_configure); 73 74 void nec7210_parallel_poll_response(struct gpib_board *board, struct nec7210_priv *priv, int ist) 75 { 76 if (ist) 77 write_byte(priv, AUX_SPPF, AUXMR); 78 else 79 write_byte(priv, AUX_CPPF, AUXMR); 80 } 81 EXPORT_SYMBOL(nec7210_parallel_poll_response); 82 /* 83 * This is really only adequate for chips that do a 488.2 style reqt/reqf 84 * based on bit 6 of the SPMR (see chapter 11.3.3 of 488.2). For simpler chips that simply 85 * set rsv directly based on bit 6, we either need to do more hardware setup to expose 86 * the 488.2 capability (for example with NI chips), or we need to implement the 87 * 488.2 set srv state machine in the driver (if that is even viable). 88 */ 89 void nec7210_serial_poll_response(struct gpib_board *board, 90 struct nec7210_priv *priv, u8 status) 91 { 92 unsigned long flags; 93 94 spin_lock_irqsave(&board->spinlock, flags); 95 if (status & request_service_bit) { 96 priv->srq_pending = 1; 97 clear_bit(SPOLL_NUM, &board->status); 98 99 } else { 100 priv->srq_pending = 0; 101 } 102 write_byte(priv, status, SPMR); 103 spin_unlock_irqrestore(&board->spinlock, flags); 104 } 105 EXPORT_SYMBOL(nec7210_serial_poll_response); 106 107 u8 nec7210_serial_poll_status(struct gpib_board *board, struct nec7210_priv *priv) 108 { 109 return read_byte(priv, SPSR); 110 } 111 EXPORT_SYMBOL(nec7210_serial_poll_status); 112 113 int nec7210_primary_address(const struct gpib_board *board, struct nec7210_priv *priv, 114 unsigned int address) 115 { 116 // put primary address in address0 117 write_byte(priv, address & ADDRESS_MASK, ADR); 118 return 0; 119 } 120 EXPORT_SYMBOL(nec7210_primary_address); 121 122 int nec7210_secondary_address(const struct gpib_board *board, struct nec7210_priv *priv, 123 unsigned int address, int enable) 124 { 125 if (enable) { 126 // put secondary address in address1 127 write_byte(priv, HR_ARS | (address & ADDRESS_MASK), ADR); 128 // go to address mode 2 129 priv->reg_bits[ADMR] &= ~HR_ADM0; 130 priv->reg_bits[ADMR] |= HR_ADM1; 131 } else { 132 // disable address1 register 133 write_byte(priv, HR_ARS | HR_DT | HR_DL, ADR); 134 // go to address mode 1 135 priv->reg_bits[ADMR] |= HR_ADM0; 136 priv->reg_bits[ADMR] &= ~HR_ADM1; 137 } 138 write_byte(priv, priv->reg_bits[ADMR], ADMR); 139 return 0; 140 } 141 EXPORT_SYMBOL(nec7210_secondary_address); 142 143 static void update_talker_state(struct nec7210_priv *priv, unsigned int address_status_bits) 144 { 145 if ((address_status_bits & HR_TA)) { 146 if ((address_status_bits & HR_NATN)) { 147 if (address_status_bits & HR_SPMS) 148 priv->talker_state = serial_poll_active; 149 else 150 priv->talker_state = talker_active; 151 } else { 152 priv->talker_state = talker_addressed; 153 } 154 } else { 155 priv->talker_state = talker_idle; 156 } 157 } 158 159 static void update_listener_state(struct nec7210_priv *priv, unsigned int address_status_bits) 160 { 161 if (address_status_bits & HR_LA) { 162 if ((address_status_bits & HR_NATN)) 163 priv->listener_state = listener_active; 164 else 165 priv->listener_state = listener_addressed; 166 } else { 167 priv->listener_state = listener_idle; 168 } 169 } 170 171 unsigned int nec7210_update_status_nolock(struct gpib_board *board, struct nec7210_priv *priv) 172 { 173 int address_status_bits; 174 u8 spoll_status; 175 176 if (!priv) 177 return 0; 178 179 address_status_bits = read_byte(priv, ADSR); 180 if (address_status_bits & HR_CIC) 181 set_bit(CIC_NUM, &board->status); 182 else 183 clear_bit(CIC_NUM, &board->status); 184 // check for talker/listener addressed 185 update_talker_state(priv, address_status_bits); 186 if (priv->talker_state == talker_active || priv->talker_state == talker_addressed) 187 set_bit(TACS_NUM, &board->status); 188 else 189 clear_bit(TACS_NUM, &board->status); 190 update_listener_state(priv, address_status_bits); 191 if (priv->listener_state == listener_active || 192 priv->listener_state == listener_addressed) 193 set_bit(LACS_NUM, &board->status); 194 else 195 clear_bit(LACS_NUM, &board->status); 196 if (address_status_bits & HR_NATN) 197 clear_bit(ATN_NUM, &board->status); 198 else 199 set_bit(ATN_NUM, &board->status); 200 spoll_status = nec7210_serial_poll_status(board, priv); 201 if (priv->srq_pending && (spoll_status & request_service_bit) == 0) { 202 priv->srq_pending = 0; 203 set_bit(SPOLL_NUM, &board->status); 204 } 205 206 /* 207 * we rely on the interrupt handler to set the 208 * rest of the status bits 209 */ 210 211 return board->status; 212 } 213 EXPORT_SYMBOL(nec7210_update_status_nolock); 214 215 unsigned int nec7210_update_status(struct gpib_board *board, struct nec7210_priv *priv, 216 unsigned int clear_mask) 217 { 218 unsigned long flags; 219 unsigned int retval; 220 221 spin_lock_irqsave(&board->spinlock, flags); 222 board->status &= ~clear_mask; 223 retval = nec7210_update_status_nolock(board, priv); 224 spin_unlock_irqrestore(&board->spinlock, flags); 225 226 return retval; 227 } 228 EXPORT_SYMBOL(nec7210_update_status); 229 230 unsigned int nec7210_set_reg_bits(struct nec7210_priv *priv, unsigned int reg, 231 unsigned int mask, unsigned int bits) 232 { 233 priv->reg_bits[reg] &= ~mask; 234 priv->reg_bits[reg] |= mask & bits; 235 write_byte(priv, priv->reg_bits[reg], reg); 236 return priv->reg_bits[reg]; 237 } 238 EXPORT_SYMBOL(nec7210_set_reg_bits); 239 240 void nec7210_set_handshake_mode(struct gpib_board *board, struct nec7210_priv *priv, int mode) 241 { 242 unsigned long flags; 243 244 mode &= HR_HANDSHAKE_MASK; 245 246 spin_lock_irqsave(&board->spinlock, flags); 247 if ((priv->auxa_bits & HR_HANDSHAKE_MASK) != mode) { 248 priv->auxa_bits &= ~HR_HANDSHAKE_MASK; 249 priv->auxa_bits |= mode; 250 write_byte(priv, priv->auxa_bits, AUXMR); 251 } 252 spin_unlock_irqrestore(&board->spinlock, flags); 253 } 254 EXPORT_SYMBOL(nec7210_set_handshake_mode); 255 256 u8 nec7210_read_data_in(struct gpib_board *board, struct nec7210_priv *priv, int *end) 257 { 258 unsigned long flags; 259 u8 data; 260 261 spin_lock_irqsave(&board->spinlock, flags); 262 data = read_byte(priv, DIR); 263 clear_bit(READ_READY_BN, &priv->state); 264 if (test_and_clear_bit(RECEIVED_END_BN, &priv->state)) 265 *end = 1; 266 else 267 *end = 0; 268 spin_unlock_irqrestore(&board->spinlock, flags); 269 270 return data; 271 } 272 EXPORT_SYMBOL(nec7210_read_data_in); 273 274 int nec7210_take_control(struct gpib_board *board, struct nec7210_priv *priv, int syncronous) 275 { 276 int i; 277 const int timeout = 100; 278 int retval = 0; 279 unsigned int adsr_bits = 0; 280 281 if (syncronous) 282 write_byte(priv, AUX_TCS, AUXMR); 283 else 284 write_byte(priv, AUX_TCA, AUXMR); 285 // busy wait until ATN is asserted 286 for (i = 0; i < timeout; i++) { 287 adsr_bits = read_byte(priv, ADSR); 288 if ((adsr_bits & HR_NATN) == 0) 289 break; 290 udelay(1); 291 } 292 if (i == timeout) 293 return -ETIMEDOUT; 294 295 clear_bit(WRITE_READY_BN, &priv->state); 296 297 return retval; 298 } 299 EXPORT_SYMBOL(nec7210_take_control); 300 301 int nec7210_go_to_standby(struct gpib_board *board, struct nec7210_priv *priv) 302 { 303 int i; 304 const int timeout = 1000; 305 unsigned int adsr_bits = 0; 306 int retval = 0; 307 308 write_byte(priv, AUX_GTS, AUXMR); 309 // busy wait until ATN is released 310 for (i = 0; i < timeout; i++) { 311 adsr_bits = read_byte(priv, ADSR); 312 if (adsr_bits & HR_NATN) 313 break; 314 udelay(1); 315 } 316 // if busy wait has failed, try sleeping 317 if (i == timeout) { 318 for (i = 0; i < HZ; i++) { 319 set_current_state(TASK_INTERRUPTIBLE); 320 if (schedule_timeout(1)) 321 return -ERESTARTSYS; 322 adsr_bits = read_byte(priv, ADSR); 323 if (adsr_bits & HR_NATN) 324 break; 325 } 326 if (i == HZ) 327 return -ETIMEDOUT; 328 } 329 330 clear_bit(COMMAND_READY_BN, &priv->state); 331 return retval; 332 } 333 EXPORT_SYMBOL(nec7210_go_to_standby); 334 335 int nec7210_request_system_control(struct gpib_board *board, struct nec7210_priv *priv, 336 int request_control) 337 { 338 if (request_control == 0) { 339 write_byte(priv, AUX_CREN, AUXMR); 340 write_byte(priv, AUX_CIFC, AUXMR); 341 write_byte(priv, AUX_DSC, AUXMR); 342 } 343 return 0; 344 } 345 EXPORT_SYMBOL(nec7210_request_system_control); 346 347 void nec7210_interface_clear(struct gpib_board *board, struct nec7210_priv *priv, int assert) 348 { 349 if (assert) 350 write_byte(priv, AUX_SIFC, AUXMR); 351 else 352 write_byte(priv, AUX_CIFC, AUXMR); 353 } 354 EXPORT_SYMBOL(nec7210_interface_clear); 355 356 void nec7210_remote_enable(struct gpib_board *board, struct nec7210_priv *priv, int enable) 357 { 358 if (enable) 359 write_byte(priv, AUX_SREN, AUXMR); 360 else 361 write_byte(priv, AUX_CREN, AUXMR); 362 } 363 EXPORT_SYMBOL(nec7210_remote_enable); 364 365 void nec7210_release_rfd_holdoff(struct gpib_board *board, struct nec7210_priv *priv) 366 { 367 unsigned long flags; 368 369 spin_lock_irqsave(&board->spinlock, flags); 370 if (test_bit(RFD_HOLDOFF_BN, &priv->state) && 371 test_bit(READ_READY_BN, &priv->state) == 0) { 372 write_byte(priv, AUX_FH, AUXMR); 373 clear_bit(RFD_HOLDOFF_BN, &priv->state); 374 } 375 spin_unlock_irqrestore(&board->spinlock, flags); 376 } 377 EXPORT_SYMBOL(nec7210_release_rfd_holdoff); 378 379 int nec7210_t1_delay(struct gpib_board *board, struct nec7210_priv *priv, 380 unsigned int nano_sec) 381 { 382 unsigned int retval; 383 384 if (nano_sec <= 500) { 385 priv->auxb_bits |= HR_TRI; 386 retval = 500; 387 } else { 388 priv->auxb_bits &= ~HR_TRI; 389 retval = 2000; 390 } 391 write_byte(priv, priv->auxb_bits, AUXMR); 392 393 return retval; 394 } 395 EXPORT_SYMBOL(nec7210_t1_delay); 396 397 void nec7210_return_to_local(const struct gpib_board *board, struct nec7210_priv *priv) 398 { 399 write_byte(priv, AUX_RTL, AUXMR); 400 } 401 EXPORT_SYMBOL(nec7210_return_to_local); 402 403 static inline short nec7210_atn_has_changed(struct gpib_board *board, struct nec7210_priv *priv) 404 { 405 short address_status_bits = read_byte(priv, ADSR); 406 407 if (address_status_bits & HR_NATN) { 408 if (test_bit(ATN_NUM, &board->status)) 409 return 1; 410 else 411 return 0; 412 } else { 413 if (test_bit(ATN_NUM, &board->status)) 414 return 0; 415 else 416 return 1; 417 } 418 return -1; 419 } 420 421 int nec7210_command(struct gpib_board *board, struct nec7210_priv *priv, u8 422 *buffer, size_t length, size_t *bytes_written) 423 { 424 int retval = 0; 425 unsigned long flags; 426 427 *bytes_written = 0; 428 429 clear_bit(BUS_ERROR_BN, &priv->state); 430 431 while (*bytes_written < length) { 432 if (wait_event_interruptible(board->wait, 433 test_bit(COMMAND_READY_BN, &priv->state) || 434 test_bit(BUS_ERROR_BN, &priv->state) || 435 test_bit(TIMO_NUM, &board->status))) { 436 dev_dbg(board->gpib_dev, "command wait interrupted\n"); 437 retval = -ERESTARTSYS; 438 break; 439 } 440 if (test_bit(TIMO_NUM, &board->status)) 441 break; 442 if (test_and_clear_bit(BUS_ERROR_BN, &priv->state)) 443 break; 444 spin_lock_irqsave(&board->spinlock, flags); 445 clear_bit(COMMAND_READY_BN, &priv->state); 446 write_byte(priv, buffer[*bytes_written], CDOR); 447 spin_unlock_irqrestore(&board->spinlock, flags); 448 449 ++(*bytes_written); 450 451 if (need_resched()) 452 schedule(); 453 } 454 // wait for last byte to get sent 455 if (wait_event_interruptible(board->wait, test_bit(COMMAND_READY_BN, &priv->state) || 456 test_bit(BUS_ERROR_BN, &priv->state) || 457 test_bit(TIMO_NUM, &board->status))) 458 retval = -ERESTARTSYS; 459 460 if (test_bit(TIMO_NUM, &board->status)) 461 retval = -ETIMEDOUT; 462 463 if (test_and_clear_bit(BUS_ERROR_BN, &priv->state)) 464 retval = -EIO; 465 466 return retval; 467 } 468 EXPORT_SYMBOL(nec7210_command); 469 470 static int pio_read(struct gpib_board *board, struct nec7210_priv *priv, u8 *buffer, 471 size_t length, int *end, size_t *bytes_read) 472 { 473 ssize_t retval = 0; 474 475 *bytes_read = 0; 476 *end = 0; 477 478 while (*bytes_read < length) { 479 if (wait_event_interruptible(board->wait, 480 test_bit(READ_READY_BN, &priv->state) || 481 test_bit(DEV_CLEAR_BN, &priv->state) || 482 test_bit(TIMO_NUM, &board->status))) { 483 retval = -ERESTARTSYS; 484 break; 485 } 486 if (test_bit(READ_READY_BN, &priv->state)) { 487 if (*bytes_read == 0) { 488 /* 489 * We set the handshake mode here because we know 490 * no new bytes will arrive (it has already arrived 491 * and is awaiting being read out of the chip) while we are changing 492 * modes. This ensures we can reliably keep track 493 * of the holdoff state. 494 */ 495 nec7210_set_handshake_mode(board, priv, HR_HLDA); 496 } 497 buffer[(*bytes_read)++] = nec7210_read_data_in(board, priv, end); 498 if (*end) 499 break; 500 } 501 if (test_bit(TIMO_NUM, &board->status)) { 502 retval = -ETIMEDOUT; 503 break; 504 } 505 if (test_bit(DEV_CLEAR_BN, &priv->state)) { 506 retval = -EINTR; 507 break; 508 } 509 510 if (*bytes_read < length) 511 nec7210_release_rfd_holdoff(board, priv); 512 513 if (need_resched()) 514 schedule(); 515 } 516 return retval; 517 } 518 519 #ifdef NEC_DMA 520 static ssize_t __dma_read(struct gpib_board *board, struct nec7210_priv *priv, size_t length) 521 { 522 ssize_t retval = 0; 523 size_t count = 0; 524 unsigned long flags, dma_irq_flags; 525 526 if (length == 0) 527 return 0; 528 529 spin_lock_irqsave(&board->spinlock, flags); 530 531 dma_irq_flags = claim_dma_lock(); 532 disable_dma(priv->dma_channel); 533 /* program dma controller */ 534 clear_dma_ff(priv->dma_channel); 535 set_dma_count(priv->dma_channel, length); 536 set_dma_addr(priv->dma_channel, priv->dma_buffer_addr); 537 set_dma_mode(priv->dma_channel, DMA_MODE_READ); 538 release_dma_lock(dma_irq_flags); 539 540 enable_dma(priv->dma_channel); 541 542 set_bit(DMA_READ_IN_PROGRESS_BN, &priv->state); 543 clear_bit(READ_READY_BN, &priv->state); 544 545 // enable nec7210 dma 546 nec7210_set_reg_bits(priv, IMR2, HR_DMAI, HR_DMAI); 547 548 spin_unlock_irqrestore(&board->spinlock, flags); 549 550 // wait for data to transfer 551 if (wait_event_interruptible(board->wait, 552 test_bit(DMA_READ_IN_PROGRESS_BN, &priv->state) == 0 || 553 test_bit(DEV_CLEAR_BN, &priv->state) || 554 test_bit(TIMO_NUM, &board->status))) 555 retval = -ERESTARTSYS; 556 557 if (test_bit(TIMO_NUM, &board->status)) 558 retval = -ETIMEDOUT; 559 if (test_bit(DEV_CLEAR_BN, &priv->state)) 560 retval = -EINTR; 561 562 // disable nec7210 dma 563 nec7210_set_reg_bits(priv, IMR2, HR_DMAI, 0); 564 565 // record how many bytes we transferred 566 flags = claim_dma_lock(); 567 clear_dma_ff(priv->dma_channel); 568 disable_dma(priv->dma_channel); 569 count += length - get_dma_residue(priv->dma_channel); 570 release_dma_lock(flags); 571 572 return retval ? retval : count; 573 } 574 575 static ssize_t dma_read(struct gpib_board *board, struct nec7210_priv *priv, u8 *buffer, 576 size_t length) 577 { 578 size_t remain = length; 579 size_t transfer_size; 580 ssize_t retval = 0; 581 582 while (remain > 0) { 583 transfer_size = (priv->dma_buffer_length < remain) ? 584 priv->dma_buffer_length : remain; 585 retval = __dma_read(board, priv, transfer_size); 586 if (retval < 0) 587 break; 588 memcpy(buffer, priv->dma_buffer, transfer_size); 589 remain -= retval; 590 buffer += retval; 591 if (test_bit(RECEIVED_END_BN, &priv->state)) 592 break; 593 } 594 595 if (retval < 0) 596 return retval; 597 598 return length - remain; 599 } 600 #endif 601 602 int nec7210_read(struct gpib_board *board, struct nec7210_priv *priv, u8 *buffer, 603 size_t length, int *end, size_t *bytes_read) 604 { 605 ssize_t retval = 0; 606 607 *end = 0; 608 *bytes_read = 0; 609 610 if (length == 0) 611 return 0; 612 613 clear_bit(DEV_CLEAR_BN, &priv->state); // XXX wrong 614 615 nec7210_release_rfd_holdoff(board, priv); 616 617 retval = pio_read(board, priv, buffer, length, end, bytes_read); 618 619 return retval; 620 } 621 EXPORT_SYMBOL(nec7210_read); 622 623 static int pio_write_wait(struct gpib_board *board, struct nec7210_priv *priv, 624 short wake_on_lacs, short wake_on_atn, short wake_on_bus_error) 625 { 626 // wait until byte is ready to be sent 627 if (wait_event_interruptible(board->wait, 628 (test_bit(TACS_NUM, &board->status) && 629 test_bit(WRITE_READY_BN, &priv->state)) || 630 test_bit(DEV_CLEAR_BN, &priv->state) || 631 (wake_on_bus_error && test_bit(BUS_ERROR_BN, &priv->state)) || 632 (wake_on_lacs && test_bit(LACS_NUM, &board->status)) || 633 (wake_on_atn && test_bit(ATN_NUM, &board->status)) || 634 test_bit(TIMO_NUM, &board->status))) 635 return -ERESTARTSYS; 636 637 if (test_bit(TIMO_NUM, &board->status)) 638 return -ETIMEDOUT; 639 640 if (test_bit(DEV_CLEAR_BN, &priv->state)) 641 return -EINTR; 642 643 if (wake_on_bus_error && test_and_clear_bit(BUS_ERROR_BN, &priv->state)) 644 return -EIO; 645 646 return 0; 647 } 648 649 static int pio_write(struct gpib_board *board, struct nec7210_priv *priv, u8 *buffer, 650 size_t length, size_t *bytes_written) 651 { 652 size_t last_count = 0; 653 ssize_t retval = 0; 654 unsigned long flags; 655 const int max_bus_errors = (length > 1000) ? length : 1000; 656 int bus_error_count = 0; 657 *bytes_written = 0; 658 659 clear_bit(BUS_ERROR_BN, &priv->state); 660 661 while (*bytes_written < length) { 662 if (need_resched()) 663 schedule(); 664 665 retval = pio_write_wait(board, priv, 0, 0, priv->type == NEC7210); 666 if (retval == -EIO) { 667 /* resend last byte on bus error */ 668 *bytes_written = last_count; 669 /* 670 * we can get unrecoverable bus errors, 671 * so give up after a while 672 */ 673 bus_error_count++; 674 if (bus_error_count > max_bus_errors) 675 return retval; 676 continue; 677 } else { 678 if (retval < 0) 679 return retval; 680 } 681 spin_lock_irqsave(&board->spinlock, flags); 682 clear_bit(BUS_ERROR_BN, &priv->state); 683 clear_bit(WRITE_READY_BN, &priv->state); 684 last_count = *bytes_written; 685 write_byte(priv, buffer[(*bytes_written)++], CDOR); 686 spin_unlock_irqrestore(&board->spinlock, flags); 687 } 688 retval = pio_write_wait(board, priv, 1, 1, priv->type == NEC7210); 689 return retval; 690 } 691 692 #ifdef NEC_DMA 693 static ssize_t __dma_write(struct gpib_board *board, struct nec7210_priv *priv, dma_addr_t address, 694 size_t length) 695 { 696 unsigned long flags, dma_irq_flags; 697 int residue = 0; 698 int retval = 0; 699 700 spin_lock_irqsave(&board->spinlock, flags); 701 702 /* program dma controller */ 703 dma_irq_flags = claim_dma_lock(); 704 disable_dma(priv->dma_channel); 705 clear_dma_ff(priv->dma_channel); 706 set_dma_count(priv->dma_channel, length); 707 set_dma_addr(priv->dma_channel, address); 708 set_dma_mode(priv->dma_channel, DMA_MODE_WRITE); 709 enable_dma(priv->dma_channel); 710 release_dma_lock(dma_irq_flags); 711 712 // enable board's dma for output 713 nec7210_set_reg_bits(priv, IMR2, HR_DMAO, HR_DMAO); 714 715 clear_bit(WRITE_READY_BN, &priv->state); 716 set_bit(DMA_WRITE_IN_PROGRESS_BN, &priv->state); 717 718 spin_unlock_irqrestore(&board->spinlock, flags); 719 720 // suspend until message is sent 721 if (wait_event_interruptible(board->wait, 722 test_bit(DMA_WRITE_IN_PROGRESS_BN, &priv->state) == 0 || 723 test_bit(BUS_ERROR_BN, &priv->state) || 724 test_bit(DEV_CLEAR_BN, &priv->state) || 725 test_bit(TIMO_NUM, &board->status))) 726 retval = -ERESTARTSYS; 727 728 if (test_bit(TIMO_NUM, &board->status)) 729 retval = -ETIMEDOUT; 730 if (test_and_clear_bit(DEV_CLEAR_BN, &priv->state)) 731 retval = -EINTR; 732 if (test_and_clear_bit(BUS_ERROR_BN, &priv->state)) 733 retval = -EIO; 734 735 // disable board's dma 736 nec7210_set_reg_bits(priv, IMR2, HR_DMAO, 0); 737 738 dma_irq_flags = claim_dma_lock(); 739 clear_dma_ff(priv->dma_channel); 740 disable_dma(priv->dma_channel); 741 residue = get_dma_residue(priv->dma_channel); 742 release_dma_lock(dma_irq_flags); 743 744 if (residue) 745 retval = -EPIPE; 746 747 return retval ? retval : length; 748 } 749 750 static ssize_t dma_write(struct gpib_board *board, struct nec7210_priv *priv, u8 *buffer, 751 size_t length) 752 { 753 size_t remain = length; 754 size_t transfer_size; 755 ssize_t retval = 0; 756 757 while (remain > 0) { 758 transfer_size = (priv->dma_buffer_length < remain) ? 759 priv->dma_buffer_length : remain; 760 memcpy(priv->dma_buffer, buffer, transfer_size); 761 retval = __dma_write(board, priv, priv->dma_buffer_addr, transfer_size); 762 if (retval < 0) 763 break; 764 remain -= retval; 765 buffer += retval; 766 } 767 768 if (retval < 0) 769 return retval; 770 771 return length - remain; 772 } 773 #endif 774 int nec7210_write(struct gpib_board *board, struct nec7210_priv *priv, 775 u8 *buffer, size_t length, int send_eoi, 776 size_t *bytes_written) 777 { 778 int retval = 0; 779 780 *bytes_written = 0; 781 782 clear_bit(DEV_CLEAR_BN, &priv->state); // XXX 783 784 if (send_eoi) 785 length-- ; // save the last byte for sending EOI 786 787 if (length > 0) { 788 // isa dma transfer 789 if (0 /*priv->dma_channel*/) { 790 /* 791 * dma writes are unreliable since they can't recover from bus errors 792 * (which happen when ATN is asserted in the middle of a write) 793 */ 794 #ifdef NEC_DMA 795 retval = dma_write(board, priv, buffer, length); 796 if (retval < 0) 797 return retval; 798 count += retval; 799 #endif 800 } else { // PIO transfer 801 size_t num_bytes; 802 803 retval = pio_write(board, priv, buffer, length, &num_bytes); 804 805 *bytes_written += num_bytes; 806 if (retval < 0) 807 return retval; 808 } 809 } 810 if (send_eoi) { 811 size_t num_bytes; 812 813 /* 814 * We need to wait to make sure we will immediately be able to write the data byte 815 * into the chip before sending the associated AUX_SEOI command. This is really 816 * only needed for length==1 since otherwise the earlier calls to pio_write 817 * will have dont the wait already. 818 */ 819 retval = pio_write_wait(board, priv, 0, 0, priv->type == NEC7210); 820 if (retval < 0) 821 return retval; 822 /*send EOI */ 823 write_byte(priv, AUX_SEOI, AUXMR); 824 825 retval = pio_write(board, priv, &buffer[*bytes_written], 1, &num_bytes); 826 *bytes_written += num_bytes; 827 if (retval < 0) 828 return retval; 829 } 830 831 return retval; 832 } 833 EXPORT_SYMBOL(nec7210_write); 834 835 /* 836 * interrupt service routine 837 */ 838 irqreturn_t nec7210_interrupt(struct gpib_board *board, struct nec7210_priv *priv) 839 { 840 int status1, status2; 841 842 // read interrupt status (also clears status) 843 status1 = read_byte(priv, ISR1); 844 status2 = read_byte(priv, ISR2); 845 846 return nec7210_interrupt_have_status(board, priv, status1, status2); 847 } 848 EXPORT_SYMBOL(nec7210_interrupt); 849 850 irqreturn_t nec7210_interrupt_have_status(struct gpib_board *board, 851 struct nec7210_priv *priv, int status1, int status2) 852 { 853 #ifdef NEC_DMA 854 unsigned long dma_flags; 855 #endif 856 int retval = IRQ_NONE; 857 858 // record service request in status 859 if (status2 & HR_SRQI) 860 set_bit(SRQI_NUM, &board->status); 861 862 // change in lockout status 863 if (status2 & HR_LOKC) { 864 if (status2 & HR_LOK) 865 set_bit(LOK_NUM, &board->status); 866 else 867 clear_bit(LOK_NUM, &board->status); 868 } 869 870 // change in remote status 871 if (status2 & HR_REMC) { 872 if (status2 & HR_REM) 873 set_bit(REM_NUM, &board->status); 874 else 875 clear_bit(REM_NUM, &board->status); 876 } 877 878 // record reception of END 879 if (status1 & HR_END) { 880 set_bit(RECEIVED_END_BN, &priv->state); 881 if ((priv->auxa_bits & HR_HANDSHAKE_MASK) == HR_HLDE) 882 set_bit(RFD_HOLDOFF_BN, &priv->state); 883 } 884 885 // get incoming data in PIO mode 886 if ((status1 & HR_DI)) { 887 set_bit(READ_READY_BN, &priv->state); 888 if ((priv->auxa_bits & HR_HANDSHAKE_MASK) == HR_HLDA) 889 set_bit(RFD_HOLDOFF_BN, &priv->state); 890 } 891 #ifdef NEC_DMA 892 // check for dma read transfer complete 893 if (test_bit(DMA_READ_IN_PROGRESS_BN, &priv->state)) { 894 dma_flags = claim_dma_lock(); 895 disable_dma(priv->dma_channel); 896 clear_dma_ff(priv->dma_channel); 897 if ((status1 & HR_END) || get_dma_residue(priv->dma_channel) == 0) 898 clear_bit(DMA_READ_IN_PROGRESS_BN, &priv->state); 899 else 900 enable_dma(priv->dma_channel); 901 release_dma_lock(dma_flags); 902 } 903 #endif 904 if ((status1 & HR_DO)) { 905 if (test_bit(DMA_WRITE_IN_PROGRESS_BN, &priv->state) == 0) 906 set_bit(WRITE_READY_BN, &priv->state); 907 #ifdef NEC_DMA 908 if (test_bit(DMA_WRITE_IN_PROGRESS_BN, &priv->state)) { // write data, isa dma mode 909 // check if dma transfer is complete 910 dma_flags = claim_dma_lock(); 911 disable_dma(priv->dma_channel); 912 clear_dma_ff(priv->dma_channel); 913 if (get_dma_residue(priv->dma_channel) == 0) { 914 clear_bit(DMA_WRITE_IN_PROGRESS_BN, &priv->state); 915 // XXX race? byte may still be in CDOR reg 916 } else { 917 clear_bit(WRITE_READY_BN, &priv->state); 918 enable_dma(priv->dma_channel); 919 } 920 release_dma_lock(dma_flags); 921 } 922 #endif 923 } 924 925 // outgoing command can be sent 926 if (status2 & HR_CO) 927 set_bit(COMMAND_READY_BN, &priv->state); 928 929 // command pass through received 930 if (status1 & HR_CPT) 931 write_byte(priv, AUX_NVAL, AUXMR); 932 933 if (status1 & HR_ERR) 934 set_bit(BUS_ERROR_BN, &priv->state); 935 936 if (status1 & HR_DEC) { 937 unsigned short address_status_bits = read_byte(priv, ADSR); 938 939 // ignore device clear events if we are controller in charge 940 if ((address_status_bits & HR_CIC) == 0) { 941 push_gpib_event(board, EVENT_DEV_CLR); 942 set_bit(DEV_CLEAR_BN, &priv->state); 943 } 944 } 945 946 if (status1 & HR_DET) 947 push_gpib_event(board, EVENT_DEV_TRG); 948 949 // Addressing status has changed 950 if (status2 & HR_ADSC) 951 set_bit(ADR_CHANGE_BN, &priv->state); 952 953 if ((status1 & priv->reg_bits[IMR1]) || 954 (status2 & (priv->reg_bits[IMR2] & IMR2_ENABLE_INTR_MASK)) || 955 nec7210_atn_has_changed(board, priv)) { 956 nec7210_update_status_nolock(board, priv); 957 dev_dbg(board->gpib_dev, "minor %i, stat %lx, isr1 0x%x, imr1 0x%x, isr2 0x%x, imr2 0x%x\n", 958 board->minor, board->status, status1, priv->reg_bits[IMR1], status2, 959 priv->reg_bits[IMR2]); 960 wake_up_interruptible(&board->wait); /* wake up sleeping process */ 961 retval = IRQ_HANDLED; 962 } 963 964 return retval; 965 } 966 EXPORT_SYMBOL(nec7210_interrupt_have_status); 967 968 void nec7210_board_reset(struct nec7210_priv *priv, const struct gpib_board *board) 969 { 970 /* 7210 chip reset */ 971 write_byte(priv, AUX_CR, AUXMR); 972 973 /* disable all interrupts */ 974 priv->reg_bits[IMR1] = 0; 975 write_byte(priv, priv->reg_bits[IMR1], IMR1); 976 priv->reg_bits[IMR2] = 0; 977 write_byte(priv, priv->reg_bits[IMR2], IMR2); 978 write_byte(priv, 0, SPMR); 979 980 /* clear registers by reading */ 981 read_byte(priv, CPTR); 982 read_byte(priv, ISR1); 983 read_byte(priv, ISR2); 984 985 /* parallel poll unconfigure */ 986 write_byte(priv, PPR | HR_PPU, AUXMR); 987 988 priv->reg_bits[ADMR] = HR_TRM0 | HR_TRM1; 989 990 priv->auxa_bits = AUXRA | HR_HLDA; 991 write_byte(priv, priv->auxa_bits, AUXMR); 992 993 write_byte(priv, AUXRE | 0, AUXMR); 994 995 /* set INT pin to active high, enable command pass through of unknown commands */ 996 priv->auxb_bits = AUXRB | HR_CPTE; 997 write_byte(priv, priv->auxb_bits, AUXMR); 998 write_byte(priv, AUXRE, AUXMR); 999 } 1000 EXPORT_SYMBOL(nec7210_board_reset); 1001 1002 void nec7210_board_online(struct nec7210_priv *priv, const struct gpib_board *board) 1003 { 1004 /* set GPIB address */ 1005 nec7210_primary_address(board, priv, board->pad); 1006 nec7210_secondary_address(board, priv, board->sad, board->sad >= 0); 1007 1008 /* enable interrupts */ 1009 priv->reg_bits[IMR1] = HR_ERRIE | HR_DECIE | HR_ENDIE | 1010 HR_DETIE | HR_CPTIE | HR_DOIE | HR_DIIE; 1011 priv->reg_bits[IMR2] = IMR2_ENABLE_INTR_MASK; 1012 write_byte(priv, priv->reg_bits[IMR1], IMR1); 1013 write_byte(priv, priv->reg_bits[IMR2], IMR2); 1014 1015 write_byte(priv, AUX_PON, AUXMR); 1016 } 1017 EXPORT_SYMBOL(nec7210_board_online); 1018 1019 #ifdef CONFIG_HAS_IOPORT 1020 /* wrappers for io */ 1021 u8 nec7210_ioport_read_byte(struct nec7210_priv *priv, unsigned int register_num) 1022 { 1023 return inb(priv->iobase + register_num * priv->offset); 1024 } 1025 EXPORT_SYMBOL(nec7210_ioport_read_byte); 1026 1027 void nec7210_ioport_write_byte(struct nec7210_priv *priv, u8 data, unsigned int register_num) 1028 { 1029 if (register_num == AUXMR) 1030 /* 1031 * locking makes absolutely sure noone accesses the 1032 * AUXMR register faster than once per microsecond 1033 */ 1034 nec7210_locking_ioport_write_byte(priv, data, register_num); 1035 else 1036 outb(data, priv->iobase + register_num * priv->offset); 1037 } 1038 EXPORT_SYMBOL(nec7210_ioport_write_byte); 1039 1040 /* locking variants of io wrappers, for chips that page-in registers */ 1041 u8 nec7210_locking_ioport_read_byte(struct nec7210_priv *priv, unsigned int register_num) 1042 { 1043 u8 retval; 1044 unsigned long flags; 1045 1046 spin_lock_irqsave(&priv->register_page_lock, flags); 1047 retval = inb(priv->iobase + register_num * priv->offset); 1048 spin_unlock_irqrestore(&priv->register_page_lock, flags); 1049 return retval; 1050 } 1051 EXPORT_SYMBOL(nec7210_locking_ioport_read_byte); 1052 1053 void nec7210_locking_ioport_write_byte(struct nec7210_priv *priv, u8 data, 1054 unsigned int register_num) 1055 { 1056 unsigned long flags; 1057 1058 spin_lock_irqsave(&priv->register_page_lock, flags); 1059 if (register_num == AUXMR) 1060 udelay(1); 1061 outb(data, priv->iobase + register_num * priv->offset); 1062 spin_unlock_irqrestore(&priv->register_page_lock, flags); 1063 } 1064 EXPORT_SYMBOL(nec7210_locking_ioport_write_byte); 1065 #endif 1066 1067 u8 nec7210_iomem_read_byte(struct nec7210_priv *priv, unsigned int register_num) 1068 { 1069 return readb(priv->mmiobase + register_num * priv->offset); 1070 } 1071 EXPORT_SYMBOL(nec7210_iomem_read_byte); 1072 1073 void nec7210_iomem_write_byte(struct nec7210_priv *priv, u8 data, unsigned int register_num) 1074 { 1075 if (register_num == AUXMR) 1076 /* 1077 * locking makes absolutely sure noone accesses the 1078 * AUXMR register faster than once per microsecond 1079 */ 1080 nec7210_locking_iomem_write_byte(priv, data, register_num); 1081 else 1082 writeb(data, priv->mmiobase + register_num * priv->offset); 1083 } 1084 EXPORT_SYMBOL(nec7210_iomem_write_byte); 1085 1086 u8 nec7210_locking_iomem_read_byte(struct nec7210_priv *priv, unsigned int register_num) 1087 { 1088 u8 retval; 1089 unsigned long flags; 1090 1091 spin_lock_irqsave(&priv->register_page_lock, flags); 1092 retval = readb(priv->mmiobase + register_num * priv->offset); 1093 spin_unlock_irqrestore(&priv->register_page_lock, flags); 1094 return retval; 1095 } 1096 EXPORT_SYMBOL(nec7210_locking_iomem_read_byte); 1097 1098 void nec7210_locking_iomem_write_byte(struct nec7210_priv *priv, u8 data, 1099 unsigned int register_num) 1100 { 1101 unsigned long flags; 1102 1103 spin_lock_irqsave(&priv->register_page_lock, flags); 1104 if (register_num == AUXMR) 1105 udelay(1); 1106 writeb(data, priv->mmiobase + register_num * priv->offset); 1107 spin_unlock_irqrestore(&priv->register_page_lock, flags); 1108 } 1109 EXPORT_SYMBOL(nec7210_locking_iomem_write_byte); 1110 1111 static int __init nec7210_init_module(void) 1112 { 1113 return 0; 1114 } 1115 1116 static void __exit nec7210_exit_module(void) 1117 { 1118 } 1119 1120 module_init(nec7210_init_module); 1121 module_exit(nec7210_exit_module); 1122