1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /*************************************************************************** 4 * Header for ines GPIB boards 5 * copyright : (C) 2002 by Frank Mori Hess 6 ***************************************************************************/ 7 8 #ifndef _INES_GPIB_H 9 #define _INES_GPIB_H 10 11 #include "nec7210.h" 12 #include "gpibP.h" 13 #include "plx9050.h" 14 #include "amcc5920.h" 15 #include "quancom_pci.h" 16 #include <linux/interrupt.h> 17 18 enum ines_pci_chip { 19 PCI_CHIP_NONE, 20 PCI_CHIP_PLX9050, 21 PCI_CHIP_AMCC5920, 22 PCI_CHIP_QUANCOM, 23 PCI_CHIP_QUICKLOGIC5030, 24 }; 25 26 struct ines_priv { 27 struct nec7210_priv nec7210_priv; 28 struct pci_dev *pci_device; 29 // base address for plx9052 pci chip 30 unsigned long plx_iobase; 31 // base address for amcc5920 pci chip 32 unsigned long amcc_iobase; 33 unsigned int irq; 34 enum ines_pci_chip pci_chip_type; 35 u8 extend_mode_bits; 36 }; 37 38 /* inb/outb wrappers */ 39 static inline unsigned int ines_inb(struct ines_priv *priv, unsigned int register_number) 40 { 41 return inb(priv->nec7210_priv.iobase + 42 register_number * priv->nec7210_priv.offset); 43 } 44 45 static inline void ines_outb(struct ines_priv *priv, unsigned int value, 46 unsigned int register_number) 47 { 48 outb(value, priv->nec7210_priv.iobase + 49 register_number * priv->nec7210_priv.offset); 50 } 51 52 enum ines_regs { 53 // read 54 FIFO_STATUS = 0x8, 55 ISR3 = 0x9, 56 ISR4 = 0xa, 57 IN_FIFO_COUNT = 0x10, 58 OUT_FIFO_COUNT = 0x11, 59 EXTEND_STATUS = 0xf, 60 61 // write 62 XDMA_CONTROL = 0x8, 63 IMR3 = ISR3, 64 IMR4 = ISR4, 65 IN_FIFO_WATERMARK = IN_FIFO_COUNT, 66 OUT_FIFO_WATERMARK = OUT_FIFO_COUNT, 67 EXTEND_MODE = 0xf, 68 69 // read-write 70 XFER_COUNT_LOWER = 0xb, 71 XFER_COUNT_UPPER = 0xc, 72 BUS_CONTROL_MONITOR = 0x13, 73 }; 74 75 enum isr3_imr3_bits { 76 HW_TIMEOUT_BIT = 0x1, 77 XFER_COUNT_BIT = 0x2, 78 CMD_RECEIVED_BIT = 0x4, 79 TCT_RECEIVED_BIT = 0x8, 80 IFC_ACTIVE_BIT = 0x10, 81 ATN_ACTIVE_BIT = 0x20, 82 FIFO_ERROR_BIT = 0x40, 83 }; 84 85 enum isr4_imr4_bits { 86 IN_FIFO_WATERMARK_BIT = 0x1, 87 OUT_FIFO_WATERMARK_BIT = 0x2, 88 IN_FIFO_FULL_BIT = 0x4, 89 OUT_FIFO_EMPTY_BIT = 0x8, 90 IN_FIFO_READY_BIT = 0x10, 91 OUT_FIFO_READY_BIT = 0x20, 92 IN_FIFO_EXIT_WATERMARK_BIT = 0x40, 93 OUT_FIFO_EXIT_WATERMARK_BIT = 0x80, 94 }; 95 96 enum extend_mode_bits { 97 TR3_TRIG_ENABLE_BIT = 0x1, // enable generation of trigger pulse T/R3 pin 98 // clear message available status bit when chip writes byte with EOI true 99 MAV_ENABLE_BIT = 0x2, 100 EOS1_ENABLE_BIT = 0x4, // enable eos register 1 101 EOS2_ENABLE_BIT = 0x8, // enable eos register 2 102 EOIDIS_BIT = 0x10, // disable EOI interrupt when doing rfd holdoff on end? 103 XFER_COUNTER_ENABLE_BIT = 0x20, 104 XFER_COUNTER_OUTPUT_BIT = 0x40, // use counter for output, clear for input 105 // when xfer counter hits 0, assert EOI on write or RFD holdoff on read 106 LAST_BYTE_HANDLING_BIT = 0x80, 107 }; 108 109 enum extend_status_bits { 110 OUTPUT_MESSAGE_IN_PROGRESS_BIT = 0x1, 111 SCSEL_BIT = 0x2, // statue of SCSEL pin 112 LISTEN_DISABLED = 0x4, 113 IN_FIFO_EMPTY_BIT = 0x8, 114 OUT_FIFO_FULL_BIT = 0x10, 115 }; 116 117 // ines adds fifo enable bits to address mode register 118 enum ines_admr_bits { 119 IN_FIFO_ENABLE_BIT = 0x8, 120 OUT_FIFO_ENABLE_BIT = 0x4, 121 }; 122 123 enum xdma_control_bits { 124 DMA_OUTPUT_BIT = 0x1, // use dma for output, clear for input 125 ENABLE_SYNC_DMA_BIT = 0x2, 126 DMA_ACCESS_EVERY_CYCLE = 0x4, // dma accesses fifo every cycle, clear for every other cycle 127 DMA_16BIT = 0x8, // clear for 8 bit transfers 128 }; 129 130 enum bus_control_monitor_bits { 131 BCM_DAV_BIT = 0x1, 132 BCM_NRFD_BIT = 0x2, 133 BCM_NDAC_BIT = 0x4, 134 BCM_IFC_BIT = 0x8, 135 BCM_ATN_BIT = 0x10, 136 BCM_SRQ_BIT = 0x20, 137 BCM_REN_BIT = 0x40, 138 BCM_EOI_BIT = 0x80, 139 }; 140 141 enum ines_aux_reg_bits { 142 INES_AUXD = 0x40, 143 }; 144 145 enum ines_aux_cmds { 146 INES_RFD_HLD_IMMEDIATE = 0x4, 147 INES_AUX_CLR_OUT_FIFO = 0x5, 148 INES_AUX_CLR_IN_FIFO = 0x6, 149 INES_AUX_XMODE = 0xa, 150 }; 151 152 enum ines_auxd_bits { 153 INES_FOLLOWING_T1_MASK = 0x3, 154 INES_FOLLOWING_T1_500ns = 0x0, 155 INES_FOLLOWING_T1_350ns = 0x1, 156 INES_FOLLOWING_T1_250ns = 0x2, 157 INES_INITIAL_TI_MASK = 0xc, 158 INES_INITIAL_T1_2000ns = 0x0, 159 INES_INITIAL_T1_1100ns = 0x4, 160 INES_INITIAL_T1_700ns = 0x8, 161 INES_T6_2us = 0x0, 162 INES_T6_50us = 0x10, 163 }; 164 165 #endif // _INES_GPIB_H 166