1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /*************************************************************************** 4 * Header for ines GPIB boards 5 * copyright : (C) 2002 by Frank Mori Hess 6 ***************************************************************************/ 7 8 #ifndef _INES_GPIB_H 9 #define _INES_GPIB_H 10 11 #include "nec7210.h" 12 #include "gpibP.h" 13 #include "plx9050.h" 14 #include "amcc5920.h" 15 #include "quancom_pci.h" 16 #include <linux/interrupt.h> 17 18 enum ines_pci_chip { 19 PCI_CHIP_NONE, 20 PCI_CHIP_PLX9050, 21 PCI_CHIP_AMCC5920, 22 PCI_CHIP_QUANCOM, 23 PCI_CHIP_QUICKLOGIC5030, 24 PCI_CHIP_INES_72130, 25 }; 26 27 struct ines_priv { 28 struct nec7210_priv nec7210_priv; 29 struct pci_dev *pci_device; 30 // base address for plx9052 pci chip 31 unsigned long plx_iobase; 32 // base address for amcc5920 pci chip 33 unsigned long amcc_iobase; 34 unsigned int irq; 35 enum ines_pci_chip pci_chip_type; 36 u8 extend_mode_bits; 37 }; 38 39 /* inb/outb wrappers */ 40 static inline unsigned int ines_inb(struct ines_priv *priv, unsigned int register_number) 41 { 42 return inb(priv->nec7210_priv.iobase + 43 register_number * priv->nec7210_priv.offset); 44 } 45 46 static inline void ines_outb(struct ines_priv *priv, unsigned int value, 47 unsigned int register_number) 48 { 49 outb(value, priv->nec7210_priv.iobase + 50 register_number * priv->nec7210_priv.offset); 51 } 52 53 enum ines_regs { 54 // read 55 FIFO_STATUS = 0x8, 56 ISR3 = 0x9, 57 ISR4 = 0xa, 58 IN_FIFO_COUNT = 0x10, 59 OUT_FIFO_COUNT = 0x11, 60 EXTEND_STATUS = 0xf, 61 62 // write 63 XDMA_CONTROL = 0x8, 64 IMR3 = ISR3, 65 IMR4 = ISR4, 66 IN_FIFO_WATERMARK = IN_FIFO_COUNT, 67 OUT_FIFO_WATERMARK = OUT_FIFO_COUNT, 68 EXTEND_MODE = 0xf, 69 70 // read-write 71 XFER_COUNT_LOWER = 0xb, 72 XFER_COUNT_UPPER = 0xc, 73 BUS_CONTROL_MONITOR = 0x13, 74 }; 75 76 enum isr3_imr3_bits { 77 HW_TIMEOUT_BIT = 0x1, 78 XFER_COUNT_BIT = 0x2, 79 CMD_RECEIVED_BIT = 0x4, 80 TCT_RECEIVED_BIT = 0x8, 81 IFC_ACTIVE_BIT = 0x10, 82 ATN_ACTIVE_BIT = 0x20, 83 FIFO_ERROR_BIT = 0x40, 84 }; 85 86 enum isr4_imr4_bits { 87 IN_FIFO_WATERMARK_BIT = 0x1, 88 OUT_FIFO_WATERMARK_BIT = 0x2, 89 IN_FIFO_FULL_BIT = 0x4, 90 OUT_FIFO_EMPTY_BIT = 0x8, 91 IN_FIFO_READY_BIT = 0x10, 92 OUT_FIFO_READY_BIT = 0x20, 93 IN_FIFO_EXIT_WATERMARK_BIT = 0x40, 94 OUT_FIFO_EXIT_WATERMARK_BIT = 0x80, 95 }; 96 97 enum extend_mode_bits { 98 TR3_TRIG_ENABLE_BIT = 0x1, // enable generation of trigger pulse T/R3 pin 99 // clear message available status bit when chip writes byte with EOI true 100 MAV_ENABLE_BIT = 0x2, 101 EOS1_ENABLE_BIT = 0x4, // enable eos register 1 102 EOS2_ENABLE_BIT = 0x8, // enable eos register 2 103 EOIDIS_BIT = 0x10, // disable EOI interrupt when doing rfd holdoff on end? 104 XFER_COUNTER_ENABLE_BIT = 0x20, 105 XFER_COUNTER_OUTPUT_BIT = 0x40, // use counter for output, clear for input 106 // when xfer counter hits 0, assert EOI on write or RFD holdoff on read 107 LAST_BYTE_HANDLING_BIT = 0x80, 108 }; 109 110 enum extend_status_bits { 111 OUTPUT_MESSAGE_IN_PROGRESS_BIT = 0x1, 112 SCSEL_BIT = 0x2, // statue of SCSEL pin 113 LISTEN_DISABLED = 0x4, 114 IN_FIFO_EMPTY_BIT = 0x8, 115 OUT_FIFO_FULL_BIT = 0x10, 116 }; 117 118 // ines adds fifo enable bits to address mode register 119 enum ines_admr_bits { 120 IN_FIFO_ENABLE_BIT = 0x8, 121 OUT_FIFO_ENABLE_BIT = 0x4, 122 }; 123 124 enum xdma_control_bits { 125 DMA_OUTPUT_BIT = 0x1, // use dma for output, clear for input 126 ENABLE_SYNC_DMA_BIT = 0x2, 127 DMA_ACCESS_EVERY_CYCLE = 0x4, // dma accesses fifo every cycle, clear for every other cycle 128 DMA_16BIT = 0x8, // clear for 8 bit transfers 129 }; 130 131 enum bus_control_monitor_bits { 132 BCM_DAV_BIT = 0x1, 133 BCM_NRFD_BIT = 0x2, 134 BCM_NDAC_BIT = 0x4, 135 BCM_IFC_BIT = 0x8, 136 BCM_ATN_BIT = 0x10, 137 BCM_SRQ_BIT = 0x20, 138 BCM_REN_BIT = 0x40, 139 BCM_EOI_BIT = 0x80, 140 }; 141 142 enum ines_aux_reg_bits { 143 INES_AUXD = 0x40, 144 }; 145 146 enum ines_aux_cmds { 147 INES_RFD_HLD_IMMEDIATE = 0x4, 148 INES_AUX_CLR_OUT_FIFO = 0x5, 149 INES_AUX_CLR_IN_FIFO = 0x6, 150 INES_AUX_XMODE = 0xa, 151 }; 152 153 enum ines_auxd_bits { 154 INES_FOLLOWING_T1_MASK = 0x3, 155 INES_FOLLOWING_T1_500ns = 0x0, 156 INES_FOLLOWING_T1_350ns = 0x1, 157 INES_FOLLOWING_T1_250ns = 0x2, 158 INES_INITIAL_TI_MASK = 0xc, 159 INES_INITIAL_T1_2000ns = 0x0, 160 INES_INITIAL_T1_1100ns = 0x4, 161 INES_INITIAL_T1_700ns = 0x8, 162 INES_T6_2us = 0x0, 163 INES_T6_50us = 0x10, 164 }; 165 166 enum ines72130_regs { 167 BUS_STATUS_REG = 0xc, 168 }; 169 170 enum ines_72130_bus_status_bits { 171 BSR_NRFD_BIT = 0x1, 172 BSR_NDAC_BIT = 0x2, 173 BSR_DAV_BIT = 0x4, 174 BSR_EOI_BIT = 0x8, 175 BSR_SRQ_BIT = 0x10, 176 BSR_ATN_BIT = 0x20, 177 BSR_REN_BIT = 0x40, 178 BSR_IFC_BIT = 0x80, 179 }; 180 181 #endif // _INES_GPIB_H 182