1*e6ab5046SDave Penkler /* SPDX-License-Identifier: GPL-2.0 */
2*e6ab5046SDave Penkler
3*e6ab5046SDave Penkler /***************************************************************************
4*e6ab5046SDave Penkler * Header for plx9050 pci chip
5*e6ab5046SDave Penkler * copyright : (C) 2002 by Frank Mori Hess
6*e6ab5046SDave Penkler ***************************************************************************/
7*e6ab5046SDave Penkler
8*e6ab5046SDave Penkler #ifndef _PLX9050_GPIB_H
9*e6ab5046SDave Penkler #define _PLX9050_GPIB_H
10*e6ab5046SDave Penkler
11*e6ab5046SDave Penkler // plx pci chip registers and bits
12*e6ab5046SDave Penkler enum {
13*e6ab5046SDave Penkler PLX9050_INTCSR_REG = 0x4c,
14*e6ab5046SDave Penkler PLX9050_CNTRL_REG = 0x50
15*e6ab5046SDave Penkler };
16*e6ab5046SDave Penkler
17*e6ab5046SDave Penkler enum plx9050_intcsr_bits {
18*e6ab5046SDave Penkler PLX9050_LINTR1_EN_BIT = 0x1,
19*e6ab5046SDave Penkler PLX9050_LINTR1_POLARITY_BIT = 0x2,
20*e6ab5046SDave Penkler PLX9050_LINTR1_STATUS_BIT = 0x4,
21*e6ab5046SDave Penkler PLX9050_LINTR2_EN_BIT = 0x8,
22*e6ab5046SDave Penkler PLX9050_LINTR2_POLARITY_BIT = 0x10,
23*e6ab5046SDave Penkler PLX9050_LINTR2_STATUS_BIT = 0x20,
24*e6ab5046SDave Penkler PLX9050_PCI_INTR_EN_BIT = 0x40,
25*e6ab5046SDave Penkler PLX9050_SOFT_INTR_BIT = 0x80,
26*e6ab5046SDave Penkler PLX9050_LINTR1_SELECT_ENABLE_BIT = 0x100, // 9052 extension
27*e6ab5046SDave Penkler PLX9050_LINTR2_SELECT_ENABLE_BIT = 0x200, // 9052 extension
28*e6ab5046SDave Penkler PLX9050_LINTR1_EDGE_CLEAR_BIT = 0x400, // 9052 extension
29*e6ab5046SDave Penkler PLX9050_LINTR2_EDGE_CLEAR_BIT = 0x800, // 9052 extension
30*e6ab5046SDave Penkler };
31*e6ab5046SDave Penkler
32*e6ab5046SDave Penkler enum plx9050_cntrl_bits {
33*e6ab5046SDave Penkler PLX9050_WAITO_NOT_USER0_SELECT_BIT = 0x1,
34*e6ab5046SDave Penkler PLX9050_USER0_OUTPUT_BIT = 0x2,
35*e6ab5046SDave Penkler PLX9050_USER0_DATA_BIT = 0x4,
36*e6ab5046SDave Penkler PLX9050_LLOCK_NOT_USER1_SELECT_BIT = 0x8,
37*e6ab5046SDave Penkler PLX9050_USER1_OUTPUT_BIT = 0x10,
38*e6ab5046SDave Penkler PLX9050_USER1_DATA_BIT = 0x20,
39*e6ab5046SDave Penkler PLX9050_CS2_NOT_USER2_SELECT_BIT = 0x40,
40*e6ab5046SDave Penkler PLX9050_USER2_OUTPUT_BIT = 0x80,
41*e6ab5046SDave Penkler PLX9050_USER2_DATA_BIT = 0x100,
42*e6ab5046SDave Penkler PLX9050_CS3_NOT_USER3_SELECT_BIT = 0x200,
43*e6ab5046SDave Penkler PLX9050_USER3_OUTPUT_BIT = 0x400,
44*e6ab5046SDave Penkler PLX9050_USER3_DATA_BIT = 0x800,
45*e6ab5046SDave Penkler PLX9050_PCIBAR_ENABLE_MASK = 0x3000,
46*e6ab5046SDave Penkler PLX9050_PCIBAR_MEMORY_AND_IO_ENABLE_BITS = 0x0,
47*e6ab5046SDave Penkler PLX9050_PCIBAR_MEMORY_NO_IO_ENABLE_BITS = 0x1000,
48*e6ab5046SDave Penkler PLX9050_PCIBAR_IO_NO_MEMORY_ENABLE_BITS = 0x2000,
49*e6ab5046SDave Penkler PLX9050_PCIBAR_MEMORY_AND_IO_TOO_ENABLE_BITS = 0x3000,
50*e6ab5046SDave Penkler PLX9050_PCI_READ_MODE_BIT = 0x4000,
51*e6ab5046SDave Penkler PLX9050_PCI_READ_WITH_WRITE_FLUSH_MODE_BIT = 0x8000,
52*e6ab5046SDave Penkler PLX9050_PCI_READ_NO_FLUSH_MODE_BIT = 0x10000,
53*e6ab5046SDave Penkler PLX9050_PCI_READ_NO_WRITE_MODE_BIT = 0x20000,
54*e6ab5046SDave Penkler PLX9050_PCI_WRITE_MODE_BIT = 0x40000,
55*e6ab5046SDave Penkler PLX9050_PCI_RETRY_DELAY_MASK = 0x780000,
56*e6ab5046SDave Penkler PLX9050_DIRECT_SLAVE_LOCK_ENABLE_BIT = 0x800000,
57*e6ab5046SDave Penkler PLX9050_EEPROM_CLOCK_BIT = 0x1000000,
58*e6ab5046SDave Penkler PLX9050_EEPROM_CHIP_SELECT_BIT = 0x2000000,
59*e6ab5046SDave Penkler PLX9050_WRITE_TO_EEPROM_BIT = 0x4000000,
60*e6ab5046SDave Penkler PLX9050_READ_EEPROM_DATA_BIT = 0x8000000,
61*e6ab5046SDave Penkler PLX9050_EEPROM_VALID_BIT = 0x10000000,
62*e6ab5046SDave Penkler PLX9050_RELOAD_CONFIG_REGISTERS_BIT = 0x20000000,
63*e6ab5046SDave Penkler PLX9050_PCI_SOFTWARE_RESET_BIT = 0x40000000,
64*e6ab5046SDave Penkler PLX9050_MASK_REVISION_BIT = 0x80000000
65*e6ab5046SDave Penkler };
66*e6ab5046SDave Penkler
PLX9050_PCI_RETRY_DELAY_BITS(unsigned int clocks)67*e6ab5046SDave Penkler static inline unsigned int PLX9050_PCI_RETRY_DELAY_BITS(unsigned int clocks)
68*e6ab5046SDave Penkler {
69*e6ab5046SDave Penkler return ((clocks / 8) << 19) & PLX9050_PCI_RETRY_DELAY_MASK;
70*e6ab5046SDave Penkler }
71*e6ab5046SDave Penkler
72*e6ab5046SDave Penkler #endif // _PLX9050_GPIB_H
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