1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * KUnit test for the FPGA Region 4 * 5 * Copyright (C) 2023 Red Hat, Inc. 6 * 7 * Author: Marco Pagani <marpagan@redhat.com> 8 */ 9 10 #include <kunit/test.h> 11 #include <linux/fpga/fpga-bridge.h> 12 #include <linux/fpga/fpga-mgr.h> 13 #include <linux/fpga/fpga-region.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/types.h> 17 18 struct mgr_stats { 19 u32 write_count; 20 }; 21 22 struct bridge_stats { 23 bool enable; 24 u32 cycles_count; 25 }; 26 27 struct test_ctx { 28 struct fpga_manager *mgr; 29 struct platform_device *mgr_pdev; 30 struct fpga_bridge *bridge; 31 struct platform_device *bridge_pdev; 32 struct fpga_region *region; 33 struct platform_device *region_pdev; 34 struct bridge_stats bridge_stats; 35 struct mgr_stats mgr_stats; 36 }; 37 38 static int op_write(struct fpga_manager *mgr, const char *buf, size_t count) 39 { 40 struct mgr_stats *stats = mgr->priv; 41 42 stats->write_count++; 43 44 return 0; 45 } 46 47 /* 48 * Fake FPGA manager that implements only the write op to count the number 49 * of programming cycles. The internals of the programming sequence are 50 * tested in the Manager suite since they are outside the responsibility 51 * of the Region. 52 */ 53 static const struct fpga_manager_ops fake_mgr_ops = { 54 .write = op_write, 55 }; 56 57 static int op_enable_set(struct fpga_bridge *bridge, bool enable) 58 { 59 struct bridge_stats *stats = bridge->priv; 60 61 if (!stats->enable && enable) 62 stats->cycles_count++; 63 64 stats->enable = enable; 65 66 return 0; 67 } 68 69 /* 70 * Fake FPGA bridge that implements only enable_set op to count the number 71 * of activation cycles. 72 */ 73 static const struct fpga_bridge_ops fake_bridge_ops = { 74 .enable_set = op_enable_set, 75 }; 76 77 static int fake_region_get_bridges(struct fpga_region *region) 78 { 79 struct fpga_bridge *bridge = region->priv; 80 81 return fpga_bridge_get_to_list(bridge->dev.parent, region->info, ®ion->bridge_list); 82 } 83 84 static int fake_region_match(struct device *dev, const void *data) 85 { 86 return dev->parent == data; 87 } 88 89 static void fpga_region_test_class_find(struct kunit *test) 90 { 91 struct test_ctx *ctx = test->priv; 92 struct fpga_region *region; 93 94 region = fpga_region_class_find(NULL, &ctx->region_pdev->dev, fake_region_match); 95 KUNIT_EXPECT_PTR_EQ(test, region, ctx->region); 96 97 put_device(®ion->dev); 98 } 99 100 /* 101 * FPGA Region programming test. The Region must call get_bridges() to get 102 * and control the bridges, and then the Manager for the actual programming. 103 */ 104 static void fpga_region_test_program_fpga(struct kunit *test) 105 { 106 struct test_ctx *ctx = test->priv; 107 struct fpga_image_info *img_info; 108 char img_buf[4]; 109 int ret; 110 111 img_info = fpga_image_info_alloc(&ctx->mgr_pdev->dev); 112 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, img_info); 113 114 img_info->buf = img_buf; 115 img_info->count = sizeof(img_buf); 116 117 ctx->region->info = img_info; 118 ret = fpga_region_program_fpga(ctx->region); 119 KUNIT_ASSERT_EQ(test, ret, 0); 120 121 KUNIT_EXPECT_EQ(test, 1, ctx->mgr_stats.write_count); 122 KUNIT_EXPECT_EQ(test, 1, ctx->bridge_stats.cycles_count); 123 124 fpga_bridges_put(&ctx->region->bridge_list); 125 126 ret = fpga_region_program_fpga(ctx->region); 127 KUNIT_ASSERT_EQ(test, ret, 0); 128 129 KUNIT_EXPECT_EQ(test, 2, ctx->mgr_stats.write_count); 130 KUNIT_EXPECT_EQ(test, 2, ctx->bridge_stats.cycles_count); 131 132 fpga_bridges_put(&ctx->region->bridge_list); 133 134 fpga_image_info_free(img_info); 135 } 136 137 /* 138 * The configuration used in this test suite uses a single bridge to 139 * limit the code under test to a single unit. The functions used by the 140 * Region for getting and controlling bridges are tested (with a list of 141 * multiple bridges) in the Bridge suite. 142 */ 143 static int fpga_region_test_init(struct kunit *test) 144 { 145 struct test_ctx *ctx; 146 struct fpga_region_info region_info = { 0 }; 147 148 ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); 149 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx); 150 151 ctx->mgr_pdev = platform_device_register_simple("mgr_pdev", PLATFORM_DEVID_AUTO, NULL, 0); 152 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->mgr_pdev); 153 154 ctx->mgr = devm_fpga_mgr_register(&ctx->mgr_pdev->dev, "Fake FPGA Manager", &fake_mgr_ops, 155 &ctx->mgr_stats); 156 KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->mgr)); 157 158 ctx->bridge_pdev = platform_device_register_simple("bridge_pdev", PLATFORM_DEVID_AUTO, 159 NULL, 0); 160 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->bridge_pdev); 161 162 ctx->bridge = fpga_bridge_register(&ctx->bridge_pdev->dev, "Fake FPGA Bridge", 163 &fake_bridge_ops, &ctx->bridge_stats); 164 KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->bridge)); 165 166 ctx->bridge_stats.enable = true; 167 168 ctx->region_pdev = platform_device_register_simple("region_pdev", PLATFORM_DEVID_AUTO, 169 NULL, 0); 170 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->region_pdev); 171 172 region_info.mgr = ctx->mgr; 173 region_info.priv = ctx->bridge; 174 region_info.get_bridges = fake_region_get_bridges; 175 176 ctx->region = fpga_region_register_full(&ctx->region_pdev->dev, ®ion_info); 177 KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->region)); 178 179 test->priv = ctx; 180 181 return 0; 182 } 183 184 static void fpga_region_test_exit(struct kunit *test) 185 { 186 struct test_ctx *ctx = test->priv; 187 188 fpga_region_unregister(ctx->region); 189 platform_device_unregister(ctx->region_pdev); 190 191 fpga_bridge_unregister(ctx->bridge); 192 platform_device_unregister(ctx->bridge_pdev); 193 194 platform_device_unregister(ctx->mgr_pdev); 195 } 196 197 static struct kunit_case fpga_region_test_cases[] = { 198 KUNIT_CASE(fpga_region_test_class_find), 199 KUNIT_CASE(fpga_region_test_program_fpga), 200 201 {} 202 }; 203 204 static struct kunit_suite fpga_region_suite = { 205 .name = "fpga_mgr", 206 .init = fpga_region_test_init, 207 .exit = fpga_region_test_exit, 208 .test_cases = fpga_region_test_cases, 209 }; 210 211 kunit_test_suite(fpga_region_suite); 212 213 MODULE_LICENSE("GPL"); 214