1bdf86d0eSRuss Weight // SPDX-License-Identifier: GPL-2.0 2bdf86d0eSRuss Weight /* 3bdf86d0eSRuss Weight * Intel MAX10 Board Management Controller Secure Update Driver 4bdf86d0eSRuss Weight * 5bdf86d0eSRuss Weight * Copyright (C) 2019-2022 Intel Corporation. All rights reserved. 6bdf86d0eSRuss Weight * 7bdf86d0eSRuss Weight */ 8bdf86d0eSRuss Weight #include <linux/bitfield.h> 9bdf86d0eSRuss Weight #include <linux/device.h> 10bdf86d0eSRuss Weight #include <linux/firmware.h> 11bdf86d0eSRuss Weight #include <linux/mfd/intel-m10-bmc.h> 12bdf86d0eSRuss Weight #include <linux/mod_devicetable.h> 13bdf86d0eSRuss Weight #include <linux/module.h> 14bdf86d0eSRuss Weight #include <linux/platform_device.h> 15bdf86d0eSRuss Weight #include <linux/slab.h> 16bdf86d0eSRuss Weight 17bdf86d0eSRuss Weight struct m10bmc_sec { 18bdf86d0eSRuss Weight struct device *dev; 19bdf86d0eSRuss Weight struct intel_m10bmc *m10bmc; 205cd339b3SRuss Weight struct fw_upload *fwl; 215cd339b3SRuss Weight char *fw_name; 225cd339b3SRuss Weight u32 fw_name_id; 235cd339b3SRuss Weight bool cancel_request; 24bdf86d0eSRuss Weight }; 25bdf86d0eSRuss Weight 265cd339b3SRuss Weight static DEFINE_XARRAY_ALLOC(fw_upload_xa); 275cd339b3SRuss Weight 28bdf86d0eSRuss Weight /* Root Entry Hash (REH) support */ 29bdf86d0eSRuss Weight #define REH_SHA256_SIZE 32 30bdf86d0eSRuss Weight #define REH_SHA384_SIZE 48 31bdf86d0eSRuss Weight #define REH_MAGIC GENMASK(15, 0) 32bdf86d0eSRuss Weight #define REH_SHA_NUM_BYTES GENMASK(31, 16) 33bdf86d0eSRuss Weight 34bdf86d0eSRuss Weight static ssize_t 35bdf86d0eSRuss Weight show_root_entry_hash(struct device *dev, u32 exp_magic, 36bdf86d0eSRuss Weight u32 prog_addr, u32 reh_addr, char *buf) 37bdf86d0eSRuss Weight { 38bdf86d0eSRuss Weight struct m10bmc_sec *sec = dev_get_drvdata(dev); 39bdf86d0eSRuss Weight int sha_num_bytes, i, ret, cnt = 0; 40bdf86d0eSRuss Weight u8 hash[REH_SHA384_SIZE]; 41bdf86d0eSRuss Weight unsigned int stride; 42bdf86d0eSRuss Weight u32 magic; 43bdf86d0eSRuss Weight 44bdf86d0eSRuss Weight stride = regmap_get_reg_stride(sec->m10bmc->regmap); 45bdf86d0eSRuss Weight ret = m10bmc_raw_read(sec->m10bmc, prog_addr, &magic); 46bdf86d0eSRuss Weight if (ret) 47bdf86d0eSRuss Weight return ret; 48bdf86d0eSRuss Weight 49bdf86d0eSRuss Weight if (FIELD_GET(REH_MAGIC, magic) != exp_magic) 50bdf86d0eSRuss Weight return sysfs_emit(buf, "hash not programmed\n"); 51bdf86d0eSRuss Weight 52bdf86d0eSRuss Weight sha_num_bytes = FIELD_GET(REH_SHA_NUM_BYTES, magic) / 8; 53bdf86d0eSRuss Weight if ((sha_num_bytes % stride) || 54bdf86d0eSRuss Weight (sha_num_bytes != REH_SHA256_SIZE && 55bdf86d0eSRuss Weight sha_num_bytes != REH_SHA384_SIZE)) { 56bdf86d0eSRuss Weight dev_err(sec->dev, "%s bad sha num bytes %d\n", __func__, 57bdf86d0eSRuss Weight sha_num_bytes); 58bdf86d0eSRuss Weight return -EINVAL; 59bdf86d0eSRuss Weight } 60bdf86d0eSRuss Weight 61bdf86d0eSRuss Weight ret = regmap_bulk_read(sec->m10bmc->regmap, reh_addr, 62bdf86d0eSRuss Weight hash, sha_num_bytes / stride); 63bdf86d0eSRuss Weight if (ret) { 64bdf86d0eSRuss Weight dev_err(dev, "failed to read root entry hash: %x cnt %x: %d\n", 65bdf86d0eSRuss Weight reh_addr, sha_num_bytes / stride, ret); 66bdf86d0eSRuss Weight return ret; 67bdf86d0eSRuss Weight } 68bdf86d0eSRuss Weight 69bdf86d0eSRuss Weight for (i = 0; i < sha_num_bytes; i++) 70bdf86d0eSRuss Weight cnt += sprintf(buf + cnt, "%02x", hash[i]); 71bdf86d0eSRuss Weight cnt += sprintf(buf + cnt, "\n"); 72bdf86d0eSRuss Weight 73bdf86d0eSRuss Weight return cnt; 74bdf86d0eSRuss Weight } 75bdf86d0eSRuss Weight 76*6052a005SIlpo Järvinen #define DEVICE_ATTR_SEC_REH_RO(_name) \ 77bdf86d0eSRuss Weight static ssize_t _name##_root_entry_hash_show(struct device *dev, \ 78bdf86d0eSRuss Weight struct device_attribute *attr, \ 79bdf86d0eSRuss Weight char *buf) \ 80*6052a005SIlpo Järvinen { \ 81*6052a005SIlpo Järvinen struct m10bmc_sec *sec = dev_get_drvdata(dev); \ 82*6052a005SIlpo Järvinen const struct m10bmc_csr_map *csr_map = sec->m10bmc->info->csr_map; \ 83*6052a005SIlpo Järvinen \ 84*6052a005SIlpo Järvinen return show_root_entry_hash(dev, csr_map->_name##_magic, \ 85*6052a005SIlpo Järvinen csr_map->_name##_prog_addr, \ 86*6052a005SIlpo Järvinen csr_map->_name##_reh_addr, \ 87*6052a005SIlpo Järvinen buf); \ 88*6052a005SIlpo Järvinen } \ 89bdf86d0eSRuss Weight static DEVICE_ATTR_RO(_name##_root_entry_hash) 90bdf86d0eSRuss Weight 91*6052a005SIlpo Järvinen DEVICE_ATTR_SEC_REH_RO(bmc); 92*6052a005SIlpo Järvinen DEVICE_ATTR_SEC_REH_RO(sr); 93*6052a005SIlpo Järvinen DEVICE_ATTR_SEC_REH_RO(pr); 94bdf86d0eSRuss Weight 957f03d84aSRuss Weight #define CSK_BIT_LEN 128U 967f03d84aSRuss Weight #define CSK_32ARRAY_SIZE DIV_ROUND_UP(CSK_BIT_LEN, 32) 977f03d84aSRuss Weight 987f03d84aSRuss Weight static ssize_t 997f03d84aSRuss Weight show_canceled_csk(struct device *dev, u32 addr, char *buf) 1007f03d84aSRuss Weight { 1017f03d84aSRuss Weight unsigned int i, stride, size = CSK_32ARRAY_SIZE * sizeof(u32); 1027f03d84aSRuss Weight struct m10bmc_sec *sec = dev_get_drvdata(dev); 1037f03d84aSRuss Weight DECLARE_BITMAP(csk_map, CSK_BIT_LEN); 1047f03d84aSRuss Weight __le32 csk_le32[CSK_32ARRAY_SIZE]; 1057f03d84aSRuss Weight u32 csk32[CSK_32ARRAY_SIZE]; 1067f03d84aSRuss Weight int ret; 1077f03d84aSRuss Weight 1087f03d84aSRuss Weight stride = regmap_get_reg_stride(sec->m10bmc->regmap); 1097f03d84aSRuss Weight if (size % stride) { 1107f03d84aSRuss Weight dev_err(sec->dev, 1117f03d84aSRuss Weight "CSK vector size (0x%x) not aligned to stride (0x%x)\n", 1127f03d84aSRuss Weight size, stride); 1137f03d84aSRuss Weight WARN_ON_ONCE(1); 1147f03d84aSRuss Weight return -EINVAL; 1157f03d84aSRuss Weight } 1167f03d84aSRuss Weight 1177f03d84aSRuss Weight ret = regmap_bulk_read(sec->m10bmc->regmap, addr, csk_le32, 1187f03d84aSRuss Weight size / stride); 1197f03d84aSRuss Weight if (ret) { 1207f03d84aSRuss Weight dev_err(sec->dev, "failed to read CSK vector: %x cnt %x: %d\n", 1217f03d84aSRuss Weight addr, size / stride, ret); 1227f03d84aSRuss Weight return ret; 1237f03d84aSRuss Weight } 1247f03d84aSRuss Weight 1257f03d84aSRuss Weight for (i = 0; i < CSK_32ARRAY_SIZE; i++) 1267f03d84aSRuss Weight csk32[i] = le32_to_cpu(((csk_le32[i]))); 1277f03d84aSRuss Weight 1287f03d84aSRuss Weight bitmap_from_arr32(csk_map, csk32, CSK_BIT_LEN); 1297f03d84aSRuss Weight bitmap_complement(csk_map, csk_map, CSK_BIT_LEN); 1307f03d84aSRuss Weight return bitmap_print_to_pagebuf(1, buf, csk_map, CSK_BIT_LEN); 1317f03d84aSRuss Weight } 1327f03d84aSRuss Weight 133*6052a005SIlpo Järvinen #define DEVICE_ATTR_SEC_CSK_RO(_name) \ 1347f03d84aSRuss Weight static ssize_t _name##_canceled_csks_show(struct device *dev, \ 1357f03d84aSRuss Weight struct device_attribute *attr, \ 1367f03d84aSRuss Weight char *buf) \ 137*6052a005SIlpo Järvinen { \ 138*6052a005SIlpo Järvinen struct m10bmc_sec *sec = dev_get_drvdata(dev); \ 139*6052a005SIlpo Järvinen const struct m10bmc_csr_map *csr_map = sec->m10bmc->info->csr_map; \ 140*6052a005SIlpo Järvinen \ 141*6052a005SIlpo Järvinen return show_canceled_csk(dev, \ 142*6052a005SIlpo Järvinen csr_map->_name##_prog_addr + CSK_VEC_OFFSET, \ 143*6052a005SIlpo Järvinen buf); \ 144*6052a005SIlpo Järvinen } \ 1457f03d84aSRuss Weight static DEVICE_ATTR_RO(_name##_canceled_csks) 1467f03d84aSRuss Weight 1477f03d84aSRuss Weight #define CSK_VEC_OFFSET 0x34 1487f03d84aSRuss Weight 149*6052a005SIlpo Järvinen DEVICE_ATTR_SEC_CSK_RO(bmc); 150*6052a005SIlpo Järvinen DEVICE_ATTR_SEC_CSK_RO(sr); 151*6052a005SIlpo Järvinen DEVICE_ATTR_SEC_CSK_RO(pr); 1527f03d84aSRuss Weight 153154afa5cSRuss Weight #define FLASH_COUNT_SIZE 4096 /* count stored as inverted bit vector */ 154154afa5cSRuss Weight 155154afa5cSRuss Weight static ssize_t flash_count_show(struct device *dev, 156154afa5cSRuss Weight struct device_attribute *attr, char *buf) 157154afa5cSRuss Weight { 158154afa5cSRuss Weight struct m10bmc_sec *sec = dev_get_drvdata(dev); 159*6052a005SIlpo Järvinen const struct m10bmc_csr_map *csr_map = sec->m10bmc->info->csr_map; 160154afa5cSRuss Weight unsigned int stride, num_bits; 161154afa5cSRuss Weight u8 *flash_buf; 162154afa5cSRuss Weight int cnt, ret; 163154afa5cSRuss Weight 164154afa5cSRuss Weight stride = regmap_get_reg_stride(sec->m10bmc->regmap); 165154afa5cSRuss Weight num_bits = FLASH_COUNT_SIZE * 8; 166154afa5cSRuss Weight 167154afa5cSRuss Weight if (FLASH_COUNT_SIZE % stride) { 168154afa5cSRuss Weight dev_err(sec->dev, 169154afa5cSRuss Weight "FLASH_COUNT_SIZE (0x%x) not aligned to stride (0x%x)\n", 170154afa5cSRuss Weight FLASH_COUNT_SIZE, stride); 171154afa5cSRuss Weight WARN_ON_ONCE(1); 172154afa5cSRuss Weight return -EINVAL; 173154afa5cSRuss Weight } 174154afa5cSRuss Weight 175468c9d92SRuss Weight flash_buf = kmalloc(FLASH_COUNT_SIZE, GFP_KERNEL); 176468c9d92SRuss Weight if (!flash_buf) 177468c9d92SRuss Weight return -ENOMEM; 178468c9d92SRuss Weight 179*6052a005SIlpo Järvinen ret = regmap_bulk_read(sec->m10bmc->regmap, csr_map->rsu_update_counter, 180154afa5cSRuss Weight flash_buf, FLASH_COUNT_SIZE / stride); 181154afa5cSRuss Weight if (ret) { 182154afa5cSRuss Weight dev_err(sec->dev, 183154afa5cSRuss Weight "failed to read flash count: %x cnt %x: %d\n", 184*6052a005SIlpo Järvinen csr_map->rsu_update_counter, FLASH_COUNT_SIZE / stride, ret); 185154afa5cSRuss Weight goto exit_free; 186154afa5cSRuss Weight } 187154afa5cSRuss Weight cnt = num_bits - bitmap_weight((unsigned long *)flash_buf, num_bits); 188154afa5cSRuss Weight 189154afa5cSRuss Weight exit_free: 190154afa5cSRuss Weight kfree(flash_buf); 191154afa5cSRuss Weight 192154afa5cSRuss Weight return ret ? : sysfs_emit(buf, "%u\n", cnt); 193154afa5cSRuss Weight } 194154afa5cSRuss Weight static DEVICE_ATTR_RO(flash_count); 195154afa5cSRuss Weight 196bdf86d0eSRuss Weight static struct attribute *m10bmc_security_attrs[] = { 197154afa5cSRuss Weight &dev_attr_flash_count.attr, 198bdf86d0eSRuss Weight &dev_attr_bmc_root_entry_hash.attr, 199bdf86d0eSRuss Weight &dev_attr_sr_root_entry_hash.attr, 200bdf86d0eSRuss Weight &dev_attr_pr_root_entry_hash.attr, 2017f03d84aSRuss Weight &dev_attr_sr_canceled_csks.attr, 2027f03d84aSRuss Weight &dev_attr_pr_canceled_csks.attr, 2037f03d84aSRuss Weight &dev_attr_bmc_canceled_csks.attr, 204bdf86d0eSRuss Weight NULL, 205bdf86d0eSRuss Weight }; 206bdf86d0eSRuss Weight 207bdf86d0eSRuss Weight static struct attribute_group m10bmc_security_attr_group = { 208bdf86d0eSRuss Weight .name = "security", 209bdf86d0eSRuss Weight .attrs = m10bmc_security_attrs, 210bdf86d0eSRuss Weight }; 211bdf86d0eSRuss Weight 212bdf86d0eSRuss Weight static const struct attribute_group *m10bmc_sec_attr_groups[] = { 213bdf86d0eSRuss Weight &m10bmc_security_attr_group, 214bdf86d0eSRuss Weight NULL, 215bdf86d0eSRuss Weight }; 216bdf86d0eSRuss Weight 2175cd339b3SRuss Weight static void log_error_regs(struct m10bmc_sec *sec, u32 doorbell) 2185cd339b3SRuss Weight { 219*6052a005SIlpo Järvinen const struct m10bmc_csr_map *csr_map = sec->m10bmc->info->csr_map; 2205cd339b3SRuss Weight u32 auth_result; 2215cd339b3SRuss Weight 2225cd339b3SRuss Weight dev_err(sec->dev, "RSU error status: 0x%08x\n", doorbell); 2235cd339b3SRuss Weight 224*6052a005SIlpo Järvinen if (!m10bmc_sys_read(sec->m10bmc, csr_map->auth_result, &auth_result)) 2255cd339b3SRuss Weight dev_err(sec->dev, "RSU auth result: 0x%08x\n", auth_result); 2265cd339b3SRuss Weight } 2275cd339b3SRuss Weight 2285cd339b3SRuss Weight static enum fw_upload_err rsu_check_idle(struct m10bmc_sec *sec) 2295cd339b3SRuss Weight { 230*6052a005SIlpo Järvinen const struct m10bmc_csr_map *csr_map = sec->m10bmc->info->csr_map; 2315cd339b3SRuss Weight u32 doorbell; 2325cd339b3SRuss Weight int ret; 2335cd339b3SRuss Weight 234*6052a005SIlpo Järvinen ret = m10bmc_sys_read(sec->m10bmc, csr_map->doorbell, &doorbell); 2355cd339b3SRuss Weight if (ret) 2365cd339b3SRuss Weight return FW_UPLOAD_ERR_RW_ERROR; 2375cd339b3SRuss Weight 2385cd339b3SRuss Weight if (rsu_prog(doorbell) != RSU_PROG_IDLE && 2395cd339b3SRuss Weight rsu_prog(doorbell) != RSU_PROG_RSU_DONE) { 2405cd339b3SRuss Weight log_error_regs(sec, doorbell); 2415cd339b3SRuss Weight return FW_UPLOAD_ERR_BUSY; 2425cd339b3SRuss Weight } 2435cd339b3SRuss Weight 2445cd339b3SRuss Weight return FW_UPLOAD_ERR_NONE; 2455cd339b3SRuss Weight } 2465cd339b3SRuss Weight 2475cd339b3SRuss Weight static inline bool rsu_start_done(u32 doorbell) 2485cd339b3SRuss Weight { 2495cd339b3SRuss Weight u32 status, progress; 2505cd339b3SRuss Weight 2515cd339b3SRuss Weight if (doorbell & DRBL_RSU_REQUEST) 2525cd339b3SRuss Weight return false; 2535cd339b3SRuss Weight 2545cd339b3SRuss Weight status = rsu_stat(doorbell); 2555cd339b3SRuss Weight if (status == RSU_STAT_ERASE_FAIL || status == RSU_STAT_WEAROUT) 2565cd339b3SRuss Weight return true; 2575cd339b3SRuss Weight 2585cd339b3SRuss Weight progress = rsu_prog(doorbell); 2595cd339b3SRuss Weight if (progress != RSU_PROG_IDLE && progress != RSU_PROG_RSU_DONE) 2605cd339b3SRuss Weight return true; 2615cd339b3SRuss Weight 2625cd339b3SRuss Weight return false; 2635cd339b3SRuss Weight } 2645cd339b3SRuss Weight 2655cd339b3SRuss Weight static enum fw_upload_err rsu_update_init(struct m10bmc_sec *sec) 2665cd339b3SRuss Weight { 267*6052a005SIlpo Järvinen const struct m10bmc_csr_map *csr_map = sec->m10bmc->info->csr_map; 2685cd339b3SRuss Weight u32 doorbell, status; 2695cd339b3SRuss Weight int ret; 2705cd339b3SRuss Weight 2715cd339b3SRuss Weight ret = regmap_update_bits(sec->m10bmc->regmap, 272*6052a005SIlpo Järvinen csr_map->base + csr_map->doorbell, 2735cd339b3SRuss Weight DRBL_RSU_REQUEST | DRBL_HOST_STATUS, 2745cd339b3SRuss Weight DRBL_RSU_REQUEST | 2755cd339b3SRuss Weight FIELD_PREP(DRBL_HOST_STATUS, 2765cd339b3SRuss Weight HOST_STATUS_IDLE)); 2775cd339b3SRuss Weight if (ret) 2785cd339b3SRuss Weight return FW_UPLOAD_ERR_RW_ERROR; 2795cd339b3SRuss Weight 2805cd339b3SRuss Weight ret = regmap_read_poll_timeout(sec->m10bmc->regmap, 281*6052a005SIlpo Järvinen csr_map->base + csr_map->doorbell, 2825cd339b3SRuss Weight doorbell, 2835cd339b3SRuss Weight rsu_start_done(doorbell), 2845cd339b3SRuss Weight NIOS_HANDSHAKE_INTERVAL_US, 2855cd339b3SRuss Weight NIOS_HANDSHAKE_TIMEOUT_US); 2865cd339b3SRuss Weight 2875cd339b3SRuss Weight if (ret == -ETIMEDOUT) { 2885cd339b3SRuss Weight log_error_regs(sec, doorbell); 2895cd339b3SRuss Weight return FW_UPLOAD_ERR_TIMEOUT; 2905cd339b3SRuss Weight } else if (ret) { 2915cd339b3SRuss Weight return FW_UPLOAD_ERR_RW_ERROR; 2925cd339b3SRuss Weight } 2935cd339b3SRuss Weight 2945cd339b3SRuss Weight status = rsu_stat(doorbell); 2955cd339b3SRuss Weight if (status == RSU_STAT_WEAROUT) { 2965cd339b3SRuss Weight dev_warn(sec->dev, "Excessive flash update count detected\n"); 2975cd339b3SRuss Weight return FW_UPLOAD_ERR_WEAROUT; 2985cd339b3SRuss Weight } else if (status == RSU_STAT_ERASE_FAIL) { 2995cd339b3SRuss Weight log_error_regs(sec, doorbell); 3005cd339b3SRuss Weight return FW_UPLOAD_ERR_HW_ERROR; 3015cd339b3SRuss Weight } 3025cd339b3SRuss Weight 3035cd339b3SRuss Weight return FW_UPLOAD_ERR_NONE; 3045cd339b3SRuss Weight } 3055cd339b3SRuss Weight 3065cd339b3SRuss Weight static enum fw_upload_err rsu_prog_ready(struct m10bmc_sec *sec) 3075cd339b3SRuss Weight { 308*6052a005SIlpo Järvinen const struct m10bmc_csr_map *csr_map = sec->m10bmc->info->csr_map; 3095cd339b3SRuss Weight unsigned long poll_timeout; 3105cd339b3SRuss Weight u32 doorbell, progress; 3115cd339b3SRuss Weight int ret; 3125cd339b3SRuss Weight 313*6052a005SIlpo Järvinen ret = m10bmc_sys_read(sec->m10bmc, csr_map->doorbell, &doorbell); 3145cd339b3SRuss Weight if (ret) 3155cd339b3SRuss Weight return FW_UPLOAD_ERR_RW_ERROR; 3165cd339b3SRuss Weight 3175cd339b3SRuss Weight poll_timeout = jiffies + msecs_to_jiffies(RSU_PREP_TIMEOUT_MS); 3185cd339b3SRuss Weight while (rsu_prog(doorbell) == RSU_PROG_PREPARE) { 3195cd339b3SRuss Weight msleep(RSU_PREP_INTERVAL_MS); 3205cd339b3SRuss Weight if (time_after(jiffies, poll_timeout)) 3215cd339b3SRuss Weight break; 3225cd339b3SRuss Weight 323*6052a005SIlpo Järvinen ret = m10bmc_sys_read(sec->m10bmc, csr_map->doorbell, &doorbell); 3245cd339b3SRuss Weight if (ret) 3255cd339b3SRuss Weight return FW_UPLOAD_ERR_RW_ERROR; 3265cd339b3SRuss Weight } 3275cd339b3SRuss Weight 3285cd339b3SRuss Weight progress = rsu_prog(doorbell); 3295cd339b3SRuss Weight if (progress == RSU_PROG_PREPARE) { 3305cd339b3SRuss Weight log_error_regs(sec, doorbell); 3315cd339b3SRuss Weight return FW_UPLOAD_ERR_TIMEOUT; 3325cd339b3SRuss Weight } else if (progress != RSU_PROG_READY) { 3335cd339b3SRuss Weight log_error_regs(sec, doorbell); 3345cd339b3SRuss Weight return FW_UPLOAD_ERR_HW_ERROR; 3355cd339b3SRuss Weight } 3365cd339b3SRuss Weight 3375cd339b3SRuss Weight return FW_UPLOAD_ERR_NONE; 3385cd339b3SRuss Weight } 3395cd339b3SRuss Weight 3405cd339b3SRuss Weight static enum fw_upload_err rsu_send_data(struct m10bmc_sec *sec) 3415cd339b3SRuss Weight { 342*6052a005SIlpo Järvinen const struct m10bmc_csr_map *csr_map = sec->m10bmc->info->csr_map; 3435cd339b3SRuss Weight u32 doorbell; 3445cd339b3SRuss Weight int ret; 3455cd339b3SRuss Weight 3465cd339b3SRuss Weight ret = regmap_update_bits(sec->m10bmc->regmap, 347*6052a005SIlpo Järvinen csr_map->base + csr_map->doorbell, 3485cd339b3SRuss Weight DRBL_HOST_STATUS, 3495cd339b3SRuss Weight FIELD_PREP(DRBL_HOST_STATUS, 3505cd339b3SRuss Weight HOST_STATUS_WRITE_DONE)); 3515cd339b3SRuss Weight if (ret) 3525cd339b3SRuss Weight return FW_UPLOAD_ERR_RW_ERROR; 3535cd339b3SRuss Weight 3545cd339b3SRuss Weight ret = regmap_read_poll_timeout(sec->m10bmc->regmap, 355*6052a005SIlpo Järvinen csr_map->base + csr_map->doorbell, 3565cd339b3SRuss Weight doorbell, 3575cd339b3SRuss Weight rsu_prog(doorbell) != RSU_PROG_READY, 3585cd339b3SRuss Weight NIOS_HANDSHAKE_INTERVAL_US, 3595cd339b3SRuss Weight NIOS_HANDSHAKE_TIMEOUT_US); 3605cd339b3SRuss Weight 3615cd339b3SRuss Weight if (ret == -ETIMEDOUT) { 3625cd339b3SRuss Weight log_error_regs(sec, doorbell); 3635cd339b3SRuss Weight return FW_UPLOAD_ERR_TIMEOUT; 3645cd339b3SRuss Weight } else if (ret) { 3655cd339b3SRuss Weight return FW_UPLOAD_ERR_RW_ERROR; 3665cd339b3SRuss Weight } 3675cd339b3SRuss Weight 3685cd339b3SRuss Weight switch (rsu_stat(doorbell)) { 3695cd339b3SRuss Weight case RSU_STAT_NORMAL: 3705cd339b3SRuss Weight case RSU_STAT_NIOS_OK: 3715cd339b3SRuss Weight case RSU_STAT_USER_OK: 3725cd339b3SRuss Weight case RSU_STAT_FACTORY_OK: 3735cd339b3SRuss Weight break; 3745cd339b3SRuss Weight default: 3755cd339b3SRuss Weight log_error_regs(sec, doorbell); 3765cd339b3SRuss Weight return FW_UPLOAD_ERR_HW_ERROR; 3775cd339b3SRuss Weight } 3785cd339b3SRuss Weight 3795cd339b3SRuss Weight return FW_UPLOAD_ERR_NONE; 3805cd339b3SRuss Weight } 3815cd339b3SRuss Weight 3825cd339b3SRuss Weight static int rsu_check_complete(struct m10bmc_sec *sec, u32 *doorbell) 3835cd339b3SRuss Weight { 384*6052a005SIlpo Järvinen const struct m10bmc_csr_map *csr_map = sec->m10bmc->info->csr_map; 385*6052a005SIlpo Järvinen 386*6052a005SIlpo Järvinen if (m10bmc_sys_read(sec->m10bmc, csr_map->doorbell, doorbell)) 3875cd339b3SRuss Weight return -EIO; 3885cd339b3SRuss Weight 3895cd339b3SRuss Weight switch (rsu_stat(*doorbell)) { 3905cd339b3SRuss Weight case RSU_STAT_NORMAL: 3915cd339b3SRuss Weight case RSU_STAT_NIOS_OK: 3925cd339b3SRuss Weight case RSU_STAT_USER_OK: 3935cd339b3SRuss Weight case RSU_STAT_FACTORY_OK: 3945cd339b3SRuss Weight break; 3955cd339b3SRuss Weight default: 3965cd339b3SRuss Weight return -EINVAL; 3975cd339b3SRuss Weight } 3985cd339b3SRuss Weight 3995cd339b3SRuss Weight switch (rsu_prog(*doorbell)) { 4005cd339b3SRuss Weight case RSU_PROG_IDLE: 4015cd339b3SRuss Weight case RSU_PROG_RSU_DONE: 4025cd339b3SRuss Weight return 0; 4035cd339b3SRuss Weight case RSU_PROG_AUTHENTICATING: 4045cd339b3SRuss Weight case RSU_PROG_COPYING: 4055cd339b3SRuss Weight case RSU_PROG_UPDATE_CANCEL: 4065cd339b3SRuss Weight case RSU_PROG_PROGRAM_KEY_HASH: 4075cd339b3SRuss Weight return -EAGAIN; 4085cd339b3SRuss Weight default: 4095cd339b3SRuss Weight return -EINVAL; 4105cd339b3SRuss Weight } 4115cd339b3SRuss Weight } 4125cd339b3SRuss Weight 4135cd339b3SRuss Weight static enum fw_upload_err rsu_cancel(struct m10bmc_sec *sec) 4145cd339b3SRuss Weight { 415*6052a005SIlpo Järvinen const struct m10bmc_csr_map *csr_map = sec->m10bmc->info->csr_map; 4165cd339b3SRuss Weight u32 doorbell; 4175cd339b3SRuss Weight int ret; 4185cd339b3SRuss Weight 419*6052a005SIlpo Järvinen ret = m10bmc_sys_read(sec->m10bmc, csr_map->doorbell, &doorbell); 4205cd339b3SRuss Weight if (ret) 4215cd339b3SRuss Weight return FW_UPLOAD_ERR_RW_ERROR; 4225cd339b3SRuss Weight 4235cd339b3SRuss Weight if (rsu_prog(doorbell) != RSU_PROG_READY) 4245cd339b3SRuss Weight return FW_UPLOAD_ERR_BUSY; 4255cd339b3SRuss Weight 4265cd339b3SRuss Weight ret = regmap_update_bits(sec->m10bmc->regmap, 427*6052a005SIlpo Järvinen csr_map->base + csr_map->doorbell, 4285cd339b3SRuss Weight DRBL_HOST_STATUS, 4295cd339b3SRuss Weight FIELD_PREP(DRBL_HOST_STATUS, 4305cd339b3SRuss Weight HOST_STATUS_ABORT_RSU)); 4315cd339b3SRuss Weight if (ret) 4325cd339b3SRuss Weight return FW_UPLOAD_ERR_RW_ERROR; 4335cd339b3SRuss Weight 4345cd339b3SRuss Weight return FW_UPLOAD_ERR_CANCELED; 4355cd339b3SRuss Weight } 4365cd339b3SRuss Weight 4375cd339b3SRuss Weight static enum fw_upload_err m10bmc_sec_prepare(struct fw_upload *fwl, 4385cd339b3SRuss Weight const u8 *data, u32 size) 4395cd339b3SRuss Weight { 4405cd339b3SRuss Weight struct m10bmc_sec *sec = fwl->dd_handle; 4415cd339b3SRuss Weight u32 ret; 4425cd339b3SRuss Weight 4435cd339b3SRuss Weight sec->cancel_request = false; 4445cd339b3SRuss Weight 4455cd339b3SRuss Weight if (!size || size > M10BMC_STAGING_SIZE) 4465cd339b3SRuss Weight return FW_UPLOAD_ERR_INVALID_SIZE; 4475cd339b3SRuss Weight 4485cd339b3SRuss Weight ret = rsu_check_idle(sec); 4495cd339b3SRuss Weight if (ret != FW_UPLOAD_ERR_NONE) 4505cd339b3SRuss Weight return ret; 4515cd339b3SRuss Weight 4525cd339b3SRuss Weight ret = rsu_update_init(sec); 4535cd339b3SRuss Weight if (ret != FW_UPLOAD_ERR_NONE) 4545cd339b3SRuss Weight return ret; 4555cd339b3SRuss Weight 4565cd339b3SRuss Weight ret = rsu_prog_ready(sec); 4575cd339b3SRuss Weight if (ret != FW_UPLOAD_ERR_NONE) 4585cd339b3SRuss Weight return ret; 4595cd339b3SRuss Weight 4605cd339b3SRuss Weight if (sec->cancel_request) 4615cd339b3SRuss Weight return rsu_cancel(sec); 4625cd339b3SRuss Weight 4635cd339b3SRuss Weight return FW_UPLOAD_ERR_NONE; 4645cd339b3SRuss Weight } 4655cd339b3SRuss Weight 4665cd339b3SRuss Weight #define WRITE_BLOCK_SIZE 0x4000 /* Default write-block size is 0x4000 bytes */ 4675cd339b3SRuss Weight 4685cd339b3SRuss Weight static enum fw_upload_err m10bmc_sec_write(struct fw_upload *fwl, const u8 *data, 4695cd339b3SRuss Weight u32 offset, u32 size, u32 *written) 4705cd339b3SRuss Weight { 4715cd339b3SRuss Weight struct m10bmc_sec *sec = fwl->dd_handle; 472*6052a005SIlpo Järvinen const struct m10bmc_csr_map *csr_map = sec->m10bmc->info->csr_map; 4735cd339b3SRuss Weight u32 blk_size, doorbell, extra_offset; 4745cd339b3SRuss Weight unsigned int stride, extra = 0; 4755cd339b3SRuss Weight int ret; 4765cd339b3SRuss Weight 4775cd339b3SRuss Weight stride = regmap_get_reg_stride(sec->m10bmc->regmap); 4785cd339b3SRuss Weight if (sec->cancel_request) 4795cd339b3SRuss Weight return rsu_cancel(sec); 4805cd339b3SRuss Weight 481*6052a005SIlpo Järvinen ret = m10bmc_sys_read(sec->m10bmc, csr_map->doorbell, &doorbell); 4825cd339b3SRuss Weight if (ret) { 4835cd339b3SRuss Weight return FW_UPLOAD_ERR_RW_ERROR; 4845cd339b3SRuss Weight } else if (rsu_prog(doorbell) != RSU_PROG_READY) { 4855cd339b3SRuss Weight log_error_regs(sec, doorbell); 4865cd339b3SRuss Weight return FW_UPLOAD_ERR_HW_ERROR; 4875cd339b3SRuss Weight } 4885cd339b3SRuss Weight 4895cd339b3SRuss Weight WARN_ON_ONCE(WRITE_BLOCK_SIZE % stride); 4905cd339b3SRuss Weight blk_size = min_t(u32, WRITE_BLOCK_SIZE, size); 4915cd339b3SRuss Weight ret = regmap_bulk_write(sec->m10bmc->regmap, 4925cd339b3SRuss Weight M10BMC_STAGING_BASE + offset, 4935cd339b3SRuss Weight (void *)data + offset, 4945cd339b3SRuss Weight blk_size / stride); 4955cd339b3SRuss Weight if (ret) 4965cd339b3SRuss Weight return FW_UPLOAD_ERR_RW_ERROR; 4975cd339b3SRuss Weight 4985cd339b3SRuss Weight /* 4995cd339b3SRuss Weight * If blk_size is not aligned to stride, then handle the extra 5005cd339b3SRuss Weight * bytes with regmap_write. 5015cd339b3SRuss Weight */ 5025cd339b3SRuss Weight if (blk_size % stride) { 5035cd339b3SRuss Weight extra_offset = offset + ALIGN_DOWN(blk_size, stride); 5045cd339b3SRuss Weight memcpy(&extra, (u8 *)(data + extra_offset), blk_size % stride); 5055cd339b3SRuss Weight ret = regmap_write(sec->m10bmc->regmap, 5065cd339b3SRuss Weight M10BMC_STAGING_BASE + extra_offset, extra); 5075cd339b3SRuss Weight if (ret) 5085cd339b3SRuss Weight return FW_UPLOAD_ERR_RW_ERROR; 5095cd339b3SRuss Weight } 5105cd339b3SRuss Weight 5115cd339b3SRuss Weight *written = blk_size; 5125cd339b3SRuss Weight return FW_UPLOAD_ERR_NONE; 5135cd339b3SRuss Weight } 5145cd339b3SRuss Weight 5155cd339b3SRuss Weight static enum fw_upload_err m10bmc_sec_poll_complete(struct fw_upload *fwl) 5165cd339b3SRuss Weight { 5175cd339b3SRuss Weight struct m10bmc_sec *sec = fwl->dd_handle; 5185cd339b3SRuss Weight unsigned long poll_timeout; 5195cd339b3SRuss Weight u32 doorbell, result; 5205cd339b3SRuss Weight int ret; 5215cd339b3SRuss Weight 5225cd339b3SRuss Weight if (sec->cancel_request) 5235cd339b3SRuss Weight return rsu_cancel(sec); 5245cd339b3SRuss Weight 5255cd339b3SRuss Weight result = rsu_send_data(sec); 5265cd339b3SRuss Weight if (result != FW_UPLOAD_ERR_NONE) 5275cd339b3SRuss Weight return result; 5285cd339b3SRuss Weight 5295cd339b3SRuss Weight poll_timeout = jiffies + msecs_to_jiffies(RSU_COMPLETE_TIMEOUT_MS); 5305cd339b3SRuss Weight do { 5315cd339b3SRuss Weight msleep(RSU_COMPLETE_INTERVAL_MS); 5325cd339b3SRuss Weight ret = rsu_check_complete(sec, &doorbell); 5335cd339b3SRuss Weight } while (ret == -EAGAIN && !time_after(jiffies, poll_timeout)); 5345cd339b3SRuss Weight 5355cd339b3SRuss Weight if (ret == -EAGAIN) { 5365cd339b3SRuss Weight log_error_regs(sec, doorbell); 5375cd339b3SRuss Weight return FW_UPLOAD_ERR_TIMEOUT; 5385cd339b3SRuss Weight } else if (ret == -EIO) { 5395cd339b3SRuss Weight return FW_UPLOAD_ERR_RW_ERROR; 5405cd339b3SRuss Weight } else if (ret) { 5415cd339b3SRuss Weight log_error_regs(sec, doorbell); 5425cd339b3SRuss Weight return FW_UPLOAD_ERR_HW_ERROR; 5435cd339b3SRuss Weight } 5445cd339b3SRuss Weight 5455cd339b3SRuss Weight return FW_UPLOAD_ERR_NONE; 5465cd339b3SRuss Weight } 5475cd339b3SRuss Weight 5485cd339b3SRuss Weight /* 5495cd339b3SRuss Weight * m10bmc_sec_cancel() may be called asynchronously with an on-going update. 5505cd339b3SRuss Weight * All other functions are called sequentially in a single thread. To avoid 5515cd339b3SRuss Weight * contention on register accesses, m10bmc_sec_cancel() must only update 5525cd339b3SRuss Weight * the cancel_request flag. Other functions will check this flag and handle 5535cd339b3SRuss Weight * the cancel request synchronously. 5545cd339b3SRuss Weight */ 5555cd339b3SRuss Weight static void m10bmc_sec_cancel(struct fw_upload *fwl) 5565cd339b3SRuss Weight { 5575cd339b3SRuss Weight struct m10bmc_sec *sec = fwl->dd_handle; 5585cd339b3SRuss Weight 5595cd339b3SRuss Weight sec->cancel_request = true; 5605cd339b3SRuss Weight } 5615cd339b3SRuss Weight 5625cd339b3SRuss Weight static void m10bmc_sec_cleanup(struct fw_upload *fwl) 5635cd339b3SRuss Weight { 5645cd339b3SRuss Weight struct m10bmc_sec *sec = fwl->dd_handle; 5655cd339b3SRuss Weight 5665cd339b3SRuss Weight (void)rsu_cancel(sec); 5675cd339b3SRuss Weight } 5685cd339b3SRuss Weight 5695cd339b3SRuss Weight static const struct fw_upload_ops m10bmc_ops = { 5705cd339b3SRuss Weight .prepare = m10bmc_sec_prepare, 5715cd339b3SRuss Weight .write = m10bmc_sec_write, 5725cd339b3SRuss Weight .poll_complete = m10bmc_sec_poll_complete, 5735cd339b3SRuss Weight .cancel = m10bmc_sec_cancel, 5745cd339b3SRuss Weight .cleanup = m10bmc_sec_cleanup, 5755cd339b3SRuss Weight }; 5765cd339b3SRuss Weight 577bdf86d0eSRuss Weight #define SEC_UPDATE_LEN_MAX 32 578bdf86d0eSRuss Weight static int m10bmc_sec_probe(struct platform_device *pdev) 579bdf86d0eSRuss Weight { 5805cd339b3SRuss Weight char buf[SEC_UPDATE_LEN_MAX]; 581bdf86d0eSRuss Weight struct m10bmc_sec *sec; 5825cd339b3SRuss Weight struct fw_upload *fwl; 5835cd339b3SRuss Weight unsigned int len; 5845cd339b3SRuss Weight int ret; 585bdf86d0eSRuss Weight 586bdf86d0eSRuss Weight sec = devm_kzalloc(&pdev->dev, sizeof(*sec), GFP_KERNEL); 587bdf86d0eSRuss Weight if (!sec) 588bdf86d0eSRuss Weight return -ENOMEM; 589bdf86d0eSRuss Weight 590bdf86d0eSRuss Weight sec->dev = &pdev->dev; 591bdf86d0eSRuss Weight sec->m10bmc = dev_get_drvdata(pdev->dev.parent); 592bdf86d0eSRuss Weight dev_set_drvdata(&pdev->dev, sec); 593bdf86d0eSRuss Weight 5945cd339b3SRuss Weight ret = xa_alloc(&fw_upload_xa, &sec->fw_name_id, sec, 5955cd339b3SRuss Weight xa_limit_32b, GFP_KERNEL); 5965cd339b3SRuss Weight if (ret) 5975cd339b3SRuss Weight return ret; 5985cd339b3SRuss Weight 5995cd339b3SRuss Weight len = scnprintf(buf, SEC_UPDATE_LEN_MAX, "secure-update%d", 6005cd339b3SRuss Weight sec->fw_name_id); 6015cd339b3SRuss Weight sec->fw_name = kmemdup_nul(buf, len, GFP_KERNEL); 6025cd339b3SRuss Weight if (!sec->fw_name) 6035cd339b3SRuss Weight return -ENOMEM; 6045cd339b3SRuss Weight 6055cd339b3SRuss Weight fwl = firmware_upload_register(THIS_MODULE, sec->dev, sec->fw_name, 6065cd339b3SRuss Weight &m10bmc_ops, sec); 6075cd339b3SRuss Weight if (IS_ERR(fwl)) { 6085cd339b3SRuss Weight dev_err(sec->dev, "Firmware Upload driver failed to start\n"); 6095cd339b3SRuss Weight kfree(sec->fw_name); 6105cd339b3SRuss Weight xa_erase(&fw_upload_xa, sec->fw_name_id); 6115cd339b3SRuss Weight return PTR_ERR(fwl); 6125cd339b3SRuss Weight } 6135cd339b3SRuss Weight 6145cd339b3SRuss Weight sec->fwl = fwl; 6155cd339b3SRuss Weight return 0; 6165cd339b3SRuss Weight } 6175cd339b3SRuss Weight 6185cd339b3SRuss Weight static int m10bmc_sec_remove(struct platform_device *pdev) 6195cd339b3SRuss Weight { 6205cd339b3SRuss Weight struct m10bmc_sec *sec = dev_get_drvdata(&pdev->dev); 6215cd339b3SRuss Weight 6225cd339b3SRuss Weight firmware_upload_unregister(sec->fwl); 6235cd339b3SRuss Weight kfree(sec->fw_name); 6245cd339b3SRuss Weight xa_erase(&fw_upload_xa, sec->fw_name_id); 6255cd339b3SRuss Weight 626bdf86d0eSRuss Weight return 0; 627bdf86d0eSRuss Weight } 628bdf86d0eSRuss Weight 629bdf86d0eSRuss Weight static const struct platform_device_id intel_m10bmc_sec_ids[] = { 630bdf86d0eSRuss Weight { 631bdf86d0eSRuss Weight .name = "n3000bmc-sec-update", 632bdf86d0eSRuss Weight }, 633562d0bf2SRuss Weight { 634562d0bf2SRuss Weight .name = "d5005bmc-sec-update", 635562d0bf2SRuss Weight }, 636bdf86d0eSRuss Weight { } 637bdf86d0eSRuss Weight }; 638bdf86d0eSRuss Weight MODULE_DEVICE_TABLE(platform, intel_m10bmc_sec_ids); 639bdf86d0eSRuss Weight 640bdf86d0eSRuss Weight static struct platform_driver intel_m10bmc_sec_driver = { 641bdf86d0eSRuss Weight .probe = m10bmc_sec_probe, 6425cd339b3SRuss Weight .remove = m10bmc_sec_remove, 643bdf86d0eSRuss Weight .driver = { 644bdf86d0eSRuss Weight .name = "intel-m10bmc-sec-update", 645bdf86d0eSRuss Weight .dev_groups = m10bmc_sec_attr_groups, 646bdf86d0eSRuss Weight }, 647bdf86d0eSRuss Weight .id_table = intel_m10bmc_sec_ids, 648bdf86d0eSRuss Weight }; 649bdf86d0eSRuss Weight module_platform_driver(intel_m10bmc_sec_driver); 650bdf86d0eSRuss Weight 651bdf86d0eSRuss Weight MODULE_AUTHOR("Intel Corporation"); 652bdf86d0eSRuss Weight MODULE_DESCRIPTION("Intel MAX10 BMC Secure Update"); 653bdf86d0eSRuss Weight MODULE_LICENSE("GPL"); 654