1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * FPGA Manager Driver for Lattice iCE40. 4 * 5 * Copyright (c) 2016 Joel Holdsworth 6 * 7 * This driver adds support to the FPGA manager for configuring the SRAM of 8 * Lattice iCE40 FPGAs through slave SPI. 9 */ 10 11 #include <linux/fpga/fpga-mgr.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/module.h> 14 #include <linux/spi/spi.h> 15 #include <linux/stringify.h> 16 17 #define ICE40_SPI_MAX_SPEED 25000000 /* Hz */ 18 #define ICE40_SPI_MIN_SPEED 1000000 /* Hz */ 19 20 #define ICE40_SPI_RESET_DELAY 1 /* us (>200ns) */ 21 #define ICE40_SPI_HOUSEKEEPING_DELAY 1200 /* us */ 22 23 #define ICE40_SPI_NUM_ACTIVATION_BYTES DIV_ROUND_UP(49, 8) 24 25 struct ice40_fpga_priv { 26 struct spi_device *dev; 27 struct gpio_desc *reset; 28 struct gpio_desc *cdone; 29 }; 30 31 static enum fpga_mgr_states ice40_fpga_ops_state(struct fpga_manager *mgr) 32 { 33 struct ice40_fpga_priv *priv = mgr->priv; 34 35 return gpiod_get_value(priv->cdone) ? FPGA_MGR_STATE_OPERATING : 36 FPGA_MGR_STATE_UNKNOWN; 37 } 38 39 static int ice40_fpga_ops_write_init(struct fpga_manager *mgr, 40 struct fpga_image_info *info, 41 const char *buf, size_t count) 42 { 43 struct ice40_fpga_priv *priv = mgr->priv; 44 struct spi_device *dev = priv->dev; 45 struct spi_message message; 46 struct spi_transfer assert_cs_then_reset_delay = { 47 .cs_change = 1, 48 .delay = { 49 .value = ICE40_SPI_RESET_DELAY, 50 .unit = SPI_DELAY_UNIT_USECS 51 } 52 }; 53 struct spi_transfer housekeeping_delay_then_release_cs = { 54 .delay = { 55 .value = ICE40_SPI_HOUSEKEEPING_DELAY, 56 .unit = SPI_DELAY_UNIT_USECS 57 } 58 }; 59 int ret; 60 61 if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { 62 dev_err(&dev->dev, 63 "Partial reconfiguration is not supported\n"); 64 return -ENOTSUPP; 65 } 66 67 /* Lock the bus, assert CRESET_B and SS_B and delay >200ns */ 68 spi_bus_lock(dev->controller); 69 70 gpiod_set_value(priv->reset, 1); 71 72 spi_message_init(&message); 73 spi_message_add_tail(&assert_cs_then_reset_delay, &message); 74 ret = spi_sync_locked(dev, &message); 75 76 /* Come out of reset */ 77 gpiod_set_value(priv->reset, 0); 78 79 /* Abort if the chip-select failed */ 80 if (ret) 81 goto fail; 82 83 /* Check CDONE is de-asserted i.e. the FPGA is reset */ 84 if (gpiod_get_value(priv->cdone)) { 85 dev_err(&dev->dev, "Device reset failed, CDONE is asserted\n"); 86 ret = -EIO; 87 goto fail; 88 } 89 90 /* Wait for the housekeeping to complete, and release SS_B */ 91 spi_message_init(&message); 92 spi_message_add_tail(&housekeeping_delay_then_release_cs, &message); 93 ret = spi_sync_locked(dev, &message); 94 95 fail: 96 spi_bus_unlock(dev->controller); 97 98 return ret; 99 } 100 101 static int ice40_fpga_ops_write(struct fpga_manager *mgr, 102 const char *buf, size_t count) 103 { 104 struct ice40_fpga_priv *priv = mgr->priv; 105 106 return spi_write(priv->dev, buf, count); 107 } 108 109 static int ice40_fpga_ops_write_complete(struct fpga_manager *mgr, 110 struct fpga_image_info *info) 111 { 112 struct ice40_fpga_priv *priv = mgr->priv; 113 struct spi_device *dev = priv->dev; 114 const u8 padding[ICE40_SPI_NUM_ACTIVATION_BYTES] = {0}; 115 116 /* Check CDONE is asserted */ 117 if (!gpiod_get_value(priv->cdone)) { 118 dev_err(&dev->dev, 119 "CDONE was not asserted after firmware transfer\n"); 120 return -EIO; 121 } 122 123 /* Send of zero-padding to activate the firmware */ 124 return spi_write(dev, padding, sizeof(padding)); 125 } 126 127 static const struct fpga_manager_ops ice40_fpga_ops = { 128 .state = ice40_fpga_ops_state, 129 .write_init = ice40_fpga_ops_write_init, 130 .write = ice40_fpga_ops_write, 131 .write_complete = ice40_fpga_ops_write_complete, 132 }; 133 134 static int ice40_fpga_probe(struct spi_device *spi) 135 { 136 struct device *dev = &spi->dev; 137 struct ice40_fpga_priv *priv; 138 struct fpga_manager *mgr; 139 int ret; 140 141 priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL); 142 if (!priv) 143 return -ENOMEM; 144 145 priv->dev = spi; 146 147 /* Check board setup data. */ 148 if (spi->max_speed_hz > ICE40_SPI_MAX_SPEED) { 149 dev_err(dev, "SPI speed is too high, maximum speed is " 150 __stringify(ICE40_SPI_MAX_SPEED) "\n"); 151 return -EINVAL; 152 } 153 154 if (spi->max_speed_hz < ICE40_SPI_MIN_SPEED) { 155 dev_err(dev, "SPI speed is too low, minimum speed is " 156 __stringify(ICE40_SPI_MIN_SPEED) "\n"); 157 return -EINVAL; 158 } 159 160 if (spi->mode & SPI_CPHA) { 161 dev_err(dev, "Bad SPI mode, CPHA not supported\n"); 162 return -EINVAL; 163 } 164 165 /* Set up the GPIOs */ 166 priv->cdone = devm_gpiod_get(dev, "cdone", GPIOD_IN); 167 if (IS_ERR(priv->cdone)) { 168 ret = PTR_ERR(priv->cdone); 169 dev_err(dev, "Failed to get CDONE GPIO: %d\n", ret); 170 return ret; 171 } 172 173 priv->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); 174 if (IS_ERR(priv->reset)) { 175 ret = PTR_ERR(priv->reset); 176 dev_err(dev, "Failed to get CRESET_B GPIO: %d\n", ret); 177 return ret; 178 } 179 180 mgr = devm_fpga_mgr_register(dev, "Lattice iCE40 FPGA Manager", 181 &ice40_fpga_ops, priv); 182 return PTR_ERR_OR_ZERO(mgr); 183 } 184 185 static const struct of_device_id ice40_fpga_of_match[] = { 186 { .compatible = "lattice,ice40-fpga-mgr", }, 187 {}, 188 }; 189 MODULE_DEVICE_TABLE(of, ice40_fpga_of_match); 190 191 static const struct spi_device_id ice40_fpga_spi_ids[] = { 192 { .name = "ice40-fpga-mgr", }, 193 {}, 194 }; 195 MODULE_DEVICE_TABLE(spi, ice40_fpga_spi_ids); 196 197 static struct spi_driver ice40_fpga_driver = { 198 .probe = ice40_fpga_probe, 199 .driver = { 200 .name = "ice40spi", 201 .of_match_table = ice40_fpga_of_match, 202 }, 203 .id_table = ice40_fpga_spi_ids, 204 }; 205 206 module_spi_driver(ice40_fpga_driver); 207 208 MODULE_AUTHOR("Joel Holdsworth <joel@airwebreathe.org.uk>"); 209 MODULE_DESCRIPTION("Lattice iCE40 FPGA Manager"); 210 MODULE_LICENSE("GPL v2"); 211