1# SPDX-License-Identifier: GPL-2.0 2# 3# Makefile for the fpga framework and fpga manager drivers. 4# 5 6# Core FPGA Manager Framework 7obj-$(CONFIG_FPGA) += fpga-mgr.o 8 9# FPGA Manager Drivers 10obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o 11obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o 12obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o 13obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o 14obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o 15obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o 16obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o 17obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o 18obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o 19obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o 20obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o 21obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o 22obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o 23obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o 24 25# FPGA Bridge Drivers 26obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o 27obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o 28obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o 29obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o 30 31# High Level Interfaces 32obj-$(CONFIG_FPGA_REGION) += fpga-region.o 33obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o 34 35# FPGA Device Feature List Support 36obj-$(CONFIG_FPGA_DFL) += dfl.o 37obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o 38obj-$(CONFIG_FPGA_DFL_FME_MGR) += dfl-fme-mgr.o 39obj-$(CONFIG_FPGA_DFL_FME_BRIDGE) += dfl-fme-br.o 40obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o 41obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o 42 43dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o dfl-fme-error.o 44dfl-fme-objs += dfl-fme-perf.o 45dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o 46dfl-afu-objs += dfl-afu-error.o 47 48obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o 49 50# Drivers for FPGAs which implement DFL 51obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o 52