1# SPDX-License-Identifier: GPL-2.0-only 2# 3# FPGA framework configuration 4# 5 6menuconfig FPGA 7 tristate "FPGA Configuration Framework" 8 help 9 Say Y here if you want support for configuring FPGAs from the 10 kernel. The FPGA framework adds an FPGA manager class and FPGA 11 manager drivers. 12 13if FPGA 14 15config FPGA_MGR_SOCFPGA 16 tristate "Altera SOCFPGA FPGA Manager" 17 depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST 18 help 19 FPGA manager driver support for Altera SOCFPGA. 20 21config FPGA_MGR_SOCFPGA_A10 22 tristate "Altera SoCFPGA Arria10" 23 depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST 24 select REGMAP_MMIO 25 help 26 FPGA manager driver support for Altera Arria10 SoCFPGA. 27 28config ALTERA_PR_IP_CORE 29 tristate "Altera Partial Reconfiguration IP Core" 30 help 31 Core driver support for Altera Partial Reconfiguration IP component 32 33config ALTERA_PR_IP_CORE_PLAT 34 tristate "Platform support of Altera Partial Reconfiguration IP Core" 35 depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM 36 help 37 Platform driver support for Altera Partial Reconfiguration IP 38 component 39 40config FPGA_MGR_ALTERA_PS_SPI 41 tristate "Altera FPGA Passive Serial over SPI" 42 depends on SPI 43 select BITREVERSE 44 help 45 FPGA manager driver support for Altera Arria/Cyclone/Stratix 46 using the passive serial interface over SPI. 47 48config FPGA_MGR_ALTERA_CVP 49 tristate "Altera CvP FPGA Manager" 50 depends on PCI 51 help 52 FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V, 53 Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe. 54 55config FPGA_MGR_ZYNQ_FPGA 56 tristate "Xilinx Zynq FPGA" 57 depends on ARCH_ZYNQ || COMPILE_TEST 58 help 59 FPGA manager driver support for Xilinx Zynq FPGAs. 60 61config FPGA_MGR_STRATIX10_SOC 62 tristate "Intel Stratix10 SoC FPGA Manager" 63 depends on (ARCH_INTEL_SOCFPGA && INTEL_STRATIX10_SERVICE) 64 help 65 FPGA manager driver support for the Intel Stratix10 SoC. 66 67config FPGA_MGR_XILINX_SPI 68 tristate "Xilinx Configuration over Slave Serial (SPI)" 69 depends on SPI 70 help 71 FPGA manager driver support for Xilinx FPGA configuration 72 over slave serial interface. 73 74config FPGA_MGR_ICE40_SPI 75 tristate "Lattice iCE40 SPI" 76 depends on OF && SPI 77 help 78 FPGA manager driver support for Lattice iCE40 FPGAs over SPI. 79 80config FPGA_MGR_MACHXO2_SPI 81 tristate "Lattice MachXO2 SPI" 82 depends on SPI 83 help 84 FPGA manager driver support for Lattice MachXO2 configuration 85 over slave SPI interface. 86 87config FPGA_MGR_TS73XX 88 tristate "Technologic Systems TS-73xx SBC FPGA Manager" 89 depends on ARCH_EP93XX && MACH_TS72XX 90 help 91 FPGA manager driver support for the Altera Cyclone II FPGA 92 present on the TS-73xx SBC boards. 93 94config FPGA_BRIDGE 95 tristate "FPGA Bridge Framework" 96 help 97 Say Y here if you want to support bridges connected between host 98 processors and FPGAs or between FPGAs. 99 100config SOCFPGA_FPGA_BRIDGE 101 tristate "Altera SoCFPGA FPGA Bridges" 102 depends on ARCH_INTEL_SOCFPGA && FPGA_BRIDGE 103 help 104 Say Y to enable drivers for FPGA bridges for Altera SOCFPGA 105 devices. 106 107config ALTERA_FREEZE_BRIDGE 108 tristate "Altera FPGA Freeze Bridge" 109 depends on FPGA_BRIDGE && HAS_IOMEM 110 help 111 Say Y to enable drivers for Altera FPGA Freeze bridges. A 112 freeze bridge is a bridge that exists in the FPGA fabric to 113 isolate one region of the FPGA from the busses while that 114 region is being reprogrammed. 115 116config XILINX_PR_DECOUPLER 117 tristate "Xilinx LogiCORE PR Decoupler" 118 depends on FPGA_BRIDGE 119 depends on HAS_IOMEM 120 help 121 Say Y to enable drivers for Xilinx LogiCORE PR Decoupler 122 or Xilinx Dynamic Function eXchange AIX Shutdown Manager. 123 The PR Decoupler exists in the FPGA fabric to isolate one 124 region of the FPGA from the busses while that region is 125 being reprogrammed during partial reconfig. 126 The Dynamic Function eXchange AXI shutdown manager prevents 127 AXI traffic from passing through the bridge. The controller 128 safely handles AXI4MM and AXI4-Lite interfaces on a 129 Reconfigurable Partition when it is undergoing dynamic 130 reconfiguration, preventing the system deadlock that can 131 occur if AXI transactions are interrupted by DFX. 132 133config FPGA_REGION 134 tristate "FPGA Region" 135 depends on FPGA_BRIDGE 136 help 137 FPGA Region common code. An FPGA Region controls an FPGA Manager 138 and the FPGA Bridges associated with either a reconfigurable 139 region of an FPGA or a whole FPGA. 140 141config OF_FPGA_REGION 142 tristate "FPGA Region Device Tree Overlay Support" 143 depends on OF && FPGA_REGION 144 help 145 Support for loading FPGA images by applying a Device Tree 146 overlay. 147 148config FPGA_DFL 149 tristate "FPGA Device Feature List (DFL) support" 150 select FPGA_BRIDGE 151 select FPGA_REGION 152 depends on HAS_IOMEM 153 help 154 Device Feature List (DFL) defines a feature list structure that 155 creates a linked list of feature headers within the MMIO space 156 to provide an extensible way of adding features for FPGA. 157 Driver can walk through the feature headers to enumerate feature 158 devices (e.g. FPGA Management Engine, Port and Accelerator 159 Function Unit) and their private features for target FPGA devices. 160 161 Select this option to enable common support for Field-Programmable 162 Gate Array (FPGA) solutions which implement Device Feature List. 163 It provides enumeration APIs and feature device infrastructure. 164 165config FPGA_DFL_FME 166 tristate "FPGA DFL FME Driver" 167 depends on FPGA_DFL && HWMON && PERF_EVENTS 168 help 169 The FPGA Management Engine (FME) is a feature device implemented 170 under Device Feature List (DFL) framework. Select this option to 171 enable the platform device driver for FME which implements all 172 FPGA platform level management features. There shall be one FME 173 per DFL based FPGA device. 174 175config FPGA_DFL_FME_MGR 176 tristate "FPGA DFL FME Manager Driver" 177 depends on FPGA_DFL_FME && HAS_IOMEM 178 help 179 Say Y to enable FPGA Manager driver for FPGA Management Engine. 180 181config FPGA_DFL_FME_BRIDGE 182 tristate "FPGA DFL FME Bridge Driver" 183 depends on FPGA_DFL_FME && HAS_IOMEM 184 help 185 Say Y to enable FPGA Bridge driver for FPGA Management Engine. 186 187config FPGA_DFL_FME_REGION 188 tristate "FPGA DFL FME Region Driver" 189 depends on FPGA_DFL_FME && HAS_IOMEM 190 help 191 Say Y to enable FPGA Region driver for FPGA Management Engine. 192 193config FPGA_DFL_AFU 194 tristate "FPGA DFL AFU Driver" 195 depends on FPGA_DFL 196 help 197 This is the driver for FPGA Accelerated Function Unit (AFU) which 198 implements AFU and Port management features. A User AFU connects 199 to the FPGA infrastructure via a Port. There may be more than one 200 Port/AFU per DFL based FPGA device. 201 202config FPGA_DFL_NIOS_INTEL_PAC_N3000 203 tristate "FPGA DFL NIOS Driver for Intel PAC N3000" 204 depends on FPGA_DFL 205 select REGMAP 206 help 207 This is the driver for the N3000 Nios private feature on Intel 208 PAC (Programmable Acceleration Card) N3000. It communicates 209 with the embedded Nios processor to configure the retimers on 210 the card. It also instantiates the SPI master (spi-altera) for 211 the card's BMC (Board Management Controller). 212 213config FPGA_DFL_PCI 214 tristate "FPGA DFL PCIe Device Driver" 215 depends on PCI && FPGA_DFL 216 help 217 Select this option to enable PCIe driver for PCIe-based 218 Field-Programmable Gate Array (FPGA) solutions which implement 219 the Device Feature List (DFL). This driver provides interfaces 220 for userspace applications to configure, enumerate, open and access 221 FPGA accelerators on the FPGA DFL devices, enables system level 222 management functions such as FPGA partial reconfiguration, power 223 management and virtualization with DFL framework and DFL feature 224 device drivers. 225 226 To compile this as a module, choose M here. 227 228config FPGA_MGR_ZYNQMP_FPGA 229 tristate "Xilinx ZynqMP FPGA" 230 depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST) 231 help 232 FPGA manager driver support for Xilinx ZynqMP FPGAs. 233 This driver uses the processor configuration port(PCAP) 234 to configure the programmable logic(PL) through PS 235 on ZynqMP SoC. 236 237config FPGA_MGR_VERSAL_FPGA 238 tristate "Xilinx Versal FPGA" 239 depends on ARCH_ZYNQMP || COMPILE_TEST 240 help 241 Select this option to enable FPGA manager driver support for 242 Xilinx Versal SoC. This driver uses the firmware interface to 243 configure the programmable logic(PL). 244 245 To compile this as a module, choose M here. 246 247config FPGA_M10_BMC_SEC_UPDATE 248 tristate "Intel MAX10 BMC Secure Update driver" 249 depends on MFD_INTEL_M10_BMC && FW_UPLOAD 250 help 251 Secure update support for the Intel MAX10 board management 252 controller. 253 254 This is a subdriver of the Intel MAX10 board management controller 255 (BMC) and provides support for secure updates for the BMC image, 256 the FPGA image, the Root Entry Hashes, etc. 257 258config FPGA_MGR_MICROCHIP_SPI 259 tristate "Microchip Polarfire SPI FPGA manager" 260 depends on SPI 261 help 262 FPGA manager driver support for Microchip Polarfire FPGAs 263 programming over slave SPI interface with .dat formatted 264 bitstream image. 265 266endif # FPGA 267