16a8c3be7SAlan Tull# 26a8c3be7SAlan Tull# FPGA framework configuration 36a8c3be7SAlan Tull# 46a8c3be7SAlan Tull 550fa0285SVincent Legollmenuconfig FPGA 66a8c3be7SAlan Tull tristate "FPGA Configuration Framework" 76a8c3be7SAlan Tull help 86a8c3be7SAlan Tull Say Y here if you want support for configuring FPGAs from the 96a8c3be7SAlan Tull kernel. The FPGA framework adds a FPGA manager class and FPGA 106a8c3be7SAlan Tull manager drivers. 116a8c3be7SAlan Tull 12fab6266eSAlan Tullif FPGA 13fab6266eSAlan Tull 14fab6266eSAlan Tullconfig FPGA_MGR_SOCFPGA 15fab6266eSAlan Tull tristate "Altera SOCFPGA FPGA Manager" 16a0e1b618SJason Gunthorpe depends on ARCH_SOCFPGA || COMPILE_TEST 17fab6266eSAlan Tull help 18fab6266eSAlan Tull FPGA manager driver support for Altera SOCFPGA. 19fab6266eSAlan Tull 20acbb910aSAlan Tullconfig FPGA_MGR_SOCFPGA_A10 21acbb910aSAlan Tull tristate "Altera SoCFPGA Arria10" 22a0e1b618SJason Gunthorpe depends on ARCH_SOCFPGA || COMPILE_TEST 23a0e1b618SJason Gunthorpe select REGMAP_MMIO 24acbb910aSAlan Tull help 25acbb910aSAlan Tull FPGA manager driver support for Altera Arria10 SoCFPGA. 26acbb910aSAlan Tull 2784e93f1dSAlan Tullconfig ALTERA_PR_IP_CORE 2884e93f1dSAlan Tull tristate "Altera Partial Reconfiguration IP Core" 294348f7e2SFlorian Fainelli help 3084e93f1dSAlan Tull Core driver support for Altera Partial Reconfiguration IP component 3184e93f1dSAlan Tull 3284e93f1dSAlan Tullconfig ALTERA_PR_IP_CORE_PLAT 3384e93f1dSAlan Tull tristate "Platform support of Altera Partial Reconfiguration IP Core" 3484e93f1dSAlan Tull depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM 3584e93f1dSAlan Tull help 3684e93f1dSAlan Tull Platform driver support for Altera Partial Reconfiguration IP 3784e93f1dSAlan Tull component 3884e93f1dSAlan Tull 3984e93f1dSAlan Tullconfig FPGA_MGR_ALTERA_PS_SPI 4084e93f1dSAlan Tull tristate "Altera FPGA Passive Serial over SPI" 4184e93f1dSAlan Tull depends on SPI 4284e93f1dSAlan Tull help 4384e93f1dSAlan Tull FPGA manager driver support for Altera Arria/Cyclone/Stratix 4484e93f1dSAlan Tull using the passive serial interface over SPI. 4584e93f1dSAlan Tull 4684e93f1dSAlan Tullconfig FPGA_MGR_ALTERA_CVP 4784e93f1dSAlan Tull tristate "Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager" 4884e93f1dSAlan Tull depends on PCI 4984e93f1dSAlan Tull help 5084e93f1dSAlan Tull FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V 5184e93f1dSAlan Tull and Arria 10 Altera FPGAs using the CvP interface over PCIe. 5284e93f1dSAlan Tull 5384e93f1dSAlan Tullconfig FPGA_MGR_ZYNQ_FPGA 5484e93f1dSAlan Tull tristate "Xilinx Zynq FPGA" 5584e93f1dSAlan Tull depends on ARCH_ZYNQ || COMPILE_TEST 5684e93f1dSAlan Tull help 5784e93f1dSAlan Tull FPGA manager driver support for Xilinx Zynq FPGAs. 584348f7e2SFlorian Fainelli 59e7eef1d7SAlan Tullconfig FPGA_MGR_STRATIX10_SOC 60e7eef1d7SAlan Tull tristate "Intel Stratix10 SoC FPGA Manager" 61e7eef1d7SAlan Tull depends on (ARCH_STRATIX10 && INTEL_STRATIX10_SERVICE) 62e7eef1d7SAlan Tull help 63e7eef1d7SAlan Tull FPGA manager driver support for the Intel Stratix10 SoC. 64e7eef1d7SAlan Tull 65061c97d1SAnatolij Gustschinconfig FPGA_MGR_XILINX_SPI 66061c97d1SAnatolij Gustschin tristate "Xilinx Configuration over Slave Serial (SPI)" 67061c97d1SAnatolij Gustschin depends on SPI 68061c97d1SAnatolij Gustschin help 69061c97d1SAnatolij Gustschin FPGA manager driver support for Xilinx FPGA configuration 70061c97d1SAnatolij Gustschin over slave serial interface. 71061c97d1SAnatolij Gustschin 7284e93f1dSAlan Tullconfig FPGA_MGR_ICE40_SPI 7384e93f1dSAlan Tull tristate "Lattice iCE40 SPI" 7484e93f1dSAlan Tull depends on OF && SPI 7537784706SMoritz Fischer help 7684e93f1dSAlan Tull FPGA manager driver support for Lattice iCE40 FPGAs over SPI. 7784e93f1dSAlan Tull 7888fb3a00SPaolo Pisaticonfig FPGA_MGR_MACHXO2_SPI 7988fb3a00SPaolo Pisati tristate "Lattice MachXO2 SPI" 8088fb3a00SPaolo Pisati depends on SPI 8188fb3a00SPaolo Pisati help 8288fb3a00SPaolo Pisati FPGA manager driver support for Lattice MachXO2 configuration 8388fb3a00SPaolo Pisati over slave SPI interface. 8488fb3a00SPaolo Pisati 8584e93f1dSAlan Tullconfig FPGA_MGR_TS73XX 8684e93f1dSAlan Tull tristate "Technologic Systems TS-73xx SBC FPGA Manager" 8784e93f1dSAlan Tull depends on ARCH_EP93XX && MACH_TS72XX 8884e93f1dSAlan Tull help 8984e93f1dSAlan Tull FPGA manager driver support for the Altera Cyclone II FPGA 9084e93f1dSAlan Tull present on the TS-73xx SBC boards. 9137784706SMoritz Fischer 9221aeda95SAlan Tullconfig FPGA_BRIDGE 9321aeda95SAlan Tull tristate "FPGA Bridge Framework" 9421aeda95SAlan Tull help 9521aeda95SAlan Tull Say Y here if you want to support bridges connected between host 9621aeda95SAlan Tull processors and FPGAs or between FPGAs. 9721aeda95SAlan Tull 98e5f8efa5SAlan Tullconfig SOCFPGA_FPGA_BRIDGE 99e5f8efa5SAlan Tull tristate "Altera SoCFPGA FPGA Bridges" 100e5f8efa5SAlan Tull depends on ARCH_SOCFPGA && FPGA_BRIDGE 101e5f8efa5SAlan Tull help 102e5f8efa5SAlan Tull Say Y to enable drivers for FPGA bridges for Altera SOCFPGA 103e5f8efa5SAlan Tull devices. 104e5f8efa5SAlan Tull 105ca24a648SAlan Tullconfig ALTERA_FREEZE_BRIDGE 106ca24a648SAlan Tull tristate "Altera FPGA Freeze Bridge" 107*38cd7ad5SAlan Tull depends on FPGA_BRIDGE && HAS_IOMEM 108ca24a648SAlan Tull help 109ca24a648SAlan Tull Say Y to enable drivers for Altera FPGA Freeze bridges. A 110ca24a648SAlan Tull freeze bridge is a bridge that exists in the FPGA fabric to 111ca24a648SAlan Tull isolate one region of the FPGA from the busses while that 112ca24a648SAlan Tull region is being reprogrammed. 113ca24a648SAlan Tull 1147e961c12SMoritz Fischerconfig XILINX_PR_DECOUPLER 1157e961c12SMoritz Fischer tristate "Xilinx LogiCORE PR Decoupler" 1167e961c12SMoritz Fischer depends on FPGA_BRIDGE 1177e961c12SMoritz Fischer depends on HAS_IOMEM 1187e961c12SMoritz Fischer help 1197e961c12SMoritz Fischer Say Y to enable drivers for Xilinx LogiCORE PR Decoupler. 1207e961c12SMoritz Fischer The PR Decoupler exists in the FPGA fabric to isolate one 1217e961c12SMoritz Fischer region of the FPGA from the busses while that region is 1227e961c12SMoritz Fischer being reprogrammed during partial reconfig. 1237e961c12SMoritz Fischer 12484e93f1dSAlan Tullconfig FPGA_REGION 12584e93f1dSAlan Tull tristate "FPGA Region" 12684e93f1dSAlan Tull depends on FPGA_BRIDGE 12784e93f1dSAlan Tull help 12884e93f1dSAlan Tull FPGA Region common code. A FPGA Region controls a FPGA Manager 12984e93f1dSAlan Tull and the FPGA Bridges associated with either a reconfigurable 13084e93f1dSAlan Tull region of an FPGA or a whole FPGA. 13184e93f1dSAlan Tull 13284e93f1dSAlan Tullconfig OF_FPGA_REGION 13384e93f1dSAlan Tull tristate "FPGA Region Device Tree Overlay Support" 13484e93f1dSAlan Tull depends on OF && FPGA_REGION 13584e93f1dSAlan Tull help 13684e93f1dSAlan Tull Support for loading FPGA images by applying a Device Tree 13784e93f1dSAlan Tull overlay. 13884e93f1dSAlan Tull 139543be3d8SWu Haoconfig FPGA_DFL 140543be3d8SWu Hao tristate "FPGA Device Feature List (DFL) support" 141543be3d8SWu Hao select FPGA_BRIDGE 142543be3d8SWu Hao select FPGA_REGION 143543be3d8SWu Hao help 144543be3d8SWu Hao Device Feature List (DFL) defines a feature list structure that 145543be3d8SWu Hao creates a linked list of feature headers within the MMIO space 146543be3d8SWu Hao to provide an extensible way of adding features for FPGA. 147543be3d8SWu Hao Driver can walk through the feature headers to enumerate feature 148543be3d8SWu Hao devices (e.g. FPGA Management Engine, Port and Accelerator 149543be3d8SWu Hao Function Unit) and their private features for target FPGA devices. 150543be3d8SWu Hao 151543be3d8SWu Hao Select this option to enable common support for Field-Programmable 152543be3d8SWu Hao Gate Array (FPGA) solutions which implement Device Feature List. 153543be3d8SWu Hao It provides enumeration APIs and feature device infrastructure. 154543be3d8SWu Hao 155322ddebeSKang Luweiconfig FPGA_DFL_FME 156322ddebeSKang Luwei tristate "FPGA DFL FME Driver" 157322ddebeSKang Luwei depends on FPGA_DFL 158322ddebeSKang Luwei help 159322ddebeSKang Luwei The FPGA Management Engine (FME) is a feature device implemented 160322ddebeSKang Luwei under Device Feature List (DFL) framework. Select this option to 161322ddebeSKang Luwei enable the platform device driver for FME which implements all 162322ddebeSKang Luwei FPGA platform level management features. There shall be one FME 163322ddebeSKang Luwei per DFL based FPGA device. 164322ddebeSKang Luwei 165af275ec6SWu Haoconfig FPGA_DFL_FME_MGR 166af275ec6SWu Hao tristate "FPGA DFL FME Manager Driver" 167af275ec6SWu Hao depends on FPGA_DFL_FME && HAS_IOMEM 168af275ec6SWu Hao help 169af275ec6SWu Hao Say Y to enable FPGA Manager driver for FPGA Management Engine. 170af275ec6SWu Hao 171de892dffSWu Haoconfig FPGA_DFL_FME_BRIDGE 172de892dffSWu Hao tristate "FPGA DFL FME Bridge Driver" 173de892dffSWu Hao depends on FPGA_DFL_FME && HAS_IOMEM 174de892dffSWu Hao help 175de892dffSWu Hao Say Y to enable FPGA Bridge driver for FPGA Management Engine. 176de892dffSWu Hao 177bb61b9beSWu Haoconfig FPGA_DFL_FME_REGION 178bb61b9beSWu Hao tristate "FPGA DFL FME Region Driver" 179bb61b9beSWu Hao depends on FPGA_DFL_FME && HAS_IOMEM 180bb61b9beSWu Hao help 181bb61b9beSWu Hao Say Y to enable FPGA Region driver for FPGA Management Engine. 182bb61b9beSWu Hao 1831a1527cfSWu Haoconfig FPGA_DFL_AFU 1841a1527cfSWu Hao tristate "FPGA DFL AFU Driver" 1851a1527cfSWu Hao depends on FPGA_DFL 1861a1527cfSWu Hao help 1871a1527cfSWu Hao This is the driver for FPGA Accelerated Function Unit (AFU) which 1881a1527cfSWu Hao implements AFU and Port management features. A User AFU connects 1891a1527cfSWu Hao to the FPGA infrastructure via a Port. There may be more than one 1901a1527cfSWu Hao Port/AFU per DFL based FPGA device. 1911a1527cfSWu Hao 19272ddd9f3SZhang Yiconfig FPGA_DFL_PCI 19372ddd9f3SZhang Yi tristate "FPGA DFL PCIe Device Driver" 19472ddd9f3SZhang Yi depends on PCI && FPGA_DFL 19572ddd9f3SZhang Yi help 19672ddd9f3SZhang Yi Select this option to enable PCIe driver for PCIe-based 19772ddd9f3SZhang Yi Field-Programmable Gate Array (FPGA) solutions which implement 19872ddd9f3SZhang Yi the Device Feature List (DFL). This driver provides interfaces 19972ddd9f3SZhang Yi for userspace applications to configure, enumerate, open and access 20072ddd9f3SZhang Yi FPGA accelerators on the FPGA DFL devices, enables system level 20172ddd9f3SZhang Yi management functions such as FPGA partial reconfiguration, power 20272ddd9f3SZhang Yi management and virtualization with DFL framework and DFL feature 20372ddd9f3SZhang Yi device drivers. 20472ddd9f3SZhang Yi 20572ddd9f3SZhang Yi To compile this as a module, choose M here. 20672ddd9f3SZhang Yi 207fab6266eSAlan Tullendif # FPGA 208