xref: /linux/drivers/fpga/Kconfig (revision c771600c6af14749609b49565ffb4cac2959710d)
1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only
26a8c3be7SAlan Tull#
36a8c3be7SAlan Tull# FPGA framework configuration
46a8c3be7SAlan Tull#
56a8c3be7SAlan Tull
650fa0285SVincent Legollmenuconfig FPGA
76a8c3be7SAlan Tull	tristate "FPGA Configuration Framework"
86a8c3be7SAlan Tull	help
96a8c3be7SAlan Tull	  Say Y here if you want support for configuring FPGAs from the
10df82d2ecSTom Rix	  kernel.  The FPGA framework adds an FPGA manager class and FPGA
116a8c3be7SAlan Tull	  manager drivers.
126a8c3be7SAlan Tull
13fab6266eSAlan Tullif FPGA
14fab6266eSAlan Tull
15fab6266eSAlan Tullconfig FPGA_MGR_SOCFPGA
16fab6266eSAlan Tull	tristate "Altera SOCFPGA FPGA Manager"
173a1fef70SKrzysztof Kozlowski	depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
18fab6266eSAlan Tull	help
19fab6266eSAlan Tull	  FPGA manager driver support for Altera SOCFPGA.
20fab6266eSAlan Tull
21acbb910aSAlan Tullconfig FPGA_MGR_SOCFPGA_A10
22acbb910aSAlan Tull	tristate "Altera SoCFPGA Arria10"
233a1fef70SKrzysztof Kozlowski	depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
24a0e1b618SJason Gunthorpe	select REGMAP_MMIO
25acbb910aSAlan Tull	help
26acbb910aSAlan Tull	  FPGA manager driver support for Altera Arria10 SoCFPGA.
27acbb910aSAlan Tull
2884e93f1dSAlan Tullconfig ALTERA_PR_IP_CORE
2984e93f1dSAlan Tull	tristate "Altera Partial Reconfiguration IP Core"
304348f7e2SFlorian Fainelli	help
3184e93f1dSAlan Tull	  Core driver support for Altera Partial Reconfiguration IP component
3284e93f1dSAlan Tull
3384e93f1dSAlan Tullconfig ALTERA_PR_IP_CORE_PLAT
3484e93f1dSAlan Tull	tristate "Platform support of Altera Partial Reconfiguration IP Core"
3584e93f1dSAlan Tull	depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
3684e93f1dSAlan Tull	help
3784e93f1dSAlan Tull	  Platform driver support for Altera Partial Reconfiguration IP
3884e93f1dSAlan Tull	  component
3984e93f1dSAlan Tull
4084e93f1dSAlan Tullconfig FPGA_MGR_ALTERA_PS_SPI
4184e93f1dSAlan Tull	tristate "Altera FPGA Passive Serial over SPI"
4284e93f1dSAlan Tull	depends on SPI
433d139703SYueHaibing	select BITREVERSE
4484e93f1dSAlan Tull	help
4584e93f1dSAlan Tull	  FPGA manager driver support for Altera Arria/Cyclone/Stratix
4684e93f1dSAlan Tull	  using the passive serial interface over SPI.
4784e93f1dSAlan Tull
4884e93f1dSAlan Tullconfig FPGA_MGR_ALTERA_CVP
49e5891517SThor Thayer	tristate "Altera CvP FPGA Manager"
5084e93f1dSAlan Tull	depends on PCI
5184e93f1dSAlan Tull	help
52e5891517SThor Thayer	  FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
53e5891517SThor Thayer	  Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
5484e93f1dSAlan Tull
5584e93f1dSAlan Tullconfig FPGA_MGR_ZYNQ_FPGA
5684e93f1dSAlan Tull	tristate "Xilinx Zynq FPGA"
5784e93f1dSAlan Tull	depends on ARCH_ZYNQ || COMPILE_TEST
5884e93f1dSAlan Tull	help
5984e93f1dSAlan Tull	  FPGA manager driver support for Xilinx Zynq FPGAs.
604348f7e2SFlorian Fainelli
61e7eef1d7SAlan Tullconfig FPGA_MGR_STRATIX10_SOC
62e7eef1d7SAlan Tull	tristate "Intel Stratix10 SoC FPGA Manager"
634a9a1a56SKrzysztof Kozlowski	depends on (ARCH_INTEL_SOCFPGA && INTEL_STRATIX10_SERVICE)
64e7eef1d7SAlan Tull	help
65e7eef1d7SAlan Tull	  FPGA manager driver support for the Intel Stratix10 SoC.
66e7eef1d7SAlan Tull
67a52e3a9dSCharles Perryconfig FPGA_MGR_XILINX_CORE
68a52e3a9dSCharles Perry	tristate
69a52e3a9dSCharles Perry
70*104712a0SCharles Perryconfig FPGA_MGR_XILINX_SELECTMAP
71*104712a0SCharles Perry	tristate "Xilinx Configuration over SelectMAP"
72*104712a0SCharles Perry	depends on HAS_IOMEM
73*104712a0SCharles Perry	select FPGA_MGR_XILINX_CORE
74*104712a0SCharles Perry	help
75*104712a0SCharles Perry	  FPGA manager driver support for Xilinx FPGA configuration
76*104712a0SCharles Perry	  over SelectMAP interface.
77*104712a0SCharles Perry
78061c97d1SAnatolij Gustschinconfig FPGA_MGR_XILINX_SPI
79061c97d1SAnatolij Gustschin	tristate "Xilinx Configuration over Slave Serial (SPI)"
80061c97d1SAnatolij Gustschin	depends on SPI
81a52e3a9dSCharles Perry	select FPGA_MGR_XILINX_CORE
82061c97d1SAnatolij Gustschin	help
83061c97d1SAnatolij Gustschin	  FPGA manager driver support for Xilinx FPGA configuration
84061c97d1SAnatolij Gustschin	  over slave serial interface.
85061c97d1SAnatolij Gustschin
8684e93f1dSAlan Tullconfig FPGA_MGR_ICE40_SPI
8784e93f1dSAlan Tull	tristate "Lattice iCE40 SPI"
8884e93f1dSAlan Tull	depends on OF && SPI
8937784706SMoritz Fischer	help
9084e93f1dSAlan Tull	  FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
9184e93f1dSAlan Tull
9288fb3a00SPaolo Pisaticonfig FPGA_MGR_MACHXO2_SPI
9388fb3a00SPaolo Pisati	tristate "Lattice MachXO2 SPI"
9488fb3a00SPaolo Pisati	depends on SPI
9588fb3a00SPaolo Pisati	help
9688fb3a00SPaolo Pisati	  FPGA manager driver support for Lattice MachXO2 configuration
9788fb3a00SPaolo Pisati	  over slave SPI interface.
9888fb3a00SPaolo Pisati
9984e93f1dSAlan Tullconfig FPGA_MGR_TS73XX
10084e93f1dSAlan Tull	tristate "Technologic Systems TS-73xx SBC FPGA Manager"
10184e93f1dSAlan Tull	depends on ARCH_EP93XX && MACH_TS72XX
10284e93f1dSAlan Tull	help
10384e93f1dSAlan Tull	  FPGA manager driver support for the Altera Cyclone II FPGA
10484e93f1dSAlan Tull	  present on the TS-73xx SBC boards.
10537784706SMoritz Fischer
10621aeda95SAlan Tullconfig FPGA_BRIDGE
10721aeda95SAlan Tull	tristate "FPGA Bridge Framework"
10821aeda95SAlan Tull	help
10921aeda95SAlan Tull	  Say Y here if you want to support bridges connected between host
11021aeda95SAlan Tull	  processors and FPGAs or between FPGAs.
11121aeda95SAlan Tull
112e5f8efa5SAlan Tullconfig SOCFPGA_FPGA_BRIDGE
113e5f8efa5SAlan Tull	tristate "Altera SoCFPGA FPGA Bridges"
1143a1fef70SKrzysztof Kozlowski	depends on ARCH_INTEL_SOCFPGA && FPGA_BRIDGE
115e5f8efa5SAlan Tull	help
116e5f8efa5SAlan Tull	  Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
117e5f8efa5SAlan Tull	  devices.
118e5f8efa5SAlan Tull
119ca24a648SAlan Tullconfig ALTERA_FREEZE_BRIDGE
120ca24a648SAlan Tull	tristate "Altera FPGA Freeze Bridge"
12138cd7ad5SAlan Tull	depends on FPGA_BRIDGE && HAS_IOMEM
122ca24a648SAlan Tull	help
123ca24a648SAlan Tull	  Say Y to enable drivers for Altera FPGA Freeze bridges.  A
124ca24a648SAlan Tull	  freeze bridge is a bridge that exists in the FPGA fabric to
125ca24a648SAlan Tull	  isolate one region of the FPGA from the busses while that
126ca24a648SAlan Tull	  region is being reprogrammed.
127ca24a648SAlan Tull
1287e961c12SMoritz Fischerconfig XILINX_PR_DECOUPLER
1297e961c12SMoritz Fischer	tristate "Xilinx LogiCORE PR Decoupler"
1307e961c12SMoritz Fischer	depends on FPGA_BRIDGE
1317e961c12SMoritz Fischer	depends on HAS_IOMEM
1327e961c12SMoritz Fischer	help
13330a2ac9aSNava kishore Manne	  Say Y to enable drivers for Xilinx LogiCORE PR Decoupler
1345f1895e0SColin Ian King	  or Xilinx Dynamic Function eXchange AIX Shutdown Manager.
1357e961c12SMoritz Fischer	  The PR Decoupler exists in the FPGA fabric to isolate one
1367e961c12SMoritz Fischer	  region of the FPGA from the busses while that region is
1377e961c12SMoritz Fischer	  being reprogrammed during partial reconfig.
13830a2ac9aSNava kishore Manne	  The Dynamic Function eXchange AXI shutdown manager prevents
13930a2ac9aSNava kishore Manne	  AXI traffic from passing through the bridge. The controller
14030a2ac9aSNava kishore Manne	  safely handles AXI4MM and AXI4-Lite interfaces on a
14130a2ac9aSNava kishore Manne	  Reconfigurable Partition when it is undergoing dynamic
14230a2ac9aSNava kishore Manne	  reconfiguration, preventing the system deadlock that can
14330a2ac9aSNava kishore Manne	  occur if AXI transactions are interrupted by DFX.
1447e961c12SMoritz Fischer
14584e93f1dSAlan Tullconfig FPGA_REGION
14684e93f1dSAlan Tull	tristate "FPGA Region"
14784e93f1dSAlan Tull	depends on FPGA_BRIDGE
14884e93f1dSAlan Tull	help
149df82d2ecSTom Rix	  FPGA Region common code.  An FPGA Region controls an FPGA Manager
15084e93f1dSAlan Tull	  and the FPGA Bridges associated with either a reconfigurable
15184e93f1dSAlan Tull	  region of an FPGA or a whole FPGA.
15284e93f1dSAlan Tull
15384e93f1dSAlan Tullconfig OF_FPGA_REGION
15484e93f1dSAlan Tull	tristate "FPGA Region Device Tree Overlay Support"
15584e93f1dSAlan Tull	depends on OF && FPGA_REGION
15684e93f1dSAlan Tull	help
15784e93f1dSAlan Tull	  Support for loading FPGA images by applying a Device Tree
15884e93f1dSAlan Tull	  overlay.
15984e93f1dSAlan Tull
160543be3d8SWu Haoconfig FPGA_DFL
161543be3d8SWu Hao	tristate "FPGA Device Feature List (DFL) support"
162543be3d8SWu Hao	select FPGA_BRIDGE
163543be3d8SWu Hao	select FPGA_REGION
1641a16af33SDavid Gow	depends on HAS_IOMEM
165543be3d8SWu Hao	help
166543be3d8SWu Hao	  Device Feature List (DFL) defines a feature list structure that
167543be3d8SWu Hao	  creates a linked list of feature headers within the MMIO space
168543be3d8SWu Hao	  to provide an extensible way of adding features for FPGA.
169543be3d8SWu Hao	  Driver can walk through the feature headers to enumerate feature
170543be3d8SWu Hao	  devices (e.g. FPGA Management Engine, Port and Accelerator
171543be3d8SWu Hao	  Function Unit) and their private features for target FPGA devices.
172543be3d8SWu Hao
173543be3d8SWu Hao	  Select this option to enable common support for Field-Programmable
174543be3d8SWu Hao	  Gate Array (FPGA) solutions which implement Device Feature List.
175543be3d8SWu Hao	  It provides enumeration APIs and feature device infrastructure.
176543be3d8SWu Hao
177322ddebeSKang Luweiconfig FPGA_DFL_FME
178322ddebeSKang Luwei	tristate "FPGA DFL FME Driver"
179724142f8SWu Hao	depends on FPGA_DFL && HWMON && PERF_EVENTS
180322ddebeSKang Luwei	help
181322ddebeSKang Luwei	  The FPGA Management Engine (FME) is a feature device implemented
182322ddebeSKang Luwei	  under Device Feature List (DFL) framework. Select this option to
183322ddebeSKang Luwei	  enable the platform device driver for FME which implements all
184322ddebeSKang Luwei	  FPGA platform level management features. There shall be one FME
185322ddebeSKang Luwei	  per DFL based FPGA device.
186322ddebeSKang Luwei
187af275ec6SWu Haoconfig FPGA_DFL_FME_MGR
188af275ec6SWu Hao	tristate "FPGA DFL FME Manager Driver"
189af275ec6SWu Hao	depends on FPGA_DFL_FME && HAS_IOMEM
190af275ec6SWu Hao	help
191af275ec6SWu Hao	  Say Y to enable FPGA Manager driver for FPGA Management Engine.
192af275ec6SWu Hao
193de892dffSWu Haoconfig FPGA_DFL_FME_BRIDGE
194de892dffSWu Hao	tristate "FPGA DFL FME Bridge Driver"
195de892dffSWu Hao	depends on FPGA_DFL_FME && HAS_IOMEM
196de892dffSWu Hao	help
197de892dffSWu Hao	  Say Y to enable FPGA Bridge driver for FPGA Management Engine.
198de892dffSWu Hao
199bb61b9beSWu Haoconfig FPGA_DFL_FME_REGION
200bb61b9beSWu Hao	tristate "FPGA DFL FME Region Driver"
201bb61b9beSWu Hao	depends on FPGA_DFL_FME && HAS_IOMEM
202bb61b9beSWu Hao	help
203bb61b9beSWu Hao	  Say Y to enable FPGA Region driver for FPGA Management Engine.
204bb61b9beSWu Hao
2051a1527cfSWu Haoconfig FPGA_DFL_AFU
2061a1527cfSWu Hao	tristate "FPGA DFL AFU Driver"
2071a1527cfSWu Hao	depends on FPGA_DFL
2081a1527cfSWu Hao	help
2091a1527cfSWu Hao	  This is the driver for FPGA Accelerated Function Unit (AFU) which
2101a1527cfSWu Hao	  implements AFU and Port management features. A User AFU connects
2111a1527cfSWu Hao	  to the FPGA infrastructure via a Port. There may be more than one
2121a1527cfSWu Hao	  Port/AFU per DFL based FPGA device.
2131a1527cfSWu Hao
21456172ab3SXu Yilunconfig FPGA_DFL_NIOS_INTEL_PAC_N3000
21556172ab3SXu Yilun	tristate "FPGA DFL NIOS Driver for Intel PAC N3000"
21656172ab3SXu Yilun	depends on FPGA_DFL
21756172ab3SXu Yilun	select REGMAP
21856172ab3SXu Yilun	help
21956172ab3SXu Yilun	  This is the driver for the N3000 Nios private feature on Intel
22056172ab3SXu Yilun	  PAC (Programmable Acceleration Card) N3000. It communicates
22156172ab3SXu Yilun	  with the embedded Nios processor to configure the retimers on
22256172ab3SXu Yilun	  the card. It also instantiates the SPI master (spi-altera) for
22356172ab3SXu Yilun	  the card's BMC (Board Management Controller).
22456172ab3SXu Yilun
22572ddd9f3SZhang Yiconfig FPGA_DFL_PCI
22672ddd9f3SZhang Yi	tristate "FPGA DFL PCIe Device Driver"
22772ddd9f3SZhang Yi	depends on PCI && FPGA_DFL
22872ddd9f3SZhang Yi	help
22972ddd9f3SZhang Yi	  Select this option to enable PCIe driver for PCIe-based
23072ddd9f3SZhang Yi	  Field-Programmable Gate Array (FPGA) solutions which implement
23172ddd9f3SZhang Yi	  the Device Feature List (DFL). This driver provides interfaces
23272ddd9f3SZhang Yi	  for userspace applications to configure, enumerate, open and access
23372ddd9f3SZhang Yi	  FPGA accelerators on the FPGA DFL devices, enables system level
23472ddd9f3SZhang Yi	  management functions such as FPGA partial reconfiguration, power
23572ddd9f3SZhang Yi	  management and virtualization with DFL framework and DFL feature
23672ddd9f3SZhang Yi	  device drivers.
23772ddd9f3SZhang Yi
23872ddd9f3SZhang Yi	  To compile this as a module, choose M here.
23972ddd9f3SZhang Yi
240c09f7471SNava kishore Manneconfig FPGA_MGR_ZYNQMP_FPGA
241c09f7471SNava kishore Manne	tristate "Xilinx ZynqMP FPGA"
2426a47d6efSArnd Bergmann	depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST)
243c09f7471SNava kishore Manne	help
244c09f7471SNava kishore Manne	  FPGA manager driver support for Xilinx ZynqMP FPGAs.
245c09f7471SNava kishore Manne	  This driver uses the processor configuration port(PCAP)
246c09f7471SNava kishore Manne	  to configure the programmable logic(PL) through PS
247c09f7471SNava kishore Manne	  on ZynqMP SoC.
248c09f7471SNava kishore Manne
24901c54e62SNava kishore Manneconfig FPGA_MGR_VERSAL_FPGA
25001c54e62SNava kishore Manne	tristate "Xilinx Versal FPGA"
25101c54e62SNava kishore Manne	depends on ARCH_ZYNQMP || COMPILE_TEST
25201c54e62SNava kishore Manne	help
25301c54e62SNava kishore Manne	  Select this option to enable FPGA manager driver support for
25401c54e62SNava kishore Manne	  Xilinx Versal SoC. This driver uses the firmware interface to
25501c54e62SNava kishore Manne	  configure the programmable logic(PL).
25601c54e62SNava kishore Manne
25701c54e62SNava kishore Manne	  To compile this as a module, choose M here.
258bdf86d0eSRuss Weight
259bdf86d0eSRuss Weightconfig FPGA_M10_BMC_SEC_UPDATE
260bdf86d0eSRuss Weight	tristate "Intel MAX10 BMC Secure Update driver"
261603aed8fSIlpo Järvinen	depends on MFD_INTEL_M10_BMC_CORE
262dfd10332SRuss Weight	select FW_LOADER
263dfd10332SRuss Weight	select FW_UPLOAD
264bdf86d0eSRuss Weight	help
265bdf86d0eSRuss Weight	  Secure update support for the Intel MAX10 board management
266bdf86d0eSRuss Weight	  controller.
267bdf86d0eSRuss Weight
268bdf86d0eSRuss Weight	  This is a subdriver of the Intel MAX10 board management controller
269bdf86d0eSRuss Weight	  (BMC) and provides support for secure updates for the BMC image,
270bdf86d0eSRuss Weight	  the FPGA image, the Root Entry Hashes, etc.
271bdf86d0eSRuss Weight
2725f8d4a90SIvan Bornyakovconfig FPGA_MGR_MICROCHIP_SPI
2735f8d4a90SIvan Bornyakov	tristate "Microchip Polarfire SPI FPGA manager"
2745f8d4a90SIvan Bornyakov	depends on SPI
2755f8d4a90SIvan Bornyakov	help
2765f8d4a90SIvan Bornyakov	  FPGA manager driver support for Microchip Polarfire FPGAs
2775f8d4a90SIvan Bornyakov	  programming over slave SPI interface with .dat formatted
2785f8d4a90SIvan Bornyakov	  bitstream image.
2795f8d4a90SIvan Bornyakov
280463dd43bSIvan Bornyakovconfig FPGA_MGR_LATTICE_SYSCONFIG
281463dd43bSIvan Bornyakov	tristate
282463dd43bSIvan Bornyakov
283463dd43bSIvan Bornyakovconfig FPGA_MGR_LATTICE_SYSCONFIG_SPI
284463dd43bSIvan Bornyakov	tristate "Lattice sysCONFIG SPI FPGA manager"
285463dd43bSIvan Bornyakov	depends on SPI
286463dd43bSIvan Bornyakov	select FPGA_MGR_LATTICE_SYSCONFIG
287463dd43bSIvan Bornyakov	help
288463dd43bSIvan Bornyakov	  FPGA manager driver support for Lattice FPGAs programming over slave
289463dd43bSIvan Bornyakov	  SPI sysCONFIG interface.
290463dd43bSIvan Bornyakov
2913969f645SMarco Paganisource "drivers/fpga/tests/Kconfig"
2923969f645SMarco Pagani
293fab6266eSAlan Tullendif # FPGA
294