1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Texas Instruments System Control Interface (TISCI) Protocol 4 * 5 * Communication protocol with TI SCI hardware 6 * The system works in a message response protocol 7 * See: https://software-dl.ti.com/tisci/esd/latest/index.html for details 8 * 9 * Copyright (C) 2015-2024 Texas Instruments Incorporated - https://www.ti.com/ 10 */ 11 12 #ifndef __TI_SCI_H 13 #define __TI_SCI_H 14 15 /* Generic Messages */ 16 #define TI_SCI_MSG_ENABLE_WDT 0x0000 17 #define TI_SCI_MSG_WAKE_RESET 0x0001 18 #define TI_SCI_MSG_VERSION 0x0002 19 #define TI_SCI_MSG_WAKE_REASON 0x0003 20 #define TI_SCI_MSG_GOODBYE 0x0004 21 #define TI_SCI_MSG_SYS_RESET 0x0005 22 #define TI_SCI_MSG_QUERY_FW_CAPS 0x0022 23 24 /* Device requests */ 25 #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200 26 #define TI_SCI_MSG_GET_DEVICE_STATE 0x0201 27 #define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202 28 29 /* Clock requests */ 30 #define TI_SCI_MSG_SET_CLOCK_STATE 0x0100 31 #define TI_SCI_MSG_GET_CLOCK_STATE 0x0101 32 #define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102 33 #define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103 34 #define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104 35 #define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c 36 #define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d 37 #define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e 38 39 /* Low Power Mode Requests */ 40 #define TI_SCI_MSG_PREPARE_SLEEP 0x0300 41 #define TI_SCI_MSG_LPM_WAKE_REASON 0x0306 42 #define TI_SCI_MSG_SET_IO_ISOLATION 0x0307 43 #define TI_SCI_MSG_LPM_SET_DEVICE_CONSTRAINT 0x0309 44 #define TI_SCI_MSG_LPM_SET_LATENCY_CONSTRAINT 0x030A 45 #define TI_SCI_MSG_LPM_ABORT 0x0311 46 47 /* Resource Management Requests */ 48 #define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500 49 50 /* IRQ requests */ 51 #define TI_SCI_MSG_SET_IRQ 0x1000 52 #define TI_SCI_MSG_FREE_IRQ 0x1001 53 54 /* NAVSS resource management */ 55 /* Ringacc requests */ 56 #define TI_SCI_MSG_RM_RING_ALLOCATE 0x1100 57 #define TI_SCI_MSG_RM_RING_FREE 0x1101 58 #define TI_SCI_MSG_RM_RING_RECONFIG 0x1102 59 #define TI_SCI_MSG_RM_RING_RESET 0x1103 60 #define TI_SCI_MSG_RM_RING_CFG 0x1110 61 62 /* PSI-L requests */ 63 #define TI_SCI_MSG_RM_PSIL_PAIR 0x1280 64 #define TI_SCI_MSG_RM_PSIL_UNPAIR 0x1281 65 66 #define TI_SCI_MSG_RM_UDMAP_TX_ALLOC 0x1200 67 #define TI_SCI_MSG_RM_UDMAP_TX_FREE 0x1201 68 #define TI_SCI_MSG_RM_UDMAP_RX_ALLOC 0x1210 69 #define TI_SCI_MSG_RM_UDMAP_RX_FREE 0x1211 70 #define TI_SCI_MSG_RM_UDMAP_FLOW_CFG 0x1220 71 #define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG 0x1221 72 73 #define TISCI_MSG_RM_UDMAP_TX_CH_CFG 0x1205 74 #define TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG 0x1206 75 #define TISCI_MSG_RM_UDMAP_RX_CH_CFG 0x1215 76 #define TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG 0x1216 77 #define TISCI_MSG_RM_UDMAP_FLOW_CFG 0x1230 78 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG 0x1231 79 #define TISCI_MSG_RM_UDMAP_FLOW_GET_CFG 0x1232 80 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG 0x1233 81 82 /* Processor Control requests */ 83 #define TI_SCI_MSG_PROC_REQUEST 0xc000 84 #define TI_SCI_MSG_PROC_RELEASE 0xc001 85 #define TI_SCI_MSG_PROC_HANDOVER 0xc005 86 #define TI_SCI_MSG_SET_CONFIG 0xc100 87 #define TI_SCI_MSG_SET_CTRL 0xc101 88 #define TI_SCI_MSG_GET_STATUS 0xc400 89 90 /** 91 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses 92 * @type: Type of messages: One of TI_SCI_MSG* values 93 * @host: Host of the message 94 * @seq: Message identifier indicating a transfer sequence 95 * @flags: Flag for the message 96 */ 97 struct ti_sci_msg_hdr { 98 u16 type; 99 u8 host; 100 u8 seq; 101 #define TI_SCI_MSG_FLAG(val) (1 << (val)) 102 #define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0 103 #define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0) 104 #define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1) 105 #define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0 106 #define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1) 107 /* Additional Flags */ 108 u32 flags; 109 } __packed; 110 111 /** 112 * struct ti_sci_msg_resp_version - Response for a message 113 * @hdr: Generic header 114 * @firmware_description: String describing the firmware 115 * @firmware_revision: Firmware revision 116 * @abi_major: Major version of the ABI that firmware supports 117 * @abi_minor: Minor version of the ABI that firmware supports 118 * 119 * In general, ABI version changes follow the rule that minor version increments 120 * are backward compatible. Major revision changes in ABI may not be 121 * backward compatible. 122 * 123 * Response to a generic message with message type TI_SCI_MSG_VERSION 124 */ 125 struct ti_sci_msg_resp_version { 126 struct ti_sci_msg_hdr hdr; 127 char firmware_description[32]; 128 u16 firmware_revision; 129 u8 abi_major; 130 u8 abi_minor; 131 } __packed; 132 133 /** 134 * struct ti_sci_msg_req_reboot - Reboot the SoC 135 * @hdr: Generic Header 136 * 137 * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic 138 * ACK/NACK message. 139 */ 140 struct ti_sci_msg_req_reboot { 141 struct ti_sci_msg_hdr hdr; 142 } __packed; 143 144 /** 145 * struct ti_sci_msg_resp_query_fw_caps - Response for query firmware caps 146 * @hdr: Generic header 147 * @fw_caps: Each bit in fw_caps indicating one FW/SOC capability 148 * MSG_FLAG_CAPS_GENERIC: Generic capability (LPM not supported) 149 * MSG_FLAG_CAPS_LPM_PARTIAL_IO: Partial IO in LPM 150 * MSG_FLAG_CAPS_LPM_DM_MANAGED: LPM can be managed by DM 151 * MSG_FLAG_CAPS_LPM_ABORT: Abort entry to LPM 152 * MSG_FLAG_CAPS_IO_ISOLATION: IO Isolation support 153 * MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED: LPM config done statically 154 * for the DM via boardcfg 155 * MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST: DM is not able to restore IRQ 156 * context 157 * MSG_FLAG_CAPS_LPM_CLK_CONTEXT_LOST: DM is not able to restore 158 * Clock context 159 * 160 * Response to a generic message with message type TI_SCI_MSG_QUERY_FW_CAPS 161 * providing currently available SOC/firmware capabilities. SoC that don't 162 * support low power modes return only MSG_FLAG_CAPS_GENERIC capability. 163 */ 164 struct ti_sci_msg_resp_query_fw_caps { 165 struct ti_sci_msg_hdr hdr; 166 #define MSG_FLAG_CAPS_GENERIC TI_SCI_MSG_FLAG(0) 167 #define MSG_FLAG_CAPS_LPM_PARTIAL_IO TI_SCI_MSG_FLAG(4) 168 #define MSG_FLAG_CAPS_LPM_DM_MANAGED TI_SCI_MSG_FLAG(5) 169 #define MSG_FLAG_CAPS_LPM_ABORT TI_SCI_MSG_FLAG(9) 170 #define MSG_FLAG_CAPS_IO_ISOLATION TI_SCI_MSG_FLAG(7) 171 #define MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED TI_SCI_MSG_FLAG(12) 172 #define MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST TI_SCI_MSG_FLAG(14) 173 #define MSG_FLAG_CAPS_LPM_CLK_CONTEXT_LOST TI_SCI_MSG_FLAG(15) 174 #define MSG_MASK_CAPS_LPM GENMASK_ULL(4, 1) 175 u64 fw_caps; 176 } __packed; 177 178 /** 179 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device 180 * @hdr: Generic header 181 * @id: Indicates which device to modify 182 * @reserved: Reserved space in message, must be 0 for backward compatibility 183 * @state: The desired state of the device. 184 * 185 * Certain flags can also be set to alter the device state: 186 * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source. 187 * The meaning of this flag will vary slightly from device to device and from 188 * SoC to SoC but it generally allows the device to wake the SoC out of deep 189 * suspend states. 190 * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device. 191 * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed 192 * with STATE_RETENTION or STATE_ON, it will claim the device exclusively. 193 * If another host already has this device set to STATE_RETENTION or STATE_ON, 194 * the message will fail. Once successful, other hosts attempting to set 195 * STATE_RETENTION or STATE_ON will fail. 196 * 197 * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic 198 * ACK/NACK message. 199 */ 200 struct ti_sci_msg_req_set_device_state { 201 /* Additional hdr->flags options */ 202 #define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8) 203 #define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9) 204 #define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10) 205 struct ti_sci_msg_hdr hdr; 206 u32 id; 207 u32 reserved; 208 209 #define MSG_DEVICE_SW_STATE_AUTO_OFF 0 210 #define MSG_DEVICE_SW_STATE_RETENTION 1 211 #define MSG_DEVICE_SW_STATE_ON 2 212 u8 state; 213 } __packed; 214 215 /** 216 * struct ti_sci_msg_req_get_device_state - Request to get device. 217 * @hdr: Generic header 218 * @id: Device Identifier 219 * 220 * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state 221 * information 222 */ 223 struct ti_sci_msg_req_get_device_state { 224 struct ti_sci_msg_hdr hdr; 225 u32 id; 226 } __packed; 227 228 /** 229 * struct ti_sci_msg_resp_get_device_state - Response to get device request. 230 * @hdr: Generic header 231 * @context_loss_count: Indicates how many times the device has lost context. A 232 * driver can use this monotonic counter to determine if the device has 233 * lost context since the last time this message was exchanged. 234 * @resets: Programmed state of the reset lines. 235 * @programmed_state: The state as programmed by set_device. 236 * - Uses the MSG_DEVICE_SW_* macros 237 * @current_state: The actual state of the hardware. 238 * 239 * Response to request TI_SCI_MSG_GET_DEVICE_STATE. 240 */ 241 struct ti_sci_msg_resp_get_device_state { 242 struct ti_sci_msg_hdr hdr; 243 u32 context_loss_count; 244 u32 resets; 245 u8 programmed_state; 246 #define MSG_DEVICE_HW_STATE_OFF 0 247 #define MSG_DEVICE_HW_STATE_ON 1 248 #define MSG_DEVICE_HW_STATE_TRANS 2 249 u8 current_state; 250 } __packed; 251 252 /** 253 * struct ti_sci_msg_req_set_device_resets - Set the desired resets 254 * configuration of the device 255 * @hdr: Generic header 256 * @id: Indicates which device to modify 257 * @resets: A bit field of resets for the device. The meaning, behavior, 258 * and usage of the reset flags are device specific. 0 for a bit 259 * indicates releasing the reset represented by that bit while 1 260 * indicates keeping it held. 261 * 262 * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic 263 * ACK/NACK message. 264 */ 265 struct ti_sci_msg_req_set_device_resets { 266 struct ti_sci_msg_hdr hdr; 267 u32 id; 268 u32 resets; 269 } __packed; 270 271 /** 272 * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state 273 * @hdr: Generic Header, Certain flags can be set specific to the clocks: 274 * MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified 275 * via spread spectrum clocking. 276 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's 277 * frequency to be changed while it is running so long as it 278 * is within the min/max limits. 279 * MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this 280 * is only applicable to clock inputs on the SoC pseudo-device. 281 * @dev_id: Device identifier this request is for 282 * @clk_id: Clock identifier for the device for this request. 283 * Each device has it's own set of clock inputs. This indexes 284 * which clock input to modify. Set to 255 if clock ID is 285 * greater than or equal to 255. 286 * @request_state: Request the state for the clock to be set to. 287 * MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock, 288 * it can be disabled, regardless of the state of the device 289 * MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to 290 * automatically manage the state of this clock. If the device 291 * is enabled, then the clock is enabled. If the device is set 292 * to off or retention, then the clock is internally set as not 293 * being required by the device.(default) 294 * MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled, 295 * regardless of the state of the device. 296 * @clk_id_32: Clock identifier for the device for this request. 297 * Only to be used if the clock ID is greater than or equal to 298 * 255. 299 * 300 * Normally, all required clocks are managed by TISCI entity, this is used 301 * only for specific control *IF* required. Auto managed state is 302 * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote 303 * will explicitly control. 304 * 305 * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic 306 * ACK or NACK message. 307 */ 308 struct ti_sci_msg_req_set_clock_state { 309 /* Additional hdr->flags options */ 310 #define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8) 311 #define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9) 312 #define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10) 313 struct ti_sci_msg_hdr hdr; 314 u32 dev_id; 315 u8 clk_id; 316 #define MSG_CLOCK_SW_STATE_UNREQ 0 317 #define MSG_CLOCK_SW_STATE_AUTO 1 318 #define MSG_CLOCK_SW_STATE_REQ 2 319 u8 request_state; 320 u32 clk_id_32; 321 } __packed; 322 323 /** 324 * struct ti_sci_msg_req_get_clock_state - Request for clock state 325 * @hdr: Generic Header 326 * @dev_id: Device identifier this request is for 327 * @clk_id: Clock identifier for the device for this request. 328 * Each device has it's own set of clock inputs. This indexes 329 * which clock input to get state of. Set to 255 if the clock 330 * ID is greater than or equal to 255. 331 * @clk_id_32: Clock identifier for the device for the request. 332 * Only to be used if the clock ID is greater than or equal to 333 * 255. 334 * 335 * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state 336 * of the clock 337 */ 338 struct ti_sci_msg_req_get_clock_state { 339 struct ti_sci_msg_hdr hdr; 340 u32 dev_id; 341 u8 clk_id; 342 u32 clk_id_32; 343 } __packed; 344 345 /** 346 * struct ti_sci_msg_resp_get_clock_state - Response to get clock state 347 * @hdr: Generic Header 348 * @programmed_state: Any programmed state of the clock. This is one of 349 * MSG_CLOCK_SW_STATE* values. 350 * @current_state: Current state of the clock. This is one of: 351 * MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready 352 * MSG_CLOCK_HW_STATE_READY: Clock is ready 353 * 354 * Response to TI_SCI_MSG_GET_CLOCK_STATE. 355 */ 356 struct ti_sci_msg_resp_get_clock_state { 357 struct ti_sci_msg_hdr hdr; 358 u8 programmed_state; 359 #define MSG_CLOCK_HW_STATE_NOT_READY 0 360 #define MSG_CLOCK_HW_STATE_READY 1 361 u8 current_state; 362 } __packed; 363 364 /** 365 * struct ti_sci_msg_req_set_clock_parent - Set the clock parent 366 * @hdr: Generic Header 367 * @dev_id: Device identifier this request is for 368 * @clk_id: Clock identifier for the device for this request. 369 * Each device has it's own set of clock inputs. This indexes 370 * which clock input to modify. Set to 255 if clock ID is 371 * greater than or equal to 255. 372 * @parent_id: The new clock parent is selectable by an index via this 373 * parameter. Set to 255 if clock ID is greater than or 374 * equal to 255. 375 * @clk_id_32: Clock identifier if @clk_id field is 255. 376 * @parent_id_32: Parent identifier if @parent_id is 255. 377 * 378 * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic 379 * ACK / NACK message. 380 */ 381 struct ti_sci_msg_req_set_clock_parent { 382 struct ti_sci_msg_hdr hdr; 383 u32 dev_id; 384 u8 clk_id; 385 u8 parent_id; 386 u32 clk_id_32; 387 u32 parent_id_32; 388 } __packed; 389 390 /** 391 * struct ti_sci_msg_req_get_clock_parent - Get the clock parent 392 * @hdr: Generic Header 393 * @dev_id: Device identifier this request is for 394 * @clk_id: Clock identifier for the device for this request. 395 * Each device has it's own set of clock inputs. This indexes 396 * which clock input to get the parent for. If this field 397 * contains 255, the actual clock identifier is stored in 398 * @clk_id_32. 399 * @clk_id_32: Clock identifier if the @clk_id field contains 255. 400 * 401 * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information 402 */ 403 struct ti_sci_msg_req_get_clock_parent { 404 struct ti_sci_msg_hdr hdr; 405 u32 dev_id; 406 u8 clk_id; 407 u32 clk_id_32; 408 } __packed; 409 410 /** 411 * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent 412 * @hdr: Generic Header 413 * @parent_id: The current clock parent. If set to 255, the current parent 414 * ID can be found from the @parent_id_32 field. 415 * @parent_id_32: Current clock parent if @parent_id field is set to 416 * 255. 417 * 418 * Response to TI_SCI_MSG_GET_CLOCK_PARENT. 419 */ 420 struct ti_sci_msg_resp_get_clock_parent { 421 struct ti_sci_msg_hdr hdr; 422 u8 parent_id; 423 u32 parent_id_32; 424 } __packed; 425 426 /** 427 * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents 428 * @hdr: Generic header 429 * @dev_id: Device identifier this request is for 430 * @clk_id: Clock identifier for the device for this request. Set to 431 * 255 if clock ID is greater than or equal to 255. 432 * @clk_id_32: Clock identifier if the @clk_id field contains 255. 433 * 434 * This request provides information about how many clock parent options 435 * are available for a given clock to a device. This is typically used 436 * for input clocks. 437 * 438 * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate 439 * message, or NACK in case of inability to satisfy request. 440 */ 441 struct ti_sci_msg_req_get_clock_num_parents { 442 struct ti_sci_msg_hdr hdr; 443 u32 dev_id; 444 u8 clk_id; 445 u32 clk_id_32; 446 } __packed; 447 448 /** 449 * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents 450 * @hdr: Generic header 451 * @num_parents: Number of clock parents. If set to 255, the actual 452 * number of parents is stored into @num_parents_32 453 * field instead. 454 * @num_parents_32: Number of clock parents if @num_parents field is 455 * set to 255. 456 * 457 * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 458 */ 459 struct ti_sci_msg_resp_get_clock_num_parents { 460 struct ti_sci_msg_hdr hdr; 461 u8 num_parents; 462 u32 num_parents_32; 463 } __packed; 464 465 /** 466 * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency 467 * @hdr: Generic Header 468 * @dev_id: Device identifier this request is for 469 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum 470 * allowable programmed frequency and does not account for clock 471 * tolerances and jitter. 472 * @target_freq_hz: The target clock frequency. A frequency will be found 473 * as close to this target frequency as possible. 474 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum 475 * allowable programmed frequency and does not account for clock 476 * tolerances and jitter. 477 * @clk_id: Clock identifier for the device for this request. Set to 478 * 255 if clock identifier is greater than or equal to 255. 479 * @clk_id_32: Clock identifier if @clk_id is set to 255. 480 * 481 * NOTE: Normally clock frequency management is automatically done by TISCI 482 * entity. In case of specific requests, TISCI evaluates capability to achieve 483 * requested frequency within provided range and responds with 484 * result message. 485 * 486 * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message, 487 * or NACK in case of inability to satisfy request. 488 */ 489 struct ti_sci_msg_req_query_clock_freq { 490 struct ti_sci_msg_hdr hdr; 491 u32 dev_id; 492 u64 min_freq_hz; 493 u64 target_freq_hz; 494 u64 max_freq_hz; 495 u8 clk_id; 496 u32 clk_id_32; 497 } __packed; 498 499 /** 500 * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query 501 * @hdr: Generic Header 502 * @freq_hz: Frequency that is the best match in Hz. 503 * 504 * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request 505 * cannot be satisfied, the message will be of type NACK. 506 */ 507 struct ti_sci_msg_resp_query_clock_freq { 508 struct ti_sci_msg_hdr hdr; 509 u64 freq_hz; 510 } __packed; 511 512 /** 513 * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency 514 * @hdr: Generic Header 515 * @dev_id: Device identifier this request is for 516 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum 517 * allowable programmed frequency and does not account for clock 518 * tolerances and jitter. 519 * @target_freq_hz: The target clock frequency. The clock will be programmed 520 * at a rate as close to this target frequency as possible. 521 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum 522 * allowable programmed frequency and does not account for clock 523 * tolerances and jitter. 524 * @clk_id: Clock identifier for the device for this request. Set to 525 * 255 if clock ID is greater than or equal to 255. 526 * @clk_id_32: Clock identifier if @clk_id field is set to 255. 527 * 528 * NOTE: Normally clock frequency management is automatically done by TISCI 529 * entity. In case of specific requests, TISCI evaluates capability to achieve 530 * requested range and responds with success/failure message. 531 * 532 * This sets the desired frequency for a clock within an allowable 533 * range. This message will fail on an enabled clock unless 534 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally, 535 * if other clocks have their frequency modified due to this message, 536 * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled. 537 * 538 * Calling set frequency on a clock input to the SoC pseudo-device will 539 * inform the PMMC of that clock's frequency. Setting a frequency of 540 * zero will indicate the clock is disabled. 541 * 542 * Calling set frequency on clock outputs from the SoC pseudo-device will 543 * function similarly to setting the clock frequency on a device. 544 * 545 * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK 546 * message. 547 */ 548 struct ti_sci_msg_req_set_clock_freq { 549 struct ti_sci_msg_hdr hdr; 550 u32 dev_id; 551 u64 min_freq_hz; 552 u64 target_freq_hz; 553 u64 max_freq_hz; 554 u8 clk_id; 555 u32 clk_id_32; 556 } __packed; 557 558 /** 559 * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency 560 * @hdr: Generic Header 561 * @dev_id: Device identifier this request is for 562 * @clk_id: Clock identifier for the device for this request. Set to 563 * 255 if clock ID is greater than or equal to 255. 564 * @clk_id_32: Clock identifier if @clk_id field is set to 255. 565 * 566 * NOTE: Normally clock frequency management is automatically done by TISCI 567 * entity. In some cases, clock frequencies are configured by host. 568 * 569 * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency 570 * that the clock is currently at. 571 */ 572 struct ti_sci_msg_req_get_clock_freq { 573 struct ti_sci_msg_hdr hdr; 574 u32 dev_id; 575 u8 clk_id; 576 u32 clk_id_32; 577 } __packed; 578 579 /** 580 * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request 581 * @hdr: Generic Header 582 * @freq_hz: Frequency that the clock is currently on, in Hz. 583 * 584 * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ. 585 */ 586 struct ti_sci_msg_resp_get_clock_freq { 587 struct ti_sci_msg_hdr hdr; 588 u64 freq_hz; 589 } __packed; 590 591 /** 592 * struct ti_sci_msg_req_prepare_sleep - Request for TISCI_MSG_PREPARE_SLEEP. 593 * 594 * @hdr: TISCI header to provide ACK/NAK flags to the host. 595 * @mode: Low power mode to enter. 596 * @ctx_lo: Low 32-bits of physical pointer to address to use for context save. 597 * @ctx_hi: High 32-bits of physical pointer to address to use for context save. 598 * @debug_flags: Flags that can be set to halt the sequence during suspend or 599 * resume to allow JTAG connection and debug. 600 * 601 * This message is used as the first step of entering a low power mode. It 602 * allows configurable information, including which state to enter to be 603 * easily shared from the application, as this is a non-secure message and 604 * therefore can be sent by anyone. 605 */ 606 struct ti_sci_msg_req_prepare_sleep { 607 struct ti_sci_msg_hdr hdr; 608 609 /* 610 * When sending prepare_sleep with MODE_PARTIAL_IO no response will be sent, 611 * no further steps are required. 612 */ 613 #define TISCI_MSG_VALUE_SLEEP_MODE_PARTIAL_IO 0x03 614 #define TISCI_MSG_VALUE_SLEEP_MODE_DM_MANAGED 0xfd 615 u8 mode; 616 u32 ctx_lo; 617 u32 ctx_hi; 618 u32 debug_flags; 619 } __packed; 620 621 /** 622 * struct ti_sci_msg_req_set_io_isolation - Request for TI_SCI_MSG_SET_IO_ISOLATION. 623 * 624 * @hdr: Generic header 625 * @state: The deseared state of the IO isolation. 626 * 627 * This message is used to enable/disable IO isolation for low power modes. 628 * Response is generic ACK / NACK message. 629 */ 630 struct ti_sci_msg_req_set_io_isolation { 631 struct ti_sci_msg_hdr hdr; 632 u8 state; 633 } __packed; 634 635 /** 636 * struct ti_sci_msg_resp_lpm_wake_reason - Response for TI_SCI_MSG_LPM_WAKE_REASON. 637 * 638 * @hdr: Generic header. 639 * @wake_source: The wake up source that woke soc from LPM. 640 * @wake_timestamp: Timestamp at which soc woke. 641 * @wake_pin: The pin that has triggered wake up. 642 * @mode: The last entered low power mode. 643 * @rsvd: Reserved for future use. 644 * 645 * Response to a generic message with message type TI_SCI_MSG_LPM_WAKE_REASON, 646 * used to query the wake up source, pin and entered low power mode. 647 */ 648 struct ti_sci_msg_resp_lpm_wake_reason { 649 struct ti_sci_msg_hdr hdr; 650 u32 wake_source; 651 u64 wake_timestamp; 652 u8 wake_pin; 653 u8 mode; 654 u32 rsvd[2]; 655 } __packed; 656 657 /** 658 * struct ti_sci_msg_req_lpm_set_device_constraint - Request for 659 * TISCI_MSG_LPM_SET_DEVICE_CONSTRAINT. 660 * 661 * @hdr: TISCI header to provide ACK/NAK flags to the host. 662 * @id: Device ID of device whose constraint has to be modified. 663 * @state: The desired state of device constraint: set or clear. 664 * @rsvd: Reserved for future use. 665 * 666 * This message is used by host to set constraint on the device. This can be 667 * sent anytime after boot before prepare sleep message. Any device can set a 668 * constraint on the low power mode that the SoC can enter. It allows 669 * configurable information to be easily shared from the application, as this 670 * is a non-secure message and therefore can be sent by anyone. By setting a 671 * constraint, the device ensures that it will not be powered off or reset in 672 * the selected mode. Note: Access Restriction: Exclusivity flag of Device will 673 * be honored. If some other host already has constraint on this device ID, 674 * NACK will be returned. 675 */ 676 struct ti_sci_msg_req_lpm_set_device_constraint { 677 struct ti_sci_msg_hdr hdr; 678 u32 id; 679 u8 state; 680 u32 rsvd[2]; 681 } __packed; 682 683 /** 684 * struct ti_sci_msg_req_lpm_set_latency_constraint - Request for 685 * TISCI_MSG_LPM_SET_LATENCY_CONSTRAINT. 686 * 687 * @hdr: TISCI header to provide ACK/NAK flags to the host. 688 * @latency: The maximum acceptable latency to wake up from low power mode 689 * in milliseconds. The deeper the state, the higher the latency. 690 * @state: The desired state of wakeup latency constraint: set or clear. 691 * @rsvd: Reserved for future use. 692 * 693 * This message is used by host to set wakeup latency from low power mode. This can 694 * be sent anytime after boot before prepare sleep message, and can be sent after 695 * current low power mode is exited. Any device can set a constraint on the low power 696 * mode that the SoC can enter. It allows configurable information to be easily shared 697 * from the application, as this is a non-secure message and therefore can be sent by 698 * anyone. By setting a wakeup latency constraint, the host ensures that the resume time 699 * from selected low power mode will be less than the constraint value. 700 */ 701 struct ti_sci_msg_req_lpm_set_latency_constraint { 702 struct ti_sci_msg_hdr hdr; 703 u16 latency; 704 u8 state; 705 u32 rsvd; 706 } __packed; 707 708 #define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff 709 710 /** 711 * struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned 712 * range of resources. 713 * @hdr: Generic Header 714 * @type: Unique resource assignment type 715 * @subtype: Resource assignment subtype within the resource type. 716 * @secondary_host: Host processing entity to which the resources are 717 * allocated. This is required only when the destination 718 * host id id different from ti sci interface host id, 719 * else TI_SCI_IRQ_SECONDARY_HOST_INVALID can be passed. 720 * 721 * Request type is TI_SCI_MSG_GET_RESOURCE_RANGE. Responded with requested 722 * resource range which is of type TI_SCI_MSG_GET_RESOURCE_RANGE. 723 */ 724 struct ti_sci_msg_req_get_resource_range { 725 struct ti_sci_msg_hdr hdr; 726 #define MSG_RM_RESOURCE_TYPE_MASK GENMASK(9, 0) 727 #define MSG_RM_RESOURCE_SUBTYPE_MASK GENMASK(5, 0) 728 u16 type; 729 u8 subtype; 730 u8 secondary_host; 731 } __packed; 732 733 /** 734 * struct ti_sci_msg_resp_get_resource_range - Response to resource get range. 735 * @hdr: Generic Header 736 * @range_start: Start index of the first resource range. 737 * @range_num: Number of resources in the first range. 738 * @range_start_sec: Start index of the second resource range. 739 * @range_num_sec: Number of resources in the second range. 740 * 741 * Response to request TI_SCI_MSG_GET_RESOURCE_RANGE. 742 */ 743 struct ti_sci_msg_resp_get_resource_range { 744 struct ti_sci_msg_hdr hdr; 745 u16 range_start; 746 u16 range_num; 747 u16 range_start_sec; 748 u16 range_num_sec; 749 } __packed; 750 751 /** 752 * struct ti_sci_msg_req_manage_irq - Request to configure/release the route 753 * between the dev and the host. 754 * @hdr: Generic Header 755 * @valid_params: Bit fields defining the validity of interrupt source 756 * parameters. If a bit is not set, then corresponding 757 * field is not valid and will not be used for route set. 758 * Bit field definitions: 759 * 0 - Valid bit for @dst_id 760 * 1 - Valid bit for @dst_host_irq 761 * 2 - Valid bit for @ia_id 762 * 3 - Valid bit for @vint 763 * 4 - Valid bit for @global_event 764 * 5 - Valid bit for @vint_status_bit_index 765 * 31 - Valid bit for @secondary_host 766 * @src_id: IRQ source peripheral ID. 767 * @src_index: IRQ source index within the peripheral 768 * @dst_id: IRQ Destination ID. Based on the architecture it can be 769 * IRQ controller or host processor ID. 770 * @dst_host_irq: IRQ number of the destination host IRQ controller 771 * @ia_id: Device ID of the interrupt aggregator in which the 772 * vint resides. 773 * @vint: Virtual interrupt number if the interrupt route 774 * is through an interrupt aggregator. 775 * @global_event: Global event that is to be mapped to interrupt 776 * aggregator virtual interrupt status bit. 777 * @vint_status_bit: Virtual interrupt status bit if the interrupt route 778 * utilizes an interrupt aggregator status bit. 779 * @secondary_host: Host ID of the IRQ destination computing entity. This is 780 * required only when destination host id is different 781 * from ti sci interface host id. 782 * 783 * Request type is TI_SCI_MSG_SET/RELEASE_IRQ. 784 * Response is generic ACK / NACK message. 785 */ 786 struct ti_sci_msg_req_manage_irq { 787 struct ti_sci_msg_hdr hdr; 788 #define MSG_FLAG_DST_ID_VALID TI_SCI_MSG_FLAG(0) 789 #define MSG_FLAG_DST_HOST_IRQ_VALID TI_SCI_MSG_FLAG(1) 790 #define MSG_FLAG_IA_ID_VALID TI_SCI_MSG_FLAG(2) 791 #define MSG_FLAG_VINT_VALID TI_SCI_MSG_FLAG(3) 792 #define MSG_FLAG_GLB_EVNT_VALID TI_SCI_MSG_FLAG(4) 793 #define MSG_FLAG_VINT_STS_BIT_VALID TI_SCI_MSG_FLAG(5) 794 #define MSG_FLAG_SHOST_VALID TI_SCI_MSG_FLAG(31) 795 u32 valid_params; 796 u16 src_id; 797 u16 src_index; 798 u16 dst_id; 799 u16 dst_host_irq; 800 u16 ia_id; 801 u16 vint; 802 u16 global_event; 803 u8 vint_status_bit; 804 u8 secondary_host; 805 } __packed; 806 807 /** 808 * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring 809 * 810 * Configures the non-real-time registers of a Navigator Subsystem ring. 811 * @hdr: Generic Header 812 * @valid_params: Bitfield defining validity of ring configuration parameters. 813 * The ring configuration fields are not valid, and will not be used for 814 * ring configuration, if their corresponding valid bit is zero. 815 * Valid bit usage: 816 * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo 817 * 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi 818 * 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count 819 * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode 820 * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size 821 * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id 822 * 6 - Valid bit for @tisci_msg_rm_ring_cfg_req virtid 823 * 7 - Valid bit for @tisci_msg_rm_ring_cfg_req ASEL 824 * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated 825 * @index: ring index to be configured. 826 * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's 827 * RING_BA_LO register 828 * @addr_hi: 16 MSBs of ring base address to be programmed into the ring's 829 * RING_BA_HI register. 830 * @count: Number of ring elements. Must be even if mode is CREDENTIALS or QM 831 * modes. 832 * @mode: Specifies the mode the ring is to be configured. 833 * @size: Specifies encoded ring element size. To calculate the encoded size use 834 * the formula (log2(size_bytes) - 2), where size_bytes cannot be 835 * greater than 256. 836 * @order_id: Specifies the ring's bus order ID. 837 * @virtid: Ring virt ID value 838 * @asel: Ring ASEL (address select) value to be set into the ASEL field of the 839 * ring's RING_BA_HI register. 840 */ 841 struct ti_sci_msg_rm_ring_cfg_req { 842 struct ti_sci_msg_hdr hdr; 843 u32 valid_params; 844 u16 nav_id; 845 u16 index; 846 u32 addr_lo; 847 u32 addr_hi; 848 u32 count; 849 u8 mode; 850 u8 size; 851 u8 order_id; 852 u16 virtid; 853 u8 asel; 854 } __packed; 855 856 /** 857 * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination 858 * thread 859 * @hdr: Generic Header 860 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is 861 * used to pair the source and destination threads. 862 * @src_thread: PSI-L source thread ID within the PSI-L System thread map. 863 * 864 * UDMAP transmit channels mapped to source threads will have their 865 * TCHAN_THRD_ID register programmed with the destination thread if the pairing 866 * is successful. 867 * 868 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map. 869 * PSI-L destination threads start at index 0x8000. The request is NACK'd if 870 * the destination thread is not greater than or equal to 0x8000. 871 * 872 * UDMAP receive channels mapped to destination threads will have their 873 * RCHAN_THRD_ID register programmed with the source thread if the pairing 874 * is successful. 875 * 876 * Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK 877 * message. 878 */ 879 struct ti_sci_msg_psil_pair { 880 struct ti_sci_msg_hdr hdr; 881 u32 nav_id; 882 u32 src_thread; 883 u32 dst_thread; 884 } __packed; 885 886 /** 887 * struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a 888 * destination thread 889 * @hdr: Generic Header 890 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is 891 * used to unpair the source and destination threads. 892 * @src_thread: PSI-L source thread ID within the PSI-L System thread map. 893 * 894 * UDMAP transmit channels mapped to source threads will have their 895 * TCHAN_THRD_ID register cleared if the unpairing is successful. 896 * 897 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map. 898 * PSI-L destination threads start at index 0x8000. The request is NACK'd if 899 * the destination thread is not greater than or equal to 0x8000. 900 * 901 * UDMAP receive channels mapped to destination threads will have their 902 * RCHAN_THRD_ID register cleared if the unpairing is successful. 903 * 904 * Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK 905 * message. 906 */ 907 struct ti_sci_msg_psil_unpair { 908 struct ti_sci_msg_hdr hdr; 909 u32 nav_id; 910 u32 src_thread; 911 u32 dst_thread; 912 } __packed; 913 914 /** 915 * struct ti_sci_msg_udmap_rx_flow_cfg - UDMAP receive flow configuration 916 * message 917 * @hdr: Generic Header 918 * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is 919 * allocated 920 * @flow_index: UDMAP receive flow index for non-optional configuration. 921 * @rx_ch_index: Specifies the index of the receive channel using the flow_index 922 * @rx_einfo_present: UDMAP receive flow extended packet info present. 923 * @rx_psinfo_present: UDMAP receive flow PS words present. 924 * @rx_error_handling: UDMAP receive flow error handling configuration. Valid 925 * values are TI_SCI_RM_UDMAP_RX_FLOW_ERR_DROP/RETRY. 926 * @rx_desc_type: UDMAP receive flow descriptor type. It can be one of 927 * TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST/MONO. 928 * @rx_sop_offset: UDMAP receive flow start of packet offset. 929 * @rx_dest_qnum: UDMAP receive flow destination queue number. 930 * @rx_ps_location: UDMAP receive flow PS words location. 931 * 0 - end of packet descriptor 932 * 1 - Beginning of the data buffer 933 * @rx_src_tag_hi: UDMAP receive flow source tag high byte constant 934 * @rx_src_tag_lo: UDMAP receive flow source tag low byte constant 935 * @rx_dest_tag_hi: UDMAP receive flow destination tag high byte constant 936 * @rx_dest_tag_lo: UDMAP receive flow destination tag low byte constant 937 * @rx_src_tag_hi_sel: UDMAP receive flow source tag high byte selector 938 * @rx_src_tag_lo_sel: UDMAP receive flow source tag low byte selector 939 * @rx_dest_tag_hi_sel: UDMAP receive flow destination tag high byte selector 940 * @rx_dest_tag_lo_sel: UDMAP receive flow destination tag low byte selector 941 * @rx_size_thresh_en: UDMAP receive flow packet size based free buffer queue 942 * enable. If enabled, the ti_sci_rm_udmap_rx_flow_opt_cfg also need to be 943 * configured and sent. 944 * @rx_fdq0_sz0_qnum: UDMAP receive flow free descriptor queue 0. 945 * @rx_fdq1_qnum: UDMAP receive flow free descriptor queue 1. 946 * @rx_fdq2_qnum: UDMAP receive flow free descriptor queue 2. 947 * @rx_fdq3_qnum: UDMAP receive flow free descriptor queue 3. 948 * 949 * For detailed information on the settings, see the UDMAP section of the TRM. 950 */ 951 struct ti_sci_msg_udmap_rx_flow_cfg { 952 struct ti_sci_msg_hdr hdr; 953 u32 nav_id; 954 u32 flow_index; 955 u32 rx_ch_index; 956 u8 rx_einfo_present; 957 u8 rx_psinfo_present; 958 u8 rx_error_handling; 959 u8 rx_desc_type; 960 u16 rx_sop_offset; 961 u16 rx_dest_qnum; 962 u8 rx_ps_location; 963 u8 rx_src_tag_hi; 964 u8 rx_src_tag_lo; 965 u8 rx_dest_tag_hi; 966 u8 rx_dest_tag_lo; 967 u8 rx_src_tag_hi_sel; 968 u8 rx_src_tag_lo_sel; 969 u8 rx_dest_tag_hi_sel; 970 u8 rx_dest_tag_lo_sel; 971 u8 rx_size_thresh_en; 972 u16 rx_fdq0_sz0_qnum; 973 u16 rx_fdq1_qnum; 974 u16 rx_fdq2_qnum; 975 u16 rx_fdq3_qnum; 976 } __packed; 977 978 /** 979 * struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg - parameters for UDMAP receive 980 * flow optional configuration 981 * @hdr: Generic Header 982 * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is 983 * allocated 984 * @flow_index: UDMAP receive flow index for optional configuration. 985 * @rx_ch_index: Specifies the index of the receive channel using the flow_index 986 * @rx_size_thresh0: UDMAP receive flow packet size threshold 0. 987 * @rx_size_thresh1: UDMAP receive flow packet size threshold 1. 988 * @rx_size_thresh2: UDMAP receive flow packet size threshold 2. 989 * @rx_fdq0_sz1_qnum: UDMAP receive flow free descriptor queue for size 990 * threshold 1. 991 * @rx_fdq0_sz2_qnum: UDMAP receive flow free descriptor queue for size 992 * threshold 2. 993 * @rx_fdq0_sz3_qnum: UDMAP receive flow free descriptor queue for size 994 * threshold 3. 995 * 996 * For detailed information on the settings, see the UDMAP section of the TRM. 997 */ 998 struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg { 999 struct ti_sci_msg_hdr hdr; 1000 u32 nav_id; 1001 u32 flow_index; 1002 u32 rx_ch_index; 1003 u16 rx_size_thresh0; 1004 u16 rx_size_thresh1; 1005 u16 rx_size_thresh2; 1006 u16 rx_fdq0_sz1_qnum; 1007 u16 rx_fdq0_sz2_qnum; 1008 u16 rx_fdq0_sz3_qnum; 1009 } __packed; 1010 1011 /** 1012 * struct ti_sci_msg_rm_udmap_tx_ch_cfg_req - Configures a 1013 * Navigator Subsystem UDMAP transmit channel 1014 * 1015 * Configures the non-real-time registers of a Navigator Subsystem UDMAP 1016 * transmit channel. The channel index must be assigned to the host defined 1017 * in the TISCI header via the RM board configuration resource assignment 1018 * range list. 1019 * 1020 * @hdr: Generic Header 1021 * 1022 * @valid_params: Bitfield defining validity of tx channel configuration 1023 * parameters. The tx channel configuration fields are not valid, and will not 1024 * be used for ch configuration, if their corresponding valid bit is zero. 1025 * Valid bit usage: 1026 * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err 1027 * 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype 1028 * 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type 1029 * 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size 1030 * 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum 1031 * 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority 1032 * 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos 1033 * 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid 1034 * 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority 1035 * 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo 1036 * 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords 1037 * 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt 1038 * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count 1039 * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth 1040 * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size 1041 * 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype 1042 * 16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type 1043 * 1044 * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located 1045 * 1046 * @index: UDMAP transmit channel index. 1047 * 1048 * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to 1049 * be programmed into the tx_pause_on_err field of the channel's TCHAN_TCFG 1050 * register. 1051 * 1052 * @tx_filt_einfo: UDMAP transmit channel extended packet information passing 1053 * configuration to be programmed into the tx_filt_einfo field of the 1054 * channel's TCHAN_TCFG register. 1055 * 1056 * @tx_filt_pswords: UDMAP transmit channel protocol specific word passing 1057 * configuration to be programmed into the tx_filt_pswords field of the 1058 * channel's TCHAN_TCFG register. 1059 * 1060 * @tx_atype: UDMAP transmit channel non Ring Accelerator access pointer 1061 * interpretation configuration to be programmed into the tx_atype field of 1062 * the channel's TCHAN_TCFG register. 1063 * 1064 * @tx_chan_type: UDMAP transmit channel functional channel type and work 1065 * passing mechanism configuration to be programmed into the tx_chan_type 1066 * field of the channel's TCHAN_TCFG register. 1067 * 1068 * @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression 1069 * configuration to be programmed into the tx_supr_tdpkt field of the channel's 1070 * TCHAN_TCFG register. 1071 * 1072 * @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to 1073 * fetch configuration to be programmed into the tx_fetch_size field of the 1074 * channel's TCHAN_TCFG register. The user must make sure to set the maximum 1075 * word count that can pass through the channel for any allowed descriptor type. 1076 * 1077 * @tx_credit_count: UDMAP transmit channel transfer request credit count 1078 * configuration to be programmed into the count field of the TCHAN_TCREDIT 1079 * register. Specifies how many credits for complete TRs are available. 1080 * 1081 * @txcq_qnum: UDMAP transmit channel completion queue configuration to be 1082 * programmed into the txcq_qnum field of the TCHAN_TCQ register. The specified 1083 * completion queue must be assigned to the host, or a subordinate of the host, 1084 * requesting configuration of the transmit channel. 1085 * 1086 * @tx_priority: UDMAP transmit channel transmit priority value to be programmed 1087 * into the priority field of the channel's TCHAN_TPRI_CTRL register. 1088 * 1089 * @tx_qos: UDMAP transmit channel transmit qos value to be programmed into the 1090 * qos field of the channel's TCHAN_TPRI_CTRL register. 1091 * 1092 * @tx_orderid: UDMAP transmit channel bus order id value to be programmed into 1093 * the orderid field of the channel's TCHAN_TPRI_CTRL register. 1094 * 1095 * @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed 1096 * into the fdepth field of the TCHAN_TFIFO_DEPTH register. Sets the number of 1097 * Tx FIFO bytes which are allowed to be stored for the channel. Check the UDMAP 1098 * section of the TRM for restrictions regarding this parameter. 1099 * 1100 * @tx_sched_priority: UDMAP transmit channel tx scheduling priority 1101 * configuration to be programmed into the priority field of the channel's 1102 * TCHAN_TST_SCHED register. 1103 * 1104 * @tx_burst_size: UDMAP transmit channel burst size configuration to be 1105 * programmed into the tx_burst_size field of the TCHAN_TCFG register. 1106 * 1107 * @tx_tdtype: UDMAP transmit channel teardown type configuration to be 1108 * programmed into the tdtype field of the TCHAN_TCFG register: 1109 * 0 - Return immediately 1110 * 1 - Wait for completion message from remote peer 1111 * 1112 * @extended_ch_type: Valid for BCDMA. 1113 * 0 - the channel is split tx channel (tchan) 1114 * 1 - the channel is block copy channel (bchan) 1115 */ 1116 struct ti_sci_msg_rm_udmap_tx_ch_cfg_req { 1117 struct ti_sci_msg_hdr hdr; 1118 u32 valid_params; 1119 u16 nav_id; 1120 u16 index; 1121 u8 tx_pause_on_err; 1122 u8 tx_filt_einfo; 1123 u8 tx_filt_pswords; 1124 u8 tx_atype; 1125 u8 tx_chan_type; 1126 u8 tx_supr_tdpkt; 1127 u16 tx_fetch_size; 1128 u8 tx_credit_count; 1129 u16 txcq_qnum; 1130 u8 tx_priority; 1131 u8 tx_qos; 1132 u8 tx_orderid; 1133 u16 fdepth; 1134 u8 tx_sched_priority; 1135 u8 tx_burst_size; 1136 u8 tx_tdtype; 1137 u8 extended_ch_type; 1138 } __packed; 1139 1140 /** 1141 * struct ti_sci_msg_rm_udmap_rx_ch_cfg_req - Configures a 1142 * Navigator Subsystem UDMAP receive channel 1143 * 1144 * Configures the non-real-time registers of a Navigator Subsystem UDMAP 1145 * receive channel. The channel index must be assigned to the host defined 1146 * in the TISCI header via the RM board configuration resource assignment 1147 * range list. 1148 * 1149 * @hdr: Generic Header 1150 * 1151 * @valid_params: Bitfield defining validity of rx channel configuration 1152 * parameters. 1153 * The rx channel configuration fields are not valid, and will not be used for 1154 * ch configuration, if their corresponding valid bit is zero. 1155 * Valid bit usage: 1156 * 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err 1157 * 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype 1158 * 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type 1159 * 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size 1160 * 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum 1161 * 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority 1162 * 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos 1163 * 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid 1164 * 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority 1165 * 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start 1166 * 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt 1167 * 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short 1168 * 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long 1169 * 14 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size 1170 * 1171 * @nav_id: SoC device ID of Navigator Subsystem where rx channel is located 1172 * 1173 * @index: UDMAP receive channel index. 1174 * 1175 * @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to 1176 * fetch configuration to be programmed into the rx_fetch_size field of the 1177 * channel's RCHAN_RCFG register. 1178 * 1179 * @rxcq_qnum: UDMAP receive channel completion queue configuration to be 1180 * programmed into the rxcq_qnum field of the RCHAN_RCQ register. 1181 * The specified completion queue must be assigned to the host, or a subordinate 1182 * of the host, requesting configuration of the receive channel. 1183 * 1184 * @rx_priority: UDMAP receive channel receive priority value to be programmed 1185 * into the priority field of the channel's RCHAN_RPRI_CTRL register. 1186 * 1187 * @rx_qos: UDMAP receive channel receive qos value to be programmed into the 1188 * qos field of the channel's RCHAN_RPRI_CTRL register. 1189 * 1190 * @rx_orderid: UDMAP receive channel bus order id value to be programmed into 1191 * the orderid field of the channel's RCHAN_RPRI_CTRL register. 1192 * 1193 * @rx_sched_priority: UDMAP receive channel rx scheduling priority 1194 * configuration to be programmed into the priority field of the channel's 1195 * RCHAN_RST_SCHED register. 1196 * 1197 * @flowid_start: UDMAP receive channel additional flows starting index 1198 * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG 1199 * register. Specifies the starting index for flow IDs the receive channel is to 1200 * make use of beyond the default flow. flowid_start and @ref flowid_cnt must be 1201 * set as valid and configured together. The starting flow ID set by 1202 * @ref flowid_cnt must be a flow index within the Navigator Subsystem's subset 1203 * of flows beyond the default flows statically mapped to receive channels. 1204 * The additional flows must be assigned to the host, or a subordinate of the 1205 * host, requesting configuration of the receive channel. 1206 * 1207 * @flowid_cnt: UDMAP receive channel additional flows count configuration to 1208 * program into the flowid_cnt field of the RCHAN_RFLOW_RNG register. 1209 * This field specifies how many flow IDs are in the additional contiguous range 1210 * of legal flow IDs for the channel. @ref flowid_start and flowid_cnt must be 1211 * set as valid and configured together. Disabling the valid_params field bit 1212 * for flowid_cnt indicates no flow IDs other than the default are to be 1213 * allocated and used by the receive channel. @ref flowid_start plus flowid_cnt 1214 * cannot be greater than the number of receive flows in the receive channel's 1215 * Navigator Subsystem. The additional flows must be assigned to the host, or a 1216 * subordinate of the host, requesting configuration of the receive channel. 1217 * 1218 * @rx_pause_on_err: UDMAP receive channel pause on error configuration to be 1219 * programmed into the rx_pause_on_err field of the channel's RCHAN_RCFG 1220 * register. 1221 * 1222 * @rx_atype: UDMAP receive channel non Ring Accelerator access pointer 1223 * interpretation configuration to be programmed into the rx_atype field of the 1224 * channel's RCHAN_RCFG register. 1225 * 1226 * @rx_chan_type: UDMAP receive channel functional channel type and work passing 1227 * mechanism configuration to be programmed into the rx_chan_type field of the 1228 * channel's RCHAN_RCFG register. 1229 * 1230 * @rx_ignore_short: UDMAP receive channel short packet treatment configuration 1231 * to be programmed into the rx_ignore_short field of the RCHAN_RCFG register. 1232 * 1233 * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to 1234 * be programmed into the rx_ignore_long field of the RCHAN_RCFG register. 1235 * 1236 * @rx_burst_size: UDMAP receive channel burst size configuration to be 1237 * programmed into the rx_burst_size field of the RCHAN_RCFG register. 1238 */ 1239 struct ti_sci_msg_rm_udmap_rx_ch_cfg_req { 1240 struct ti_sci_msg_hdr hdr; 1241 u32 valid_params; 1242 u16 nav_id; 1243 u16 index; 1244 u16 rx_fetch_size; 1245 u16 rxcq_qnum; 1246 u8 rx_priority; 1247 u8 rx_qos; 1248 u8 rx_orderid; 1249 u8 rx_sched_priority; 1250 u16 flowid_start; 1251 u16 flowid_cnt; 1252 u8 rx_pause_on_err; 1253 u8 rx_atype; 1254 u8 rx_chan_type; 1255 u8 rx_ignore_short; 1256 u8 rx_ignore_long; 1257 u8 rx_burst_size; 1258 } __packed; 1259 1260 /** 1261 * struct ti_sci_msg_rm_udmap_flow_cfg_req - Configures a 1262 * Navigator Subsystem UDMAP receive flow 1263 * 1264 * Configures a Navigator Subsystem UDMAP receive flow's registers. 1265 * Configuration does not include the flow registers which handle size-based 1266 * free descriptor queue routing. 1267 * 1268 * The flow index must be assigned to the host defined in the TISCI header via 1269 * the RM board configuration resource assignment range list. 1270 * 1271 * @hdr: Standard TISCI header 1272 * 1273 * @valid_params: 1274 * Bitfield defining validity of rx flow configuration parameters. The 1275 * rx flow configuration fields are not valid, and will not be used for flow 1276 * configuration, if their corresponding valid bit is zero. Valid bit usage: 1277 * 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present 1278 * 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present 1279 * 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling 1280 * 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type 1281 * 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset 1282 * 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum 1283 * 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi 1284 * 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo 1285 * 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi 1286 * 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo 1287 * 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel 1288 * 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel 1289 * 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel 1290 * 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel 1291 * 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum 1292 * 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum 1293 * 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum 1294 * 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum 1295 * 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location 1296 * 1297 * @nav_id: SoC device ID of Navigator Subsystem from which the receive flow is 1298 * allocated 1299 * 1300 * @flow_index: UDMAP receive flow index for non-optional configuration. 1301 * 1302 * @rx_einfo_present: 1303 * UDMAP receive flow extended packet info present configuration to be 1304 * programmed into the rx_einfo_present field of the flow's RFLOW_RFA register. 1305 * 1306 * @rx_psinfo_present: 1307 * UDMAP receive flow PS words present configuration to be programmed into the 1308 * rx_psinfo_present field of the flow's RFLOW_RFA register. 1309 * 1310 * @rx_error_handling: 1311 * UDMAP receive flow error handling configuration to be programmed into the 1312 * rx_error_handling field of the flow's RFLOW_RFA register. 1313 * 1314 * @rx_desc_type: 1315 * UDMAP receive flow descriptor type configuration to be programmed into the 1316 * rx_desc_type field field of the flow's RFLOW_RFA register. 1317 * 1318 * @rx_sop_offset: 1319 * UDMAP receive flow start of packet offset configuration to be programmed 1320 * into the rx_sop_offset field of the RFLOW_RFA register. See the UDMAP 1321 * section of the TRM for more information on this setting. Valid values for 1322 * this field are 0-255 bytes. 1323 * 1324 * @rx_dest_qnum: 1325 * UDMAP receive flow destination queue configuration to be programmed into the 1326 * rx_dest_qnum field of the flow's RFLOW_RFA register. The specified 1327 * destination queue must be valid within the Navigator Subsystem and must be 1328 * owned by the host, or a subordinate of the host, requesting allocation and 1329 * configuration of the receive flow. 1330 * 1331 * @rx_src_tag_hi: 1332 * UDMAP receive flow source tag high byte constant configuration to be 1333 * programmed into the rx_src_tag_hi field of the flow's RFLOW_RFB register. 1334 * See the UDMAP section of the TRM for more information on this setting. 1335 * 1336 * @rx_src_tag_lo: 1337 * UDMAP receive flow source tag low byte constant configuration to be 1338 * programmed into the rx_src_tag_lo field of the flow's RFLOW_RFB register. 1339 * See the UDMAP section of the TRM for more information on this setting. 1340 * 1341 * @rx_dest_tag_hi: 1342 * UDMAP receive flow destination tag high byte constant configuration to be 1343 * programmed into the rx_dest_tag_hi field of the flow's RFLOW_RFB register. 1344 * See the UDMAP section of the TRM for more information on this setting. 1345 * 1346 * @rx_dest_tag_lo: 1347 * UDMAP receive flow destination tag low byte constant configuration to be 1348 * programmed into the rx_dest_tag_lo field of the flow's RFLOW_RFB register. 1349 * See the UDMAP section of the TRM for more information on this setting. 1350 * 1351 * @rx_src_tag_hi_sel: 1352 * UDMAP receive flow source tag high byte selector configuration to be 1353 * programmed into the rx_src_tag_hi_sel field of the RFLOW_RFC register. See 1354 * the UDMAP section of the TRM for more information on this setting. 1355 * 1356 * @rx_src_tag_lo_sel: 1357 * UDMAP receive flow source tag low byte selector configuration to be 1358 * programmed into the rx_src_tag_lo_sel field of the RFLOW_RFC register. See 1359 * the UDMAP section of the TRM for more information on this setting. 1360 * 1361 * @rx_dest_tag_hi_sel: 1362 * UDMAP receive flow destination tag high byte selector configuration to be 1363 * programmed into the rx_dest_tag_hi_sel field of the RFLOW_RFC register. See 1364 * the UDMAP section of the TRM for more information on this setting. 1365 * 1366 * @rx_dest_tag_lo_sel: 1367 * UDMAP receive flow destination tag low byte selector configuration to be 1368 * programmed into the rx_dest_tag_lo_sel field of the RFLOW_RFC register. See 1369 * the UDMAP section of the TRM for more information on this setting. 1370 * 1371 * @rx_fdq0_sz0_qnum: 1372 * UDMAP receive flow free descriptor queue 0 configuration to be programmed 1373 * into the rx_fdq0_sz0_qnum field of the flow's RFLOW_RFD register. See the 1374 * UDMAP section of the TRM for more information on this setting. The specified 1375 * free queue must be valid within the Navigator Subsystem and must be owned 1376 * by the host, or a subordinate of the host, requesting allocation and 1377 * configuration of the receive flow. 1378 * 1379 * @rx_fdq1_qnum: 1380 * UDMAP receive flow free descriptor queue 1 configuration to be programmed 1381 * into the rx_fdq1_qnum field of the flow's RFLOW_RFD register. See the 1382 * UDMAP section of the TRM for more information on this setting. The specified 1383 * free queue must be valid within the Navigator Subsystem and must be owned 1384 * by the host, or a subordinate of the host, requesting allocation and 1385 * configuration of the receive flow. 1386 * 1387 * @rx_fdq2_qnum: 1388 * UDMAP receive flow free descriptor queue 2 configuration to be programmed 1389 * into the rx_fdq2_qnum field of the flow's RFLOW_RFE register. See the 1390 * UDMAP section of the TRM for more information on this setting. The specified 1391 * free queue must be valid within the Navigator Subsystem and must be owned 1392 * by the host, or a subordinate of the host, requesting allocation and 1393 * configuration of the receive flow. 1394 * 1395 * @rx_fdq3_qnum: 1396 * UDMAP receive flow free descriptor queue 3 configuration to be programmed 1397 * into the rx_fdq3_qnum field of the flow's RFLOW_RFE register. See the 1398 * UDMAP section of the TRM for more information on this setting. The specified 1399 * free queue must be valid within the Navigator Subsystem and must be owned 1400 * by the host, or a subordinate of the host, requesting allocation and 1401 * configuration of the receive flow. 1402 * 1403 * @rx_ps_location: 1404 * UDMAP receive flow PS words location configuration to be programmed into the 1405 * rx_ps_location field of the flow's RFLOW_RFA register. 1406 */ 1407 struct ti_sci_msg_rm_udmap_flow_cfg_req { 1408 struct ti_sci_msg_hdr hdr; 1409 u32 valid_params; 1410 u16 nav_id; 1411 u16 flow_index; 1412 u8 rx_einfo_present; 1413 u8 rx_psinfo_present; 1414 u8 rx_error_handling; 1415 u8 rx_desc_type; 1416 u16 rx_sop_offset; 1417 u16 rx_dest_qnum; 1418 u8 rx_src_tag_hi; 1419 u8 rx_src_tag_lo; 1420 u8 rx_dest_tag_hi; 1421 u8 rx_dest_tag_lo; 1422 u8 rx_src_tag_hi_sel; 1423 u8 rx_src_tag_lo_sel; 1424 u8 rx_dest_tag_hi_sel; 1425 u8 rx_dest_tag_lo_sel; 1426 u16 rx_fdq0_sz0_qnum; 1427 u16 rx_fdq1_qnum; 1428 u16 rx_fdq2_qnum; 1429 u16 rx_fdq3_qnum; 1430 u8 rx_ps_location; 1431 } __packed; 1432 1433 /** 1434 * struct ti_sci_msg_req_proc_request - Request a processor 1435 * @hdr: Generic Header 1436 * @processor_id: ID of processor being requested 1437 * 1438 * Request type is TI_SCI_MSG_PROC_REQUEST, response is a generic ACK/NACK 1439 * message. 1440 */ 1441 struct ti_sci_msg_req_proc_request { 1442 struct ti_sci_msg_hdr hdr; 1443 u8 processor_id; 1444 } __packed; 1445 1446 /** 1447 * struct ti_sci_msg_req_proc_release - Release a processor 1448 * @hdr: Generic Header 1449 * @processor_id: ID of processor being released 1450 * 1451 * Request type is TI_SCI_MSG_PROC_RELEASE, response is a generic ACK/NACK 1452 * message. 1453 */ 1454 struct ti_sci_msg_req_proc_release { 1455 struct ti_sci_msg_hdr hdr; 1456 u8 processor_id; 1457 } __packed; 1458 1459 /** 1460 * struct ti_sci_msg_req_proc_handover - Handover a processor to a host 1461 * @hdr: Generic Header 1462 * @processor_id: ID of processor being handed over 1463 * @host_id: Host ID the control needs to be transferred to 1464 * 1465 * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK 1466 * message. 1467 */ 1468 struct ti_sci_msg_req_proc_handover { 1469 struct ti_sci_msg_hdr hdr; 1470 u8 processor_id; 1471 u8 host_id; 1472 } __packed; 1473 1474 /* Boot Vector masks */ 1475 #define TI_SCI_ADDR_LOW_MASK GENMASK_ULL(31, 0) 1476 #define TI_SCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32) 1477 #define TI_SCI_ADDR_HIGH_SHIFT 32 1478 1479 /** 1480 * struct ti_sci_msg_req_set_config - Set Processor boot configuration 1481 * @hdr: Generic Header 1482 * @processor_id: ID of processor being configured 1483 * @bootvector_low: Lower 32 bit address (Little Endian) of boot vector 1484 * @bootvector_high: Higher 32 bit address (Little Endian) of boot vector 1485 * @config_flags_set: Optional Processor specific Config Flags to set. 1486 * Setting a bit here implies the corresponding mode 1487 * will be set 1488 * @config_flags_clear: Optional Processor specific Config Flags to clear. 1489 * Setting a bit here implies the corresponding mode 1490 * will be cleared 1491 * 1492 * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK 1493 * message. 1494 */ 1495 struct ti_sci_msg_req_set_config { 1496 struct ti_sci_msg_hdr hdr; 1497 u8 processor_id; 1498 u32 bootvector_low; 1499 u32 bootvector_high; 1500 u32 config_flags_set; 1501 u32 config_flags_clear; 1502 } __packed; 1503 1504 /** 1505 * struct ti_sci_msg_req_set_ctrl - Set Processor boot control flags 1506 * @hdr: Generic Header 1507 * @processor_id: ID of processor being configured 1508 * @control_flags_set: Optional Processor specific Control Flags to set. 1509 * Setting a bit here implies the corresponding mode 1510 * will be set 1511 * @control_flags_clear:Optional Processor specific Control Flags to clear. 1512 * Setting a bit here implies the corresponding mode 1513 * will be cleared 1514 * 1515 * Request type is TI_SCI_MSG_SET_CTRL, response is a generic ACK/NACK 1516 * message. 1517 */ 1518 struct ti_sci_msg_req_set_ctrl { 1519 struct ti_sci_msg_hdr hdr; 1520 u8 processor_id; 1521 u32 control_flags_set; 1522 u32 control_flags_clear; 1523 } __packed; 1524 1525 /** 1526 * struct ti_sci_msg_req_get_status - Processor boot status request 1527 * @hdr: Generic Header 1528 * @processor_id: ID of processor whose status is being requested 1529 * 1530 * Request type is TI_SCI_MSG_GET_STATUS, response is an appropriate 1531 * message, or NACK in case of inability to satisfy request. 1532 */ 1533 struct ti_sci_msg_req_get_status { 1534 struct ti_sci_msg_hdr hdr; 1535 u8 processor_id; 1536 } __packed; 1537 1538 /** 1539 * struct ti_sci_msg_resp_get_status - Processor boot status response 1540 * @hdr: Generic Header 1541 * @processor_id: ID of processor whose status is returned 1542 * @bootvector_low: Lower 32 bit address (Little Endian) of boot vector 1543 * @bootvector_high: Higher 32 bit address (Little Endian) of boot vector 1544 * @config_flags: Optional Processor specific Config Flags set currently 1545 * @control_flags: Optional Processor specific Control Flags set currently 1546 * @status_flags: Optional Processor specific Status Flags set currently 1547 * 1548 * Response structure to a TI_SCI_MSG_GET_STATUS request. 1549 */ 1550 struct ti_sci_msg_resp_get_status { 1551 struct ti_sci_msg_hdr hdr; 1552 u8 processor_id; 1553 u32 bootvector_low; 1554 u32 bootvector_high; 1555 u32 config_flags; 1556 u32 control_flags; 1557 u32 status_flags; 1558 } __packed; 1559 1560 #endif /* __TI_SCI_H */ 1561