1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Texas Instruments System Control Interface (TISCI) Protocol 4 * 5 * Communication protocol with TI SCI hardware 6 * The system works in a message response protocol 7 * See: https://software-dl.ti.com/tisci/esd/latest/index.html for details 8 * 9 * Copyright (C) 2015-2024 Texas Instruments Incorporated - https://www.ti.com/ 10 */ 11 12 #ifndef __TI_SCI_H 13 #define __TI_SCI_H 14 15 /* Generic Messages */ 16 #define TI_SCI_MSG_ENABLE_WDT 0x0000 17 #define TI_SCI_MSG_WAKE_RESET 0x0001 18 #define TI_SCI_MSG_VERSION 0x0002 19 #define TI_SCI_MSG_WAKE_REASON 0x0003 20 #define TI_SCI_MSG_GOODBYE 0x0004 21 #define TI_SCI_MSG_SYS_RESET 0x0005 22 #define TI_SCI_MSG_QUERY_FW_CAPS 0x0022 23 24 /* Device requests */ 25 #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200 26 #define TI_SCI_MSG_GET_DEVICE_STATE 0x0201 27 #define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202 28 29 /* Clock requests */ 30 #define TI_SCI_MSG_SET_CLOCK_STATE 0x0100 31 #define TI_SCI_MSG_GET_CLOCK_STATE 0x0101 32 #define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102 33 #define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103 34 #define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104 35 #define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c 36 #define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d 37 #define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e 38 39 /* Low Power Mode Requests */ 40 #define TI_SCI_MSG_PREPARE_SLEEP 0x0300 41 #define TI_SCI_MSG_LPM_WAKE_REASON 0x0306 42 #define TI_SCI_MSG_SET_IO_ISOLATION 0x0307 43 #define TI_SCI_MSG_LPM_SET_DEVICE_CONSTRAINT 0x0309 44 #define TI_SCI_MSG_LPM_SET_LATENCY_CONSTRAINT 0x030A 45 46 /* Resource Management Requests */ 47 #define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500 48 49 /* IRQ requests */ 50 #define TI_SCI_MSG_SET_IRQ 0x1000 51 #define TI_SCI_MSG_FREE_IRQ 0x1001 52 53 /* NAVSS resource management */ 54 /* Ringacc requests */ 55 #define TI_SCI_MSG_RM_RING_ALLOCATE 0x1100 56 #define TI_SCI_MSG_RM_RING_FREE 0x1101 57 #define TI_SCI_MSG_RM_RING_RECONFIG 0x1102 58 #define TI_SCI_MSG_RM_RING_RESET 0x1103 59 #define TI_SCI_MSG_RM_RING_CFG 0x1110 60 61 /* PSI-L requests */ 62 #define TI_SCI_MSG_RM_PSIL_PAIR 0x1280 63 #define TI_SCI_MSG_RM_PSIL_UNPAIR 0x1281 64 65 #define TI_SCI_MSG_RM_UDMAP_TX_ALLOC 0x1200 66 #define TI_SCI_MSG_RM_UDMAP_TX_FREE 0x1201 67 #define TI_SCI_MSG_RM_UDMAP_RX_ALLOC 0x1210 68 #define TI_SCI_MSG_RM_UDMAP_RX_FREE 0x1211 69 #define TI_SCI_MSG_RM_UDMAP_FLOW_CFG 0x1220 70 #define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG 0x1221 71 72 #define TISCI_MSG_RM_UDMAP_TX_CH_CFG 0x1205 73 #define TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG 0x1206 74 #define TISCI_MSG_RM_UDMAP_RX_CH_CFG 0x1215 75 #define TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG 0x1216 76 #define TISCI_MSG_RM_UDMAP_FLOW_CFG 0x1230 77 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG 0x1231 78 #define TISCI_MSG_RM_UDMAP_FLOW_GET_CFG 0x1232 79 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG 0x1233 80 81 /* Processor Control requests */ 82 #define TI_SCI_MSG_PROC_REQUEST 0xc000 83 #define TI_SCI_MSG_PROC_RELEASE 0xc001 84 #define TI_SCI_MSG_PROC_HANDOVER 0xc005 85 #define TI_SCI_MSG_SET_CONFIG 0xc100 86 #define TI_SCI_MSG_SET_CTRL 0xc101 87 #define TI_SCI_MSG_GET_STATUS 0xc400 88 89 /** 90 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses 91 * @type: Type of messages: One of TI_SCI_MSG* values 92 * @host: Host of the message 93 * @seq: Message identifier indicating a transfer sequence 94 * @flags: Flag for the message 95 */ 96 struct ti_sci_msg_hdr { 97 u16 type; 98 u8 host; 99 u8 seq; 100 #define TI_SCI_MSG_FLAG(val) (1 << (val)) 101 #define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0 102 #define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0) 103 #define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1) 104 #define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0 105 #define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1) 106 /* Additional Flags */ 107 u32 flags; 108 } __packed; 109 110 /** 111 * struct ti_sci_msg_resp_version - Response for a message 112 * @hdr: Generic header 113 * @firmware_description: String describing the firmware 114 * @firmware_revision: Firmware revision 115 * @abi_major: Major version of the ABI that firmware supports 116 * @abi_minor: Minor version of the ABI that firmware supports 117 * 118 * In general, ABI version changes follow the rule that minor version increments 119 * are backward compatible. Major revision changes in ABI may not be 120 * backward compatible. 121 * 122 * Response to a generic message with message type TI_SCI_MSG_VERSION 123 */ 124 struct ti_sci_msg_resp_version { 125 struct ti_sci_msg_hdr hdr; 126 char firmware_description[32]; 127 u16 firmware_revision; 128 u8 abi_major; 129 u8 abi_minor; 130 } __packed; 131 132 /** 133 * struct ti_sci_msg_req_reboot - Reboot the SoC 134 * @hdr: Generic Header 135 * 136 * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic 137 * ACK/NACK message. 138 */ 139 struct ti_sci_msg_req_reboot { 140 struct ti_sci_msg_hdr hdr; 141 } __packed; 142 143 /** 144 * struct ti_sci_msg_resp_query_fw_caps - Response for query firmware caps 145 * @hdr: Generic header 146 * @fw_caps: Each bit in fw_caps indicating one FW/SOC capability 147 * MSG_FLAG_CAPS_GENERIC: Generic capability (LPM not supported) 148 * MSG_FLAG_CAPS_LPM_PARTIAL_IO: Partial IO in LPM 149 * MSG_FLAG_CAPS_LPM_DM_MANAGED: LPM can be managed by DM 150 * 151 * Response to a generic message with message type TI_SCI_MSG_QUERY_FW_CAPS 152 * providing currently available SOC/firmware capabilities. SoC that don't 153 * support low power modes return only MSG_FLAG_CAPS_GENERIC capability. 154 */ 155 struct ti_sci_msg_resp_query_fw_caps { 156 struct ti_sci_msg_hdr hdr; 157 #define MSG_FLAG_CAPS_GENERIC TI_SCI_MSG_FLAG(0) 158 #define MSG_FLAG_CAPS_LPM_PARTIAL_IO TI_SCI_MSG_FLAG(4) 159 #define MSG_FLAG_CAPS_LPM_DM_MANAGED TI_SCI_MSG_FLAG(5) 160 #define MSG_MASK_CAPS_LPM GENMASK_ULL(4, 1) 161 u64 fw_caps; 162 } __packed; 163 164 /** 165 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device 166 * @hdr: Generic header 167 * @id: Indicates which device to modify 168 * @reserved: Reserved space in message, must be 0 for backward compatibility 169 * @state: The desired state of the device. 170 * 171 * Certain flags can also be set to alter the device state: 172 * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source. 173 * The meaning of this flag will vary slightly from device to device and from 174 * SoC to SoC but it generally allows the device to wake the SoC out of deep 175 * suspend states. 176 * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device. 177 * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed 178 * with STATE_RETENTION or STATE_ON, it will claim the device exclusively. 179 * If another host already has this device set to STATE_RETENTION or STATE_ON, 180 * the message will fail. Once successful, other hosts attempting to set 181 * STATE_RETENTION or STATE_ON will fail. 182 * 183 * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic 184 * ACK/NACK message. 185 */ 186 struct ti_sci_msg_req_set_device_state { 187 /* Additional hdr->flags options */ 188 #define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8) 189 #define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9) 190 #define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10) 191 struct ti_sci_msg_hdr hdr; 192 u32 id; 193 u32 reserved; 194 195 #define MSG_DEVICE_SW_STATE_AUTO_OFF 0 196 #define MSG_DEVICE_SW_STATE_RETENTION 1 197 #define MSG_DEVICE_SW_STATE_ON 2 198 u8 state; 199 } __packed; 200 201 /** 202 * struct ti_sci_msg_req_get_device_state - Request to get device. 203 * @hdr: Generic header 204 * @id: Device Identifier 205 * 206 * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state 207 * information 208 */ 209 struct ti_sci_msg_req_get_device_state { 210 struct ti_sci_msg_hdr hdr; 211 u32 id; 212 } __packed; 213 214 /** 215 * struct ti_sci_msg_resp_get_device_state - Response to get device request. 216 * @hdr: Generic header 217 * @context_loss_count: Indicates how many times the device has lost context. A 218 * driver can use this monotonic counter to determine if the device has 219 * lost context since the last time this message was exchanged. 220 * @resets: Programmed state of the reset lines. 221 * @programmed_state: The state as programmed by set_device. 222 * - Uses the MSG_DEVICE_SW_* macros 223 * @current_state: The actual state of the hardware. 224 * 225 * Response to request TI_SCI_MSG_GET_DEVICE_STATE. 226 */ 227 struct ti_sci_msg_resp_get_device_state { 228 struct ti_sci_msg_hdr hdr; 229 u32 context_loss_count; 230 u32 resets; 231 u8 programmed_state; 232 #define MSG_DEVICE_HW_STATE_OFF 0 233 #define MSG_DEVICE_HW_STATE_ON 1 234 #define MSG_DEVICE_HW_STATE_TRANS 2 235 u8 current_state; 236 } __packed; 237 238 /** 239 * struct ti_sci_msg_req_set_device_resets - Set the desired resets 240 * configuration of the device 241 * @hdr: Generic header 242 * @id: Indicates which device to modify 243 * @resets: A bit field of resets for the device. The meaning, behavior, 244 * and usage of the reset flags are device specific. 0 for a bit 245 * indicates releasing the reset represented by that bit while 1 246 * indicates keeping it held. 247 * 248 * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic 249 * ACK/NACK message. 250 */ 251 struct ti_sci_msg_req_set_device_resets { 252 struct ti_sci_msg_hdr hdr; 253 u32 id; 254 u32 resets; 255 } __packed; 256 257 /** 258 * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state 259 * @hdr: Generic Header, Certain flags can be set specific to the clocks: 260 * MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified 261 * via spread spectrum clocking. 262 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's 263 * frequency to be changed while it is running so long as it 264 * is within the min/max limits. 265 * MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this 266 * is only applicable to clock inputs on the SoC pseudo-device. 267 * @dev_id: Device identifier this request is for 268 * @clk_id: Clock identifier for the device for this request. 269 * Each device has it's own set of clock inputs. This indexes 270 * which clock input to modify. Set to 255 if clock ID is 271 * greater than or equal to 255. 272 * @request_state: Request the state for the clock to be set to. 273 * MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock, 274 * it can be disabled, regardless of the state of the device 275 * MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to 276 * automatically manage the state of this clock. If the device 277 * is enabled, then the clock is enabled. If the device is set 278 * to off or retention, then the clock is internally set as not 279 * being required by the device.(default) 280 * MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled, 281 * regardless of the state of the device. 282 * @clk_id_32: Clock identifier for the device for this request. 283 * Only to be used if the clock ID is greater than or equal to 284 * 255. 285 * 286 * Normally, all required clocks are managed by TISCI entity, this is used 287 * only for specific control *IF* required. Auto managed state is 288 * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote 289 * will explicitly control. 290 * 291 * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic 292 * ACK or NACK message. 293 */ 294 struct ti_sci_msg_req_set_clock_state { 295 /* Additional hdr->flags options */ 296 #define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8) 297 #define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9) 298 #define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10) 299 struct ti_sci_msg_hdr hdr; 300 u32 dev_id; 301 u8 clk_id; 302 #define MSG_CLOCK_SW_STATE_UNREQ 0 303 #define MSG_CLOCK_SW_STATE_AUTO 1 304 #define MSG_CLOCK_SW_STATE_REQ 2 305 u8 request_state; 306 u32 clk_id_32; 307 } __packed; 308 309 /** 310 * struct ti_sci_msg_req_get_clock_state - Request for clock state 311 * @hdr: Generic Header 312 * @dev_id: Device identifier this request is for 313 * @clk_id: Clock identifier for the device for this request. 314 * Each device has it's own set of clock inputs. This indexes 315 * which clock input to get state of. Set to 255 if the clock 316 * ID is greater than or equal to 255. 317 * @clk_id_32: Clock identifier for the device for the request. 318 * Only to be used if the clock ID is greater than or equal to 319 * 255. 320 * 321 * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state 322 * of the clock 323 */ 324 struct ti_sci_msg_req_get_clock_state { 325 struct ti_sci_msg_hdr hdr; 326 u32 dev_id; 327 u8 clk_id; 328 u32 clk_id_32; 329 } __packed; 330 331 /** 332 * struct ti_sci_msg_resp_get_clock_state - Response to get clock state 333 * @hdr: Generic Header 334 * @programmed_state: Any programmed state of the clock. This is one of 335 * MSG_CLOCK_SW_STATE* values. 336 * @current_state: Current state of the clock. This is one of: 337 * MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready 338 * MSG_CLOCK_HW_STATE_READY: Clock is ready 339 * 340 * Response to TI_SCI_MSG_GET_CLOCK_STATE. 341 */ 342 struct ti_sci_msg_resp_get_clock_state { 343 struct ti_sci_msg_hdr hdr; 344 u8 programmed_state; 345 #define MSG_CLOCK_HW_STATE_NOT_READY 0 346 #define MSG_CLOCK_HW_STATE_READY 1 347 u8 current_state; 348 } __packed; 349 350 /** 351 * struct ti_sci_msg_req_set_clock_parent - Set the clock parent 352 * @hdr: Generic Header 353 * @dev_id: Device identifier this request is for 354 * @clk_id: Clock identifier for the device for this request. 355 * Each device has it's own set of clock inputs. This indexes 356 * which clock input to modify. Set to 255 if clock ID is 357 * greater than or equal to 255. 358 * @parent_id: The new clock parent is selectable by an index via this 359 * parameter. Set to 255 if clock ID is greater than or 360 * equal to 255. 361 * @clk_id_32: Clock identifier if @clk_id field is 255. 362 * @parent_id_32: Parent identifier if @parent_id is 255. 363 * 364 * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic 365 * ACK / NACK message. 366 */ 367 struct ti_sci_msg_req_set_clock_parent { 368 struct ti_sci_msg_hdr hdr; 369 u32 dev_id; 370 u8 clk_id; 371 u8 parent_id; 372 u32 clk_id_32; 373 u32 parent_id_32; 374 } __packed; 375 376 /** 377 * struct ti_sci_msg_req_get_clock_parent - Get the clock parent 378 * @hdr: Generic Header 379 * @dev_id: Device identifier this request is for 380 * @clk_id: Clock identifier for the device for this request. 381 * Each device has it's own set of clock inputs. This indexes 382 * which clock input to get the parent for. If this field 383 * contains 255, the actual clock identifier is stored in 384 * @clk_id_32. 385 * @clk_id_32: Clock identifier if the @clk_id field contains 255. 386 * 387 * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information 388 */ 389 struct ti_sci_msg_req_get_clock_parent { 390 struct ti_sci_msg_hdr hdr; 391 u32 dev_id; 392 u8 clk_id; 393 u32 clk_id_32; 394 } __packed; 395 396 /** 397 * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent 398 * @hdr: Generic Header 399 * @parent_id: The current clock parent. If set to 255, the current parent 400 * ID can be found from the @parent_id_32 field. 401 * @parent_id_32: Current clock parent if @parent_id field is set to 402 * 255. 403 * 404 * Response to TI_SCI_MSG_GET_CLOCK_PARENT. 405 */ 406 struct ti_sci_msg_resp_get_clock_parent { 407 struct ti_sci_msg_hdr hdr; 408 u8 parent_id; 409 u32 parent_id_32; 410 } __packed; 411 412 /** 413 * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents 414 * @hdr: Generic header 415 * @dev_id: Device identifier this request is for 416 * @clk_id: Clock identifier for the device for this request. Set to 417 * 255 if clock ID is greater than or equal to 255. 418 * @clk_id_32: Clock identifier if the @clk_id field contains 255. 419 * 420 * This request provides information about how many clock parent options 421 * are available for a given clock to a device. This is typically used 422 * for input clocks. 423 * 424 * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate 425 * message, or NACK in case of inability to satisfy request. 426 */ 427 struct ti_sci_msg_req_get_clock_num_parents { 428 struct ti_sci_msg_hdr hdr; 429 u32 dev_id; 430 u8 clk_id; 431 u32 clk_id_32; 432 } __packed; 433 434 /** 435 * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents 436 * @hdr: Generic header 437 * @num_parents: Number of clock parents. If set to 255, the actual 438 * number of parents is stored into @num_parents_32 439 * field instead. 440 * @num_parents_32: Number of clock parents if @num_parents field is 441 * set to 255. 442 * 443 * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 444 */ 445 struct ti_sci_msg_resp_get_clock_num_parents { 446 struct ti_sci_msg_hdr hdr; 447 u8 num_parents; 448 u32 num_parents_32; 449 } __packed; 450 451 /** 452 * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency 453 * @hdr: Generic Header 454 * @dev_id: Device identifier this request is for 455 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum 456 * allowable programmed frequency and does not account for clock 457 * tolerances and jitter. 458 * @target_freq_hz: The target clock frequency. A frequency will be found 459 * as close to this target frequency as possible. 460 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum 461 * allowable programmed frequency and does not account for clock 462 * tolerances and jitter. 463 * @clk_id: Clock identifier for the device for this request. Set to 464 * 255 if clock identifier is greater than or equal to 255. 465 * @clk_id_32: Clock identifier if @clk_id is set to 255. 466 * 467 * NOTE: Normally clock frequency management is automatically done by TISCI 468 * entity. In case of specific requests, TISCI evaluates capability to achieve 469 * requested frequency within provided range and responds with 470 * result message. 471 * 472 * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message, 473 * or NACK in case of inability to satisfy request. 474 */ 475 struct ti_sci_msg_req_query_clock_freq { 476 struct ti_sci_msg_hdr hdr; 477 u32 dev_id; 478 u64 min_freq_hz; 479 u64 target_freq_hz; 480 u64 max_freq_hz; 481 u8 clk_id; 482 u32 clk_id_32; 483 } __packed; 484 485 /** 486 * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query 487 * @hdr: Generic Header 488 * @freq_hz: Frequency that is the best match in Hz. 489 * 490 * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request 491 * cannot be satisfied, the message will be of type NACK. 492 */ 493 struct ti_sci_msg_resp_query_clock_freq { 494 struct ti_sci_msg_hdr hdr; 495 u64 freq_hz; 496 } __packed; 497 498 /** 499 * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency 500 * @hdr: Generic Header 501 * @dev_id: Device identifier this request is for 502 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum 503 * allowable programmed frequency and does not account for clock 504 * tolerances and jitter. 505 * @target_freq_hz: The target clock frequency. The clock will be programmed 506 * at a rate as close to this target frequency as possible. 507 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum 508 * allowable programmed frequency and does not account for clock 509 * tolerances and jitter. 510 * @clk_id: Clock identifier for the device for this request. Set to 511 * 255 if clock ID is greater than or equal to 255. 512 * @clk_id_32: Clock identifier if @clk_id field is set to 255. 513 * 514 * NOTE: Normally clock frequency management is automatically done by TISCI 515 * entity. In case of specific requests, TISCI evaluates capability to achieve 516 * requested range and responds with success/failure message. 517 * 518 * This sets the desired frequency for a clock within an allowable 519 * range. This message will fail on an enabled clock unless 520 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally, 521 * if other clocks have their frequency modified due to this message, 522 * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled. 523 * 524 * Calling set frequency on a clock input to the SoC pseudo-device will 525 * inform the PMMC of that clock's frequency. Setting a frequency of 526 * zero will indicate the clock is disabled. 527 * 528 * Calling set frequency on clock outputs from the SoC pseudo-device will 529 * function similarly to setting the clock frequency on a device. 530 * 531 * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK 532 * message. 533 */ 534 struct ti_sci_msg_req_set_clock_freq { 535 struct ti_sci_msg_hdr hdr; 536 u32 dev_id; 537 u64 min_freq_hz; 538 u64 target_freq_hz; 539 u64 max_freq_hz; 540 u8 clk_id; 541 u32 clk_id_32; 542 } __packed; 543 544 /** 545 * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency 546 * @hdr: Generic Header 547 * @dev_id: Device identifier this request is for 548 * @clk_id: Clock identifier for the device for this request. Set to 549 * 255 if clock ID is greater than or equal to 255. 550 * @clk_id_32: Clock identifier if @clk_id field is set to 255. 551 * 552 * NOTE: Normally clock frequency management is automatically done by TISCI 553 * entity. In some cases, clock frequencies are configured by host. 554 * 555 * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency 556 * that the clock is currently at. 557 */ 558 struct ti_sci_msg_req_get_clock_freq { 559 struct ti_sci_msg_hdr hdr; 560 u32 dev_id; 561 u8 clk_id; 562 u32 clk_id_32; 563 } __packed; 564 565 /** 566 * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request 567 * @hdr: Generic Header 568 * @freq_hz: Frequency that the clock is currently on, in Hz. 569 * 570 * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ. 571 */ 572 struct ti_sci_msg_resp_get_clock_freq { 573 struct ti_sci_msg_hdr hdr; 574 u64 freq_hz; 575 } __packed; 576 577 /** 578 * struct tisci_msg_req_prepare_sleep - Request for TISCI_MSG_PREPARE_SLEEP. 579 * 580 * @hdr TISCI header to provide ACK/NAK flags to the host. 581 * @mode Low power mode to enter. 582 * @ctx_lo Low 32-bits of physical pointer to address to use for context save. 583 * @ctx_hi High 32-bits of physical pointer to address to use for context save. 584 * @debug_flags Flags that can be set to halt the sequence during suspend or 585 * resume to allow JTAG connection and debug. 586 * 587 * This message is used as the first step of entering a low power mode. It 588 * allows configurable information, including which state to enter to be 589 * easily shared from the application, as this is a non-secure message and 590 * therefore can be sent by anyone. 591 */ 592 struct ti_sci_msg_req_prepare_sleep { 593 struct ti_sci_msg_hdr hdr; 594 595 #define TISCI_MSG_VALUE_SLEEP_MODE_DM_MANAGED 0xfd 596 u8 mode; 597 u32 ctx_lo; 598 u32 ctx_hi; 599 u32 debug_flags; 600 } __packed; 601 602 /** 603 * struct tisci_msg_set_io_isolation_req - Request for TI_SCI_MSG_SET_IO_ISOLATION. 604 * 605 * @hdr: Generic header 606 * @state: The deseared state of the IO isolation. 607 * 608 * This message is used to enable/disable IO isolation for low power modes. 609 * Response is generic ACK / NACK message. 610 */ 611 struct ti_sci_msg_req_set_io_isolation { 612 struct ti_sci_msg_hdr hdr; 613 u8 state; 614 } __packed; 615 616 /** 617 * struct ti_sci_msg_resp_lpm_wake_reason - Response for TI_SCI_MSG_LPM_WAKE_REASON. 618 * 619 * @hdr: Generic header. 620 * @wake_source: The wake up source that woke soc from LPM. 621 * @wake_timestamp: Timestamp at which soc woke. 622 * @wake_pin: The pin that has triggered wake up. 623 * @mode: The last entered low power mode. 624 * @rsvd: Reserved for future use. 625 * 626 * Response to a generic message with message type TI_SCI_MSG_LPM_WAKE_REASON, 627 * used to query the wake up source, pin and entered low power mode. 628 */ 629 struct ti_sci_msg_resp_lpm_wake_reason { 630 struct ti_sci_msg_hdr hdr; 631 u32 wake_source; 632 u64 wake_timestamp; 633 u8 wake_pin; 634 u8 mode; 635 u32 rsvd[2]; 636 } __packed; 637 638 /** 639 * struct ti_sci_msg_req_lpm_set_device_constraint - Request for 640 * TISCI_MSG_LPM_SET_DEVICE_CONSTRAINT. 641 * 642 * @hdr: TISCI header to provide ACK/NAK flags to the host. 643 * @id: Device ID of device whose constraint has to be modified. 644 * @state: The desired state of device constraint: set or clear. 645 * @rsvd: Reserved for future use. 646 * 647 * This message is used by host to set constraint on the device. This can be 648 * sent anytime after boot before prepare sleep message. Any device can set a 649 * constraint on the low power mode that the SoC can enter. It allows 650 * configurable information to be easily shared from the application, as this 651 * is a non-secure message and therefore can be sent by anyone. By setting a 652 * constraint, the device ensures that it will not be powered off or reset in 653 * the selected mode. Note: Access Restriction: Exclusivity flag of Device will 654 * be honored. If some other host already has constraint on this device ID, 655 * NACK will be returned. 656 */ 657 struct ti_sci_msg_req_lpm_set_device_constraint { 658 struct ti_sci_msg_hdr hdr; 659 u32 id; 660 u8 state; 661 u32 rsvd[2]; 662 } __packed; 663 664 /** 665 * struct ti_sci_msg_req_lpm_set_latency_constraint - Request for 666 * TISCI_MSG_LPM_SET_LATENCY_CONSTRAINT. 667 * 668 * @hdr: TISCI header to provide ACK/NAK flags to the host. 669 * @wkup_latency: The maximum acceptable latency to wake up from low power mode 670 * in milliseconds. The deeper the state, the higher the latency. 671 * @state: The desired state of wakeup latency constraint: set or clear. 672 * @rsvd: Reserved for future use. 673 * 674 * This message is used by host to set wakeup latency from low power mode. This can 675 * be sent anytime after boot before prepare sleep message, and can be sent after 676 * current low power mode is exited. Any device can set a constraint on the low power 677 * mode that the SoC can enter. It allows configurable information to be easily shared 678 * from the application, as this is a non-secure message and therefore can be sent by 679 * anyone. By setting a wakeup latency constraint, the host ensures that the resume time 680 * from selected low power mode will be less than the constraint value. 681 */ 682 struct ti_sci_msg_req_lpm_set_latency_constraint { 683 struct ti_sci_msg_hdr hdr; 684 u16 latency; 685 u8 state; 686 u32 rsvd; 687 } __packed; 688 689 #define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff 690 691 /** 692 * struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned 693 * range of resources. 694 * @hdr: Generic Header 695 * @type: Unique resource assignment type 696 * @subtype: Resource assignment subtype within the resource type. 697 * @secondary_host: Host processing entity to which the resources are 698 * allocated. This is required only when the destination 699 * host id id different from ti sci interface host id, 700 * else TI_SCI_IRQ_SECONDARY_HOST_INVALID can be passed. 701 * 702 * Request type is TI_SCI_MSG_GET_RESOURCE_RANGE. Responded with requested 703 * resource range which is of type TI_SCI_MSG_GET_RESOURCE_RANGE. 704 */ 705 struct ti_sci_msg_req_get_resource_range { 706 struct ti_sci_msg_hdr hdr; 707 #define MSG_RM_RESOURCE_TYPE_MASK GENMASK(9, 0) 708 #define MSG_RM_RESOURCE_SUBTYPE_MASK GENMASK(5, 0) 709 u16 type; 710 u8 subtype; 711 u8 secondary_host; 712 } __packed; 713 714 /** 715 * struct ti_sci_msg_resp_get_resource_range - Response to resource get range. 716 * @hdr: Generic Header 717 * @range_start: Start index of the first resource range. 718 * @range_num: Number of resources in the first range. 719 * @range_start_sec: Start index of the second resource range. 720 * @range_num_sec: Number of resources in the second range. 721 * 722 * Response to request TI_SCI_MSG_GET_RESOURCE_RANGE. 723 */ 724 struct ti_sci_msg_resp_get_resource_range { 725 struct ti_sci_msg_hdr hdr; 726 u16 range_start; 727 u16 range_num; 728 u16 range_start_sec; 729 u16 range_num_sec; 730 } __packed; 731 732 /** 733 * struct ti_sci_msg_req_manage_irq - Request to configure/release the route 734 * between the dev and the host. 735 * @hdr: Generic Header 736 * @valid_params: Bit fields defining the validity of interrupt source 737 * parameters. If a bit is not set, then corresponding 738 * field is not valid and will not be used for route set. 739 * Bit field definitions: 740 * 0 - Valid bit for @dst_id 741 * 1 - Valid bit for @dst_host_irq 742 * 2 - Valid bit for @ia_id 743 * 3 - Valid bit for @vint 744 * 4 - Valid bit for @global_event 745 * 5 - Valid bit for @vint_status_bit_index 746 * 31 - Valid bit for @secondary_host 747 * @src_id: IRQ source peripheral ID. 748 * @src_index: IRQ source index within the peripheral 749 * @dst_id: IRQ Destination ID. Based on the architecture it can be 750 * IRQ controller or host processor ID. 751 * @dst_host_irq: IRQ number of the destination host IRQ controller 752 * @ia_id: Device ID of the interrupt aggregator in which the 753 * vint resides. 754 * @vint: Virtual interrupt number if the interrupt route 755 * is through an interrupt aggregator. 756 * @global_event: Global event that is to be mapped to interrupt 757 * aggregator virtual interrupt status bit. 758 * @vint_status_bit: Virtual interrupt status bit if the interrupt route 759 * utilizes an interrupt aggregator status bit. 760 * @secondary_host: Host ID of the IRQ destination computing entity. This is 761 * required only when destination host id is different 762 * from ti sci interface host id. 763 * 764 * Request type is TI_SCI_MSG_SET/RELEASE_IRQ. 765 * Response is generic ACK / NACK message. 766 */ 767 struct ti_sci_msg_req_manage_irq { 768 struct ti_sci_msg_hdr hdr; 769 #define MSG_FLAG_DST_ID_VALID TI_SCI_MSG_FLAG(0) 770 #define MSG_FLAG_DST_HOST_IRQ_VALID TI_SCI_MSG_FLAG(1) 771 #define MSG_FLAG_IA_ID_VALID TI_SCI_MSG_FLAG(2) 772 #define MSG_FLAG_VINT_VALID TI_SCI_MSG_FLAG(3) 773 #define MSG_FLAG_GLB_EVNT_VALID TI_SCI_MSG_FLAG(4) 774 #define MSG_FLAG_VINT_STS_BIT_VALID TI_SCI_MSG_FLAG(5) 775 #define MSG_FLAG_SHOST_VALID TI_SCI_MSG_FLAG(31) 776 u32 valid_params; 777 u16 src_id; 778 u16 src_index; 779 u16 dst_id; 780 u16 dst_host_irq; 781 u16 ia_id; 782 u16 vint; 783 u16 global_event; 784 u8 vint_status_bit; 785 u8 secondary_host; 786 } __packed; 787 788 /** 789 * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring 790 * 791 * Configures the non-real-time registers of a Navigator Subsystem ring. 792 * @hdr: Generic Header 793 * @valid_params: Bitfield defining validity of ring configuration parameters. 794 * The ring configuration fields are not valid, and will not be used for 795 * ring configuration, if their corresponding valid bit is zero. 796 * Valid bit usage: 797 * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo 798 * 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi 799 * 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count 800 * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode 801 * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size 802 * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id 803 * 6 - Valid bit for @tisci_msg_rm_ring_cfg_req virtid 804 * 7 - Valid bit for @tisci_msg_rm_ring_cfg_req ASEL 805 * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated 806 * @index: ring index to be configured. 807 * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's 808 * RING_BA_LO register 809 * @addr_hi: 16 MSBs of ring base address to be programmed into the ring's 810 * RING_BA_HI register. 811 * @count: Number of ring elements. Must be even if mode is CREDENTIALS or QM 812 * modes. 813 * @mode: Specifies the mode the ring is to be configured. 814 * @size: Specifies encoded ring element size. To calculate the encoded size use 815 * the formula (log2(size_bytes) - 2), where size_bytes cannot be 816 * greater than 256. 817 * @order_id: Specifies the ring's bus order ID. 818 * @virtid: Ring virt ID value 819 * @asel: Ring ASEL (address select) value to be set into the ASEL field of the 820 * ring's RING_BA_HI register. 821 */ 822 struct ti_sci_msg_rm_ring_cfg_req { 823 struct ti_sci_msg_hdr hdr; 824 u32 valid_params; 825 u16 nav_id; 826 u16 index; 827 u32 addr_lo; 828 u32 addr_hi; 829 u32 count; 830 u8 mode; 831 u8 size; 832 u8 order_id; 833 u16 virtid; 834 u8 asel; 835 } __packed; 836 837 /** 838 * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination 839 * thread 840 * @hdr: Generic Header 841 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is 842 * used to pair the source and destination threads. 843 * @src_thread: PSI-L source thread ID within the PSI-L System thread map. 844 * 845 * UDMAP transmit channels mapped to source threads will have their 846 * TCHAN_THRD_ID register programmed with the destination thread if the pairing 847 * is successful. 848 849 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map. 850 * PSI-L destination threads start at index 0x8000. The request is NACK'd if 851 * the destination thread is not greater than or equal to 0x8000. 852 * 853 * UDMAP receive channels mapped to destination threads will have their 854 * RCHAN_THRD_ID register programmed with the source thread if the pairing 855 * is successful. 856 * 857 * Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK 858 * message. 859 */ 860 struct ti_sci_msg_psil_pair { 861 struct ti_sci_msg_hdr hdr; 862 u32 nav_id; 863 u32 src_thread; 864 u32 dst_thread; 865 } __packed; 866 867 /** 868 * struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a 869 * destination thread 870 * @hdr: Generic Header 871 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is 872 * used to unpair the source and destination threads. 873 * @src_thread: PSI-L source thread ID within the PSI-L System thread map. 874 * 875 * UDMAP transmit channels mapped to source threads will have their 876 * TCHAN_THRD_ID register cleared if the unpairing is successful. 877 * 878 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map. 879 * PSI-L destination threads start at index 0x8000. The request is NACK'd if 880 * the destination thread is not greater than or equal to 0x8000. 881 * 882 * UDMAP receive channels mapped to destination threads will have their 883 * RCHAN_THRD_ID register cleared if the unpairing is successful. 884 * 885 * Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK 886 * message. 887 */ 888 struct ti_sci_msg_psil_unpair { 889 struct ti_sci_msg_hdr hdr; 890 u32 nav_id; 891 u32 src_thread; 892 u32 dst_thread; 893 } __packed; 894 895 /** 896 * struct ti_sci_msg_udmap_rx_flow_cfg - UDMAP receive flow configuration 897 * message 898 * @hdr: Generic Header 899 * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is 900 * allocated 901 * @flow_index: UDMAP receive flow index for non-optional configuration. 902 * @rx_ch_index: Specifies the index of the receive channel using the flow_index 903 * @rx_einfo_present: UDMAP receive flow extended packet info present. 904 * @rx_psinfo_present: UDMAP receive flow PS words present. 905 * @rx_error_handling: UDMAP receive flow error handling configuration. Valid 906 * values are TI_SCI_RM_UDMAP_RX_FLOW_ERR_DROP/RETRY. 907 * @rx_desc_type: UDMAP receive flow descriptor type. It can be one of 908 * TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST/MONO. 909 * @rx_sop_offset: UDMAP receive flow start of packet offset. 910 * @rx_dest_qnum: UDMAP receive flow destination queue number. 911 * @rx_ps_location: UDMAP receive flow PS words location. 912 * 0 - end of packet descriptor 913 * 1 - Beginning of the data buffer 914 * @rx_src_tag_hi: UDMAP receive flow source tag high byte constant 915 * @rx_src_tag_lo: UDMAP receive flow source tag low byte constant 916 * @rx_dest_tag_hi: UDMAP receive flow destination tag high byte constant 917 * @rx_dest_tag_lo: UDMAP receive flow destination tag low byte constant 918 * @rx_src_tag_hi_sel: UDMAP receive flow source tag high byte selector 919 * @rx_src_tag_lo_sel: UDMAP receive flow source tag low byte selector 920 * @rx_dest_tag_hi_sel: UDMAP receive flow destination tag high byte selector 921 * @rx_dest_tag_lo_sel: UDMAP receive flow destination tag low byte selector 922 * @rx_size_thresh_en: UDMAP receive flow packet size based free buffer queue 923 * enable. If enabled, the ti_sci_rm_udmap_rx_flow_opt_cfg also need to be 924 * configured and sent. 925 * @rx_fdq0_sz0_qnum: UDMAP receive flow free descriptor queue 0. 926 * @rx_fdq1_qnum: UDMAP receive flow free descriptor queue 1. 927 * @rx_fdq2_qnum: UDMAP receive flow free descriptor queue 2. 928 * @rx_fdq3_qnum: UDMAP receive flow free descriptor queue 3. 929 * 930 * For detailed information on the settings, see the UDMAP section of the TRM. 931 */ 932 struct ti_sci_msg_udmap_rx_flow_cfg { 933 struct ti_sci_msg_hdr hdr; 934 u32 nav_id; 935 u32 flow_index; 936 u32 rx_ch_index; 937 u8 rx_einfo_present; 938 u8 rx_psinfo_present; 939 u8 rx_error_handling; 940 u8 rx_desc_type; 941 u16 rx_sop_offset; 942 u16 rx_dest_qnum; 943 u8 rx_ps_location; 944 u8 rx_src_tag_hi; 945 u8 rx_src_tag_lo; 946 u8 rx_dest_tag_hi; 947 u8 rx_dest_tag_lo; 948 u8 rx_src_tag_hi_sel; 949 u8 rx_src_tag_lo_sel; 950 u8 rx_dest_tag_hi_sel; 951 u8 rx_dest_tag_lo_sel; 952 u8 rx_size_thresh_en; 953 u16 rx_fdq0_sz0_qnum; 954 u16 rx_fdq1_qnum; 955 u16 rx_fdq2_qnum; 956 u16 rx_fdq3_qnum; 957 } __packed; 958 959 /** 960 * struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg - parameters for UDMAP receive 961 * flow optional configuration 962 * @hdr: Generic Header 963 * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is 964 * allocated 965 * @flow_index: UDMAP receive flow index for optional configuration. 966 * @rx_ch_index: Specifies the index of the receive channel using the flow_index 967 * @rx_size_thresh0: UDMAP receive flow packet size threshold 0. 968 * @rx_size_thresh1: UDMAP receive flow packet size threshold 1. 969 * @rx_size_thresh2: UDMAP receive flow packet size threshold 2. 970 * @rx_fdq0_sz1_qnum: UDMAP receive flow free descriptor queue for size 971 * threshold 1. 972 * @rx_fdq0_sz2_qnum: UDMAP receive flow free descriptor queue for size 973 * threshold 2. 974 * @rx_fdq0_sz3_qnum: UDMAP receive flow free descriptor queue for size 975 * threshold 3. 976 * 977 * For detailed information on the settings, see the UDMAP section of the TRM. 978 */ 979 struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg { 980 struct ti_sci_msg_hdr hdr; 981 u32 nav_id; 982 u32 flow_index; 983 u32 rx_ch_index; 984 u16 rx_size_thresh0; 985 u16 rx_size_thresh1; 986 u16 rx_size_thresh2; 987 u16 rx_fdq0_sz1_qnum; 988 u16 rx_fdq0_sz2_qnum; 989 u16 rx_fdq0_sz3_qnum; 990 } __packed; 991 992 /** 993 * Configures a Navigator Subsystem UDMAP transmit channel 994 * 995 * Configures the non-real-time registers of a Navigator Subsystem UDMAP 996 * transmit channel. The channel index must be assigned to the host defined 997 * in the TISCI header via the RM board configuration resource assignment 998 * range list. 999 * 1000 * @hdr: Generic Header 1001 * 1002 * @valid_params: Bitfield defining validity of tx channel configuration 1003 * parameters. The tx channel configuration fields are not valid, and will not 1004 * be used for ch configuration, if their corresponding valid bit is zero. 1005 * Valid bit usage: 1006 * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err 1007 * 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype 1008 * 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type 1009 * 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size 1010 * 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum 1011 * 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority 1012 * 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos 1013 * 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid 1014 * 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority 1015 * 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo 1016 * 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords 1017 * 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt 1018 * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count 1019 * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth 1020 * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size 1021 * 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype 1022 * 16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type 1023 * 1024 * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located 1025 * 1026 * @index: UDMAP transmit channel index. 1027 * 1028 * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to 1029 * be programmed into the tx_pause_on_err field of the channel's TCHAN_TCFG 1030 * register. 1031 * 1032 * @tx_filt_einfo: UDMAP transmit channel extended packet information passing 1033 * configuration to be programmed into the tx_filt_einfo field of the 1034 * channel's TCHAN_TCFG register. 1035 * 1036 * @tx_filt_pswords: UDMAP transmit channel protocol specific word passing 1037 * configuration to be programmed into the tx_filt_pswords field of the 1038 * channel's TCHAN_TCFG register. 1039 * 1040 * @tx_atype: UDMAP transmit channel non Ring Accelerator access pointer 1041 * interpretation configuration to be programmed into the tx_atype field of 1042 * the channel's TCHAN_TCFG register. 1043 * 1044 * @tx_chan_type: UDMAP transmit channel functional channel type and work 1045 * passing mechanism configuration to be programmed into the tx_chan_type 1046 * field of the channel's TCHAN_TCFG register. 1047 * 1048 * @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression 1049 * configuration to be programmed into the tx_supr_tdpkt field of the channel's 1050 * TCHAN_TCFG register. 1051 * 1052 * @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to 1053 * fetch configuration to be programmed into the tx_fetch_size field of the 1054 * channel's TCHAN_TCFG register. The user must make sure to set the maximum 1055 * word count that can pass through the channel for any allowed descriptor type. 1056 * 1057 * @tx_credit_count: UDMAP transmit channel transfer request credit count 1058 * configuration to be programmed into the count field of the TCHAN_TCREDIT 1059 * register. Specifies how many credits for complete TRs are available. 1060 * 1061 * @txcq_qnum: UDMAP transmit channel completion queue configuration to be 1062 * programmed into the txcq_qnum field of the TCHAN_TCQ register. The specified 1063 * completion queue must be assigned to the host, or a subordinate of the host, 1064 * requesting configuration of the transmit channel. 1065 * 1066 * @tx_priority: UDMAP transmit channel transmit priority value to be programmed 1067 * into the priority field of the channel's TCHAN_TPRI_CTRL register. 1068 * 1069 * @tx_qos: UDMAP transmit channel transmit qos value to be programmed into the 1070 * qos field of the channel's TCHAN_TPRI_CTRL register. 1071 * 1072 * @tx_orderid: UDMAP transmit channel bus order id value to be programmed into 1073 * the orderid field of the channel's TCHAN_TPRI_CTRL register. 1074 * 1075 * @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed 1076 * into the fdepth field of the TCHAN_TFIFO_DEPTH register. Sets the number of 1077 * Tx FIFO bytes which are allowed to be stored for the channel. Check the UDMAP 1078 * section of the TRM for restrictions regarding this parameter. 1079 * 1080 * @tx_sched_priority: UDMAP transmit channel tx scheduling priority 1081 * configuration to be programmed into the priority field of the channel's 1082 * TCHAN_TST_SCHED register. 1083 * 1084 * @tx_burst_size: UDMAP transmit channel burst size configuration to be 1085 * programmed into the tx_burst_size field of the TCHAN_TCFG register. 1086 * 1087 * @tx_tdtype: UDMAP transmit channel teardown type configuration to be 1088 * programmed into the tdtype field of the TCHAN_TCFG register: 1089 * 0 - Return immediately 1090 * 1 - Wait for completion message from remote peer 1091 * 1092 * @extended_ch_type: Valid for BCDMA. 1093 * 0 - the channel is split tx channel (tchan) 1094 * 1 - the channel is block copy channel (bchan) 1095 */ 1096 struct ti_sci_msg_rm_udmap_tx_ch_cfg_req { 1097 struct ti_sci_msg_hdr hdr; 1098 u32 valid_params; 1099 u16 nav_id; 1100 u16 index; 1101 u8 tx_pause_on_err; 1102 u8 tx_filt_einfo; 1103 u8 tx_filt_pswords; 1104 u8 tx_atype; 1105 u8 tx_chan_type; 1106 u8 tx_supr_tdpkt; 1107 u16 tx_fetch_size; 1108 u8 tx_credit_count; 1109 u16 txcq_qnum; 1110 u8 tx_priority; 1111 u8 tx_qos; 1112 u8 tx_orderid; 1113 u16 fdepth; 1114 u8 tx_sched_priority; 1115 u8 tx_burst_size; 1116 u8 tx_tdtype; 1117 u8 extended_ch_type; 1118 } __packed; 1119 1120 /** 1121 * Configures a Navigator Subsystem UDMAP receive channel 1122 * 1123 * Configures the non-real-time registers of a Navigator Subsystem UDMAP 1124 * receive channel. The channel index must be assigned to the host defined 1125 * in the TISCI header via the RM board configuration resource assignment 1126 * range list. 1127 * 1128 * @hdr: Generic Header 1129 * 1130 * @valid_params: Bitfield defining validity of rx channel configuration 1131 * parameters. 1132 * The rx channel configuration fields are not valid, and will not be used for 1133 * ch configuration, if their corresponding valid bit is zero. 1134 * Valid bit usage: 1135 * 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err 1136 * 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype 1137 * 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type 1138 * 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size 1139 * 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum 1140 * 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority 1141 * 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos 1142 * 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid 1143 * 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority 1144 * 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start 1145 * 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt 1146 * 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short 1147 * 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long 1148 * 14 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size 1149 * 1150 * @nav_id: SoC device ID of Navigator Subsystem where rx channel is located 1151 * 1152 * @index: UDMAP receive channel index. 1153 * 1154 * @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to 1155 * fetch configuration to be programmed into the rx_fetch_size field of the 1156 * channel's RCHAN_RCFG register. 1157 * 1158 * @rxcq_qnum: UDMAP receive channel completion queue configuration to be 1159 * programmed into the rxcq_qnum field of the RCHAN_RCQ register. 1160 * The specified completion queue must be assigned to the host, or a subordinate 1161 * of the host, requesting configuration of the receive channel. 1162 * 1163 * @rx_priority: UDMAP receive channel receive priority value to be programmed 1164 * into the priority field of the channel's RCHAN_RPRI_CTRL register. 1165 * 1166 * @rx_qos: UDMAP receive channel receive qos value to be programmed into the 1167 * qos field of the channel's RCHAN_RPRI_CTRL register. 1168 * 1169 * @rx_orderid: UDMAP receive channel bus order id value to be programmed into 1170 * the orderid field of the channel's RCHAN_RPRI_CTRL register. 1171 * 1172 * @rx_sched_priority: UDMAP receive channel rx scheduling priority 1173 * configuration to be programmed into the priority field of the channel's 1174 * RCHAN_RST_SCHED register. 1175 * 1176 * @flowid_start: UDMAP receive channel additional flows starting index 1177 * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG 1178 * register. Specifies the starting index for flow IDs the receive channel is to 1179 * make use of beyond the default flow. flowid_start and @ref flowid_cnt must be 1180 * set as valid and configured together. The starting flow ID set by 1181 * @ref flowid_cnt must be a flow index within the Navigator Subsystem's subset 1182 * of flows beyond the default flows statically mapped to receive channels. 1183 * The additional flows must be assigned to the host, or a subordinate of the 1184 * host, requesting configuration of the receive channel. 1185 * 1186 * @flowid_cnt: UDMAP receive channel additional flows count configuration to 1187 * program into the flowid_cnt field of the RCHAN_RFLOW_RNG register. 1188 * This field specifies how many flow IDs are in the additional contiguous range 1189 * of legal flow IDs for the channel. @ref flowid_start and flowid_cnt must be 1190 * set as valid and configured together. Disabling the valid_params field bit 1191 * for flowid_cnt indicates no flow IDs other than the default are to be 1192 * allocated and used by the receive channel. @ref flowid_start plus flowid_cnt 1193 * cannot be greater than the number of receive flows in the receive channel's 1194 * Navigator Subsystem. The additional flows must be assigned to the host, or a 1195 * subordinate of the host, requesting configuration of the receive channel. 1196 * 1197 * @rx_pause_on_err: UDMAP receive channel pause on error configuration to be 1198 * programmed into the rx_pause_on_err field of the channel's RCHAN_RCFG 1199 * register. 1200 * 1201 * @rx_atype: UDMAP receive channel non Ring Accelerator access pointer 1202 * interpretation configuration to be programmed into the rx_atype field of the 1203 * channel's RCHAN_RCFG register. 1204 * 1205 * @rx_chan_type: UDMAP receive channel functional channel type and work passing 1206 * mechanism configuration to be programmed into the rx_chan_type field of the 1207 * channel's RCHAN_RCFG register. 1208 * 1209 * @rx_ignore_short: UDMAP receive channel short packet treatment configuration 1210 * to be programmed into the rx_ignore_short field of the RCHAN_RCFG register. 1211 * 1212 * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to 1213 * be programmed into the rx_ignore_long field of the RCHAN_RCFG register. 1214 * 1215 * @rx_burst_size: UDMAP receive channel burst size configuration to be 1216 * programmed into the rx_burst_size field of the RCHAN_RCFG register. 1217 */ 1218 struct ti_sci_msg_rm_udmap_rx_ch_cfg_req { 1219 struct ti_sci_msg_hdr hdr; 1220 u32 valid_params; 1221 u16 nav_id; 1222 u16 index; 1223 u16 rx_fetch_size; 1224 u16 rxcq_qnum; 1225 u8 rx_priority; 1226 u8 rx_qos; 1227 u8 rx_orderid; 1228 u8 rx_sched_priority; 1229 u16 flowid_start; 1230 u16 flowid_cnt; 1231 u8 rx_pause_on_err; 1232 u8 rx_atype; 1233 u8 rx_chan_type; 1234 u8 rx_ignore_short; 1235 u8 rx_ignore_long; 1236 u8 rx_burst_size; 1237 } __packed; 1238 1239 /** 1240 * Configures a Navigator Subsystem UDMAP receive flow 1241 * 1242 * Configures a Navigator Subsystem UDMAP receive flow's registers. 1243 * Configuration does not include the flow registers which handle size-based 1244 * free descriptor queue routing. 1245 * 1246 * The flow index must be assigned to the host defined in the TISCI header via 1247 * the RM board configuration resource assignment range list. 1248 * 1249 * @hdr: Standard TISCI header 1250 * 1251 * @valid_params 1252 * Bitfield defining validity of rx flow configuration parameters. The 1253 * rx flow configuration fields are not valid, and will not be used for flow 1254 * configuration, if their corresponding valid bit is zero. Valid bit usage: 1255 * 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present 1256 * 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present 1257 * 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling 1258 * 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type 1259 * 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset 1260 * 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum 1261 * 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi 1262 * 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo 1263 * 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi 1264 * 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo 1265 * 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel 1266 * 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel 1267 * 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel 1268 * 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel 1269 * 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum 1270 * 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum 1271 * 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum 1272 * 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum 1273 * 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location 1274 * 1275 * @nav_id: SoC device ID of Navigator Subsystem from which the receive flow is 1276 * allocated 1277 * 1278 * @flow_index: UDMAP receive flow index for non-optional configuration. 1279 * 1280 * @rx_einfo_present: 1281 * UDMAP receive flow extended packet info present configuration to be 1282 * programmed into the rx_einfo_present field of the flow's RFLOW_RFA register. 1283 * 1284 * @rx_psinfo_present: 1285 * UDMAP receive flow PS words present configuration to be programmed into the 1286 * rx_psinfo_present field of the flow's RFLOW_RFA register. 1287 * 1288 * @rx_error_handling: 1289 * UDMAP receive flow error handling configuration to be programmed into the 1290 * rx_error_handling field of the flow's RFLOW_RFA register. 1291 * 1292 * @rx_desc_type: 1293 * UDMAP receive flow descriptor type configuration to be programmed into the 1294 * rx_desc_type field field of the flow's RFLOW_RFA register. 1295 * 1296 * @rx_sop_offset: 1297 * UDMAP receive flow start of packet offset configuration to be programmed 1298 * into the rx_sop_offset field of the RFLOW_RFA register. See the UDMAP 1299 * section of the TRM for more information on this setting. Valid values for 1300 * this field are 0-255 bytes. 1301 * 1302 * @rx_dest_qnum: 1303 * UDMAP receive flow destination queue configuration to be programmed into the 1304 * rx_dest_qnum field of the flow's RFLOW_RFA register. The specified 1305 * destination queue must be valid within the Navigator Subsystem and must be 1306 * owned by the host, or a subordinate of the host, requesting allocation and 1307 * configuration of the receive flow. 1308 * 1309 * @rx_src_tag_hi: 1310 * UDMAP receive flow source tag high byte constant configuration to be 1311 * programmed into the rx_src_tag_hi field of the flow's RFLOW_RFB register. 1312 * See the UDMAP section of the TRM for more information on this setting. 1313 * 1314 * @rx_src_tag_lo: 1315 * UDMAP receive flow source tag low byte constant configuration to be 1316 * programmed into the rx_src_tag_lo field of the flow's RFLOW_RFB register. 1317 * See the UDMAP section of the TRM for more information on this setting. 1318 * 1319 * @rx_dest_tag_hi: 1320 * UDMAP receive flow destination tag high byte constant configuration to be 1321 * programmed into the rx_dest_tag_hi field of the flow's RFLOW_RFB register. 1322 * See the UDMAP section of the TRM for more information on this setting. 1323 * 1324 * @rx_dest_tag_lo: 1325 * UDMAP receive flow destination tag low byte constant configuration to be 1326 * programmed into the rx_dest_tag_lo field of the flow's RFLOW_RFB register. 1327 * See the UDMAP section of the TRM for more information on this setting. 1328 * 1329 * @rx_src_tag_hi_sel: 1330 * UDMAP receive flow source tag high byte selector configuration to be 1331 * programmed into the rx_src_tag_hi_sel field of the RFLOW_RFC register. See 1332 * the UDMAP section of the TRM for more information on this setting. 1333 * 1334 * @rx_src_tag_lo_sel: 1335 * UDMAP receive flow source tag low byte selector configuration to be 1336 * programmed into the rx_src_tag_lo_sel field of the RFLOW_RFC register. See 1337 * the UDMAP section of the TRM for more information on this setting. 1338 * 1339 * @rx_dest_tag_hi_sel: 1340 * UDMAP receive flow destination tag high byte selector configuration to be 1341 * programmed into the rx_dest_tag_hi_sel field of the RFLOW_RFC register. See 1342 * the UDMAP section of the TRM for more information on this setting. 1343 * 1344 * @rx_dest_tag_lo_sel: 1345 * UDMAP receive flow destination tag low byte selector configuration to be 1346 * programmed into the rx_dest_tag_lo_sel field of the RFLOW_RFC register. See 1347 * the UDMAP section of the TRM for more information on this setting. 1348 * 1349 * @rx_fdq0_sz0_qnum: 1350 * UDMAP receive flow free descriptor queue 0 configuration to be programmed 1351 * into the rx_fdq0_sz0_qnum field of the flow's RFLOW_RFD register. See the 1352 * UDMAP section of the TRM for more information on this setting. The specified 1353 * free queue must be valid within the Navigator Subsystem and must be owned 1354 * by the host, or a subordinate of the host, requesting allocation and 1355 * configuration of the receive flow. 1356 * 1357 * @rx_fdq1_qnum: 1358 * UDMAP receive flow free descriptor queue 1 configuration to be programmed 1359 * into the rx_fdq1_qnum field of the flow's RFLOW_RFD register. See the 1360 * UDMAP section of the TRM for more information on this setting. The specified 1361 * free queue must be valid within the Navigator Subsystem and must be owned 1362 * by the host, or a subordinate of the host, requesting allocation and 1363 * configuration of the receive flow. 1364 * 1365 * @rx_fdq2_qnum: 1366 * UDMAP receive flow free descriptor queue 2 configuration to be programmed 1367 * into the rx_fdq2_qnum field of the flow's RFLOW_RFE register. See the 1368 * UDMAP section of the TRM for more information on this setting. The specified 1369 * free queue must be valid within the Navigator Subsystem and must be owned 1370 * by the host, or a subordinate of the host, requesting allocation and 1371 * configuration of the receive flow. 1372 * 1373 * @rx_fdq3_qnum: 1374 * UDMAP receive flow free descriptor queue 3 configuration to be programmed 1375 * into the rx_fdq3_qnum field of the flow's RFLOW_RFE register. See the 1376 * UDMAP section of the TRM for more information on this setting. The specified 1377 * free queue must be valid within the Navigator Subsystem and must be owned 1378 * by the host, or a subordinate of the host, requesting allocation and 1379 * configuration of the receive flow. 1380 * 1381 * @rx_ps_location: 1382 * UDMAP receive flow PS words location configuration to be programmed into the 1383 * rx_ps_location field of the flow's RFLOW_RFA register. 1384 */ 1385 struct ti_sci_msg_rm_udmap_flow_cfg_req { 1386 struct ti_sci_msg_hdr hdr; 1387 u32 valid_params; 1388 u16 nav_id; 1389 u16 flow_index; 1390 u8 rx_einfo_present; 1391 u8 rx_psinfo_present; 1392 u8 rx_error_handling; 1393 u8 rx_desc_type; 1394 u16 rx_sop_offset; 1395 u16 rx_dest_qnum; 1396 u8 rx_src_tag_hi; 1397 u8 rx_src_tag_lo; 1398 u8 rx_dest_tag_hi; 1399 u8 rx_dest_tag_lo; 1400 u8 rx_src_tag_hi_sel; 1401 u8 rx_src_tag_lo_sel; 1402 u8 rx_dest_tag_hi_sel; 1403 u8 rx_dest_tag_lo_sel; 1404 u16 rx_fdq0_sz0_qnum; 1405 u16 rx_fdq1_qnum; 1406 u16 rx_fdq2_qnum; 1407 u16 rx_fdq3_qnum; 1408 u8 rx_ps_location; 1409 } __packed; 1410 1411 /** 1412 * struct ti_sci_msg_req_proc_request - Request a processor 1413 * @hdr: Generic Header 1414 * @processor_id: ID of processor being requested 1415 * 1416 * Request type is TI_SCI_MSG_PROC_REQUEST, response is a generic ACK/NACK 1417 * message. 1418 */ 1419 struct ti_sci_msg_req_proc_request { 1420 struct ti_sci_msg_hdr hdr; 1421 u8 processor_id; 1422 } __packed; 1423 1424 /** 1425 * struct ti_sci_msg_req_proc_release - Release a processor 1426 * @hdr: Generic Header 1427 * @processor_id: ID of processor being released 1428 * 1429 * Request type is TI_SCI_MSG_PROC_RELEASE, response is a generic ACK/NACK 1430 * message. 1431 */ 1432 struct ti_sci_msg_req_proc_release { 1433 struct ti_sci_msg_hdr hdr; 1434 u8 processor_id; 1435 } __packed; 1436 1437 /** 1438 * struct ti_sci_msg_req_proc_handover - Handover a processor to a host 1439 * @hdr: Generic Header 1440 * @processor_id: ID of processor being handed over 1441 * @host_id: Host ID the control needs to be transferred to 1442 * 1443 * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK 1444 * message. 1445 */ 1446 struct ti_sci_msg_req_proc_handover { 1447 struct ti_sci_msg_hdr hdr; 1448 u8 processor_id; 1449 u8 host_id; 1450 } __packed; 1451 1452 /* Boot Vector masks */ 1453 #define TI_SCI_ADDR_LOW_MASK GENMASK_ULL(31, 0) 1454 #define TI_SCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32) 1455 #define TI_SCI_ADDR_HIGH_SHIFT 32 1456 1457 /** 1458 * struct ti_sci_msg_req_set_config - Set Processor boot configuration 1459 * @hdr: Generic Header 1460 * @processor_id: ID of processor being configured 1461 * @bootvector_low: Lower 32 bit address (Little Endian) of boot vector 1462 * @bootvector_high: Higher 32 bit address (Little Endian) of boot vector 1463 * @config_flags_set: Optional Processor specific Config Flags to set. 1464 * Setting a bit here implies the corresponding mode 1465 * will be set 1466 * @config_flags_clear: Optional Processor specific Config Flags to clear. 1467 * Setting a bit here implies the corresponding mode 1468 * will be cleared 1469 * 1470 * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK 1471 * message. 1472 */ 1473 struct ti_sci_msg_req_set_config { 1474 struct ti_sci_msg_hdr hdr; 1475 u8 processor_id; 1476 u32 bootvector_low; 1477 u32 bootvector_high; 1478 u32 config_flags_set; 1479 u32 config_flags_clear; 1480 } __packed; 1481 1482 /** 1483 * struct ti_sci_msg_req_set_ctrl - Set Processor boot control flags 1484 * @hdr: Generic Header 1485 * @processor_id: ID of processor being configured 1486 * @control_flags_set: Optional Processor specific Control Flags to set. 1487 * Setting a bit here implies the corresponding mode 1488 * will be set 1489 * @control_flags_clear:Optional Processor specific Control Flags to clear. 1490 * Setting a bit here implies the corresponding mode 1491 * will be cleared 1492 * 1493 * Request type is TI_SCI_MSG_SET_CTRL, response is a generic ACK/NACK 1494 * message. 1495 */ 1496 struct ti_sci_msg_req_set_ctrl { 1497 struct ti_sci_msg_hdr hdr; 1498 u8 processor_id; 1499 u32 control_flags_set; 1500 u32 control_flags_clear; 1501 } __packed; 1502 1503 /** 1504 * struct ti_sci_msg_req_get_status - Processor boot status request 1505 * @hdr: Generic Header 1506 * @processor_id: ID of processor whose status is being requested 1507 * 1508 * Request type is TI_SCI_MSG_GET_STATUS, response is an appropriate 1509 * message, or NACK in case of inability to satisfy request. 1510 */ 1511 struct ti_sci_msg_req_get_status { 1512 struct ti_sci_msg_hdr hdr; 1513 u8 processor_id; 1514 } __packed; 1515 1516 /** 1517 * struct ti_sci_msg_resp_get_status - Processor boot status response 1518 * @hdr: Generic Header 1519 * @processor_id: ID of processor whose status is returned 1520 * @bootvector_low: Lower 32 bit address (Little Endian) of boot vector 1521 * @bootvector_high: Higher 32 bit address (Little Endian) of boot vector 1522 * @config_flags: Optional Processor specific Config Flags set currently 1523 * @control_flags: Optional Processor specific Control Flags set currently 1524 * @status_flags: Optional Processor specific Status Flags set currently 1525 * 1526 * Response structure to a TI_SCI_MSG_GET_STATUS request. 1527 */ 1528 struct ti_sci_msg_resp_get_status { 1529 struct ti_sci_msg_hdr hdr; 1530 u8 processor_id; 1531 u32 bootvector_low; 1532 u32 bootvector_high; 1533 u32 config_flags; 1534 u32 control_flags; 1535 u32 status_flags; 1536 } __packed; 1537 1538 #endif /* __TI_SCI_H */ 1539