1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Texas Instruments System Control Interface (TISCI) Protocol 4 * 5 * Communication protocol with TI SCI hardware 6 * The system works in a message response protocol 7 * See: https://software-dl.ti.com/tisci/esd/latest/index.html for details 8 * 9 * Copyright (C) 2015-2024 Texas Instruments Incorporated - https://www.ti.com/ 10 */ 11 12 #ifndef __TI_SCI_H 13 #define __TI_SCI_H 14 15 /* Generic Messages */ 16 #define TI_SCI_MSG_ENABLE_WDT 0x0000 17 #define TI_SCI_MSG_WAKE_RESET 0x0001 18 #define TI_SCI_MSG_VERSION 0x0002 19 #define TI_SCI_MSG_WAKE_REASON 0x0003 20 #define TI_SCI_MSG_GOODBYE 0x0004 21 #define TI_SCI_MSG_SYS_RESET 0x0005 22 #define TI_SCI_MSG_QUERY_FW_CAPS 0x0022 23 24 /* Device requests */ 25 #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200 26 #define TI_SCI_MSG_GET_DEVICE_STATE 0x0201 27 #define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202 28 29 /* Clock requests */ 30 #define TI_SCI_MSG_SET_CLOCK_STATE 0x0100 31 #define TI_SCI_MSG_GET_CLOCK_STATE 0x0101 32 #define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102 33 #define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103 34 #define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104 35 #define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c 36 #define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d 37 #define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e 38 39 /* Low Power Mode Requests */ 40 #define TI_SCI_MSG_PREPARE_SLEEP 0x0300 41 #define TI_SCI_MSG_LPM_WAKE_REASON 0x0306 42 #define TI_SCI_MSG_SET_IO_ISOLATION 0x0307 43 #define TI_SCI_MSG_LPM_SET_DEVICE_CONSTRAINT 0x0309 44 #define TI_SCI_MSG_LPM_SET_LATENCY_CONSTRAINT 0x030A 45 #define TI_SCI_MSG_LPM_ABORT 0x0311 46 47 /* Resource Management Requests */ 48 #define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500 49 50 /* IRQ requests */ 51 #define TI_SCI_MSG_SET_IRQ 0x1000 52 #define TI_SCI_MSG_FREE_IRQ 0x1001 53 54 /* NAVSS resource management */ 55 /* Ringacc requests */ 56 #define TI_SCI_MSG_RM_RING_ALLOCATE 0x1100 57 #define TI_SCI_MSG_RM_RING_FREE 0x1101 58 #define TI_SCI_MSG_RM_RING_RECONFIG 0x1102 59 #define TI_SCI_MSG_RM_RING_RESET 0x1103 60 #define TI_SCI_MSG_RM_RING_CFG 0x1110 61 62 /* PSI-L requests */ 63 #define TI_SCI_MSG_RM_PSIL_PAIR 0x1280 64 #define TI_SCI_MSG_RM_PSIL_UNPAIR 0x1281 65 66 #define TI_SCI_MSG_RM_UDMAP_TX_ALLOC 0x1200 67 #define TI_SCI_MSG_RM_UDMAP_TX_FREE 0x1201 68 #define TI_SCI_MSG_RM_UDMAP_RX_ALLOC 0x1210 69 #define TI_SCI_MSG_RM_UDMAP_RX_FREE 0x1211 70 #define TI_SCI_MSG_RM_UDMAP_FLOW_CFG 0x1220 71 #define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG 0x1221 72 73 #define TISCI_MSG_RM_UDMAP_TX_CH_CFG 0x1205 74 #define TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG 0x1206 75 #define TISCI_MSG_RM_UDMAP_RX_CH_CFG 0x1215 76 #define TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG 0x1216 77 #define TISCI_MSG_RM_UDMAP_FLOW_CFG 0x1230 78 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG 0x1231 79 #define TISCI_MSG_RM_UDMAP_FLOW_GET_CFG 0x1232 80 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG 0x1233 81 82 /* Processor Control requests */ 83 #define TI_SCI_MSG_PROC_REQUEST 0xc000 84 #define TI_SCI_MSG_PROC_RELEASE 0xc001 85 #define TI_SCI_MSG_PROC_HANDOVER 0xc005 86 #define TI_SCI_MSG_SET_CONFIG 0xc100 87 #define TI_SCI_MSG_SET_CTRL 0xc101 88 #define TI_SCI_MSG_GET_STATUS 0xc400 89 90 /** 91 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses 92 * @type: Type of messages: One of TI_SCI_MSG* values 93 * @host: Host of the message 94 * @seq: Message identifier indicating a transfer sequence 95 * @flags: Flag for the message 96 */ 97 struct ti_sci_msg_hdr { 98 u16 type; 99 u8 host; 100 u8 seq; 101 #define TI_SCI_MSG_FLAG(val) (1 << (val)) 102 #define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0 103 #define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0) 104 #define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1) 105 #define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0 106 #define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1) 107 /* Additional Flags */ 108 u32 flags; 109 } __packed; 110 111 /** 112 * struct ti_sci_msg_resp_version - Response for a message 113 * @hdr: Generic header 114 * @firmware_description: String describing the firmware 115 * @firmware_revision: Firmware revision 116 * @abi_major: Major version of the ABI that firmware supports 117 * @abi_minor: Minor version of the ABI that firmware supports 118 * 119 * In general, ABI version changes follow the rule that minor version increments 120 * are backward compatible. Major revision changes in ABI may not be 121 * backward compatible. 122 * 123 * Response to a generic message with message type TI_SCI_MSG_VERSION 124 */ 125 struct ti_sci_msg_resp_version { 126 struct ti_sci_msg_hdr hdr; 127 char firmware_description[32]; 128 u16 firmware_revision; 129 u8 abi_major; 130 u8 abi_minor; 131 } __packed; 132 133 /** 134 * struct ti_sci_msg_req_reboot - Reboot the SoC 135 * @hdr: Generic Header 136 * 137 * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic 138 * ACK/NACK message. 139 */ 140 struct ti_sci_msg_req_reboot { 141 struct ti_sci_msg_hdr hdr; 142 } __packed; 143 144 /** 145 * struct ti_sci_msg_resp_query_fw_caps - Response for query firmware caps 146 * @hdr: Generic header 147 * @fw_caps: Each bit in fw_caps indicating one FW/SOC capability 148 * MSG_FLAG_CAPS_GENERIC: Generic capability (LPM not supported) 149 * MSG_FLAG_CAPS_LPM_PARTIAL_IO: Partial IO in LPM 150 * MSG_FLAG_CAPS_LPM_DM_MANAGED: LPM can be managed by DM 151 * MSG_FLAG_CAPS_LPM_ABORT: Abort entry to LPM 152 * 153 * Response to a generic message with message type TI_SCI_MSG_QUERY_FW_CAPS 154 * providing currently available SOC/firmware capabilities. SoC that don't 155 * support low power modes return only MSG_FLAG_CAPS_GENERIC capability. 156 */ 157 struct ti_sci_msg_resp_query_fw_caps { 158 struct ti_sci_msg_hdr hdr; 159 #define MSG_FLAG_CAPS_GENERIC TI_SCI_MSG_FLAG(0) 160 #define MSG_FLAG_CAPS_LPM_PARTIAL_IO TI_SCI_MSG_FLAG(4) 161 #define MSG_FLAG_CAPS_LPM_DM_MANAGED TI_SCI_MSG_FLAG(5) 162 #define MSG_FLAG_CAPS_LPM_ABORT TI_SCI_MSG_FLAG(9) 163 #define MSG_MASK_CAPS_LPM GENMASK_ULL(4, 1) 164 u64 fw_caps; 165 } __packed; 166 167 /** 168 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device 169 * @hdr: Generic header 170 * @id: Indicates which device to modify 171 * @reserved: Reserved space in message, must be 0 for backward compatibility 172 * @state: The desired state of the device. 173 * 174 * Certain flags can also be set to alter the device state: 175 * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source. 176 * The meaning of this flag will vary slightly from device to device and from 177 * SoC to SoC but it generally allows the device to wake the SoC out of deep 178 * suspend states. 179 * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device. 180 * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed 181 * with STATE_RETENTION or STATE_ON, it will claim the device exclusively. 182 * If another host already has this device set to STATE_RETENTION or STATE_ON, 183 * the message will fail. Once successful, other hosts attempting to set 184 * STATE_RETENTION or STATE_ON will fail. 185 * 186 * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic 187 * ACK/NACK message. 188 */ 189 struct ti_sci_msg_req_set_device_state { 190 /* Additional hdr->flags options */ 191 #define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8) 192 #define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9) 193 #define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10) 194 struct ti_sci_msg_hdr hdr; 195 u32 id; 196 u32 reserved; 197 198 #define MSG_DEVICE_SW_STATE_AUTO_OFF 0 199 #define MSG_DEVICE_SW_STATE_RETENTION 1 200 #define MSG_DEVICE_SW_STATE_ON 2 201 u8 state; 202 } __packed; 203 204 /** 205 * struct ti_sci_msg_req_get_device_state - Request to get device. 206 * @hdr: Generic header 207 * @id: Device Identifier 208 * 209 * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state 210 * information 211 */ 212 struct ti_sci_msg_req_get_device_state { 213 struct ti_sci_msg_hdr hdr; 214 u32 id; 215 } __packed; 216 217 /** 218 * struct ti_sci_msg_resp_get_device_state - Response to get device request. 219 * @hdr: Generic header 220 * @context_loss_count: Indicates how many times the device has lost context. A 221 * driver can use this monotonic counter to determine if the device has 222 * lost context since the last time this message was exchanged. 223 * @resets: Programmed state of the reset lines. 224 * @programmed_state: The state as programmed by set_device. 225 * - Uses the MSG_DEVICE_SW_* macros 226 * @current_state: The actual state of the hardware. 227 * 228 * Response to request TI_SCI_MSG_GET_DEVICE_STATE. 229 */ 230 struct ti_sci_msg_resp_get_device_state { 231 struct ti_sci_msg_hdr hdr; 232 u32 context_loss_count; 233 u32 resets; 234 u8 programmed_state; 235 #define MSG_DEVICE_HW_STATE_OFF 0 236 #define MSG_DEVICE_HW_STATE_ON 1 237 #define MSG_DEVICE_HW_STATE_TRANS 2 238 u8 current_state; 239 } __packed; 240 241 /** 242 * struct ti_sci_msg_req_set_device_resets - Set the desired resets 243 * configuration of the device 244 * @hdr: Generic header 245 * @id: Indicates which device to modify 246 * @resets: A bit field of resets for the device. The meaning, behavior, 247 * and usage of the reset flags are device specific. 0 for a bit 248 * indicates releasing the reset represented by that bit while 1 249 * indicates keeping it held. 250 * 251 * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic 252 * ACK/NACK message. 253 */ 254 struct ti_sci_msg_req_set_device_resets { 255 struct ti_sci_msg_hdr hdr; 256 u32 id; 257 u32 resets; 258 } __packed; 259 260 /** 261 * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state 262 * @hdr: Generic Header, Certain flags can be set specific to the clocks: 263 * MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified 264 * via spread spectrum clocking. 265 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's 266 * frequency to be changed while it is running so long as it 267 * is within the min/max limits. 268 * MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this 269 * is only applicable to clock inputs on the SoC pseudo-device. 270 * @dev_id: Device identifier this request is for 271 * @clk_id: Clock identifier for the device for this request. 272 * Each device has it's own set of clock inputs. This indexes 273 * which clock input to modify. Set to 255 if clock ID is 274 * greater than or equal to 255. 275 * @request_state: Request the state for the clock to be set to. 276 * MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock, 277 * it can be disabled, regardless of the state of the device 278 * MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to 279 * automatically manage the state of this clock. If the device 280 * is enabled, then the clock is enabled. If the device is set 281 * to off or retention, then the clock is internally set as not 282 * being required by the device.(default) 283 * MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled, 284 * regardless of the state of the device. 285 * @clk_id_32: Clock identifier for the device for this request. 286 * Only to be used if the clock ID is greater than or equal to 287 * 255. 288 * 289 * Normally, all required clocks are managed by TISCI entity, this is used 290 * only for specific control *IF* required. Auto managed state is 291 * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote 292 * will explicitly control. 293 * 294 * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic 295 * ACK or NACK message. 296 */ 297 struct ti_sci_msg_req_set_clock_state { 298 /* Additional hdr->flags options */ 299 #define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8) 300 #define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9) 301 #define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10) 302 struct ti_sci_msg_hdr hdr; 303 u32 dev_id; 304 u8 clk_id; 305 #define MSG_CLOCK_SW_STATE_UNREQ 0 306 #define MSG_CLOCK_SW_STATE_AUTO 1 307 #define MSG_CLOCK_SW_STATE_REQ 2 308 u8 request_state; 309 u32 clk_id_32; 310 } __packed; 311 312 /** 313 * struct ti_sci_msg_req_get_clock_state - Request for clock state 314 * @hdr: Generic Header 315 * @dev_id: Device identifier this request is for 316 * @clk_id: Clock identifier for the device for this request. 317 * Each device has it's own set of clock inputs. This indexes 318 * which clock input to get state of. Set to 255 if the clock 319 * ID is greater than or equal to 255. 320 * @clk_id_32: Clock identifier for the device for the request. 321 * Only to be used if the clock ID is greater than or equal to 322 * 255. 323 * 324 * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state 325 * of the clock 326 */ 327 struct ti_sci_msg_req_get_clock_state { 328 struct ti_sci_msg_hdr hdr; 329 u32 dev_id; 330 u8 clk_id; 331 u32 clk_id_32; 332 } __packed; 333 334 /** 335 * struct ti_sci_msg_resp_get_clock_state - Response to get clock state 336 * @hdr: Generic Header 337 * @programmed_state: Any programmed state of the clock. This is one of 338 * MSG_CLOCK_SW_STATE* values. 339 * @current_state: Current state of the clock. This is one of: 340 * MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready 341 * MSG_CLOCK_HW_STATE_READY: Clock is ready 342 * 343 * Response to TI_SCI_MSG_GET_CLOCK_STATE. 344 */ 345 struct ti_sci_msg_resp_get_clock_state { 346 struct ti_sci_msg_hdr hdr; 347 u8 programmed_state; 348 #define MSG_CLOCK_HW_STATE_NOT_READY 0 349 #define MSG_CLOCK_HW_STATE_READY 1 350 u8 current_state; 351 } __packed; 352 353 /** 354 * struct ti_sci_msg_req_set_clock_parent - Set the clock parent 355 * @hdr: Generic Header 356 * @dev_id: Device identifier this request is for 357 * @clk_id: Clock identifier for the device for this request. 358 * Each device has it's own set of clock inputs. This indexes 359 * which clock input to modify. Set to 255 if clock ID is 360 * greater than or equal to 255. 361 * @parent_id: The new clock parent is selectable by an index via this 362 * parameter. Set to 255 if clock ID is greater than or 363 * equal to 255. 364 * @clk_id_32: Clock identifier if @clk_id field is 255. 365 * @parent_id_32: Parent identifier if @parent_id is 255. 366 * 367 * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic 368 * ACK / NACK message. 369 */ 370 struct ti_sci_msg_req_set_clock_parent { 371 struct ti_sci_msg_hdr hdr; 372 u32 dev_id; 373 u8 clk_id; 374 u8 parent_id; 375 u32 clk_id_32; 376 u32 parent_id_32; 377 } __packed; 378 379 /** 380 * struct ti_sci_msg_req_get_clock_parent - Get the clock parent 381 * @hdr: Generic Header 382 * @dev_id: Device identifier this request is for 383 * @clk_id: Clock identifier for the device for this request. 384 * Each device has it's own set of clock inputs. This indexes 385 * which clock input to get the parent for. If this field 386 * contains 255, the actual clock identifier is stored in 387 * @clk_id_32. 388 * @clk_id_32: Clock identifier if the @clk_id field contains 255. 389 * 390 * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information 391 */ 392 struct ti_sci_msg_req_get_clock_parent { 393 struct ti_sci_msg_hdr hdr; 394 u32 dev_id; 395 u8 clk_id; 396 u32 clk_id_32; 397 } __packed; 398 399 /** 400 * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent 401 * @hdr: Generic Header 402 * @parent_id: The current clock parent. If set to 255, the current parent 403 * ID can be found from the @parent_id_32 field. 404 * @parent_id_32: Current clock parent if @parent_id field is set to 405 * 255. 406 * 407 * Response to TI_SCI_MSG_GET_CLOCK_PARENT. 408 */ 409 struct ti_sci_msg_resp_get_clock_parent { 410 struct ti_sci_msg_hdr hdr; 411 u8 parent_id; 412 u32 parent_id_32; 413 } __packed; 414 415 /** 416 * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents 417 * @hdr: Generic header 418 * @dev_id: Device identifier this request is for 419 * @clk_id: Clock identifier for the device for this request. Set to 420 * 255 if clock ID is greater than or equal to 255. 421 * @clk_id_32: Clock identifier if the @clk_id field contains 255. 422 * 423 * This request provides information about how many clock parent options 424 * are available for a given clock to a device. This is typically used 425 * for input clocks. 426 * 427 * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate 428 * message, or NACK in case of inability to satisfy request. 429 */ 430 struct ti_sci_msg_req_get_clock_num_parents { 431 struct ti_sci_msg_hdr hdr; 432 u32 dev_id; 433 u8 clk_id; 434 u32 clk_id_32; 435 } __packed; 436 437 /** 438 * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents 439 * @hdr: Generic header 440 * @num_parents: Number of clock parents. If set to 255, the actual 441 * number of parents is stored into @num_parents_32 442 * field instead. 443 * @num_parents_32: Number of clock parents if @num_parents field is 444 * set to 255. 445 * 446 * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 447 */ 448 struct ti_sci_msg_resp_get_clock_num_parents { 449 struct ti_sci_msg_hdr hdr; 450 u8 num_parents; 451 u32 num_parents_32; 452 } __packed; 453 454 /** 455 * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency 456 * @hdr: Generic Header 457 * @dev_id: Device identifier this request is for 458 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum 459 * allowable programmed frequency and does not account for clock 460 * tolerances and jitter. 461 * @target_freq_hz: The target clock frequency. A frequency will be found 462 * as close to this target frequency as possible. 463 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum 464 * allowable programmed frequency and does not account for clock 465 * tolerances and jitter. 466 * @clk_id: Clock identifier for the device for this request. Set to 467 * 255 if clock identifier is greater than or equal to 255. 468 * @clk_id_32: Clock identifier if @clk_id is set to 255. 469 * 470 * NOTE: Normally clock frequency management is automatically done by TISCI 471 * entity. In case of specific requests, TISCI evaluates capability to achieve 472 * requested frequency within provided range and responds with 473 * result message. 474 * 475 * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message, 476 * or NACK in case of inability to satisfy request. 477 */ 478 struct ti_sci_msg_req_query_clock_freq { 479 struct ti_sci_msg_hdr hdr; 480 u32 dev_id; 481 u64 min_freq_hz; 482 u64 target_freq_hz; 483 u64 max_freq_hz; 484 u8 clk_id; 485 u32 clk_id_32; 486 } __packed; 487 488 /** 489 * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query 490 * @hdr: Generic Header 491 * @freq_hz: Frequency that is the best match in Hz. 492 * 493 * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request 494 * cannot be satisfied, the message will be of type NACK. 495 */ 496 struct ti_sci_msg_resp_query_clock_freq { 497 struct ti_sci_msg_hdr hdr; 498 u64 freq_hz; 499 } __packed; 500 501 /** 502 * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency 503 * @hdr: Generic Header 504 * @dev_id: Device identifier this request is for 505 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum 506 * allowable programmed frequency and does not account for clock 507 * tolerances and jitter. 508 * @target_freq_hz: The target clock frequency. The clock will be programmed 509 * at a rate as close to this target frequency as possible. 510 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum 511 * allowable programmed frequency and does not account for clock 512 * tolerances and jitter. 513 * @clk_id: Clock identifier for the device for this request. Set to 514 * 255 if clock ID is greater than or equal to 255. 515 * @clk_id_32: Clock identifier if @clk_id field is set to 255. 516 * 517 * NOTE: Normally clock frequency management is automatically done by TISCI 518 * entity. In case of specific requests, TISCI evaluates capability to achieve 519 * requested range and responds with success/failure message. 520 * 521 * This sets the desired frequency for a clock within an allowable 522 * range. This message will fail on an enabled clock unless 523 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally, 524 * if other clocks have their frequency modified due to this message, 525 * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled. 526 * 527 * Calling set frequency on a clock input to the SoC pseudo-device will 528 * inform the PMMC of that clock's frequency. Setting a frequency of 529 * zero will indicate the clock is disabled. 530 * 531 * Calling set frequency on clock outputs from the SoC pseudo-device will 532 * function similarly to setting the clock frequency on a device. 533 * 534 * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK 535 * message. 536 */ 537 struct ti_sci_msg_req_set_clock_freq { 538 struct ti_sci_msg_hdr hdr; 539 u32 dev_id; 540 u64 min_freq_hz; 541 u64 target_freq_hz; 542 u64 max_freq_hz; 543 u8 clk_id; 544 u32 clk_id_32; 545 } __packed; 546 547 /** 548 * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency 549 * @hdr: Generic Header 550 * @dev_id: Device identifier this request is for 551 * @clk_id: Clock identifier for the device for this request. Set to 552 * 255 if clock ID is greater than or equal to 255. 553 * @clk_id_32: Clock identifier if @clk_id field is set to 255. 554 * 555 * NOTE: Normally clock frequency management is automatically done by TISCI 556 * entity. In some cases, clock frequencies are configured by host. 557 * 558 * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency 559 * that the clock is currently at. 560 */ 561 struct ti_sci_msg_req_get_clock_freq { 562 struct ti_sci_msg_hdr hdr; 563 u32 dev_id; 564 u8 clk_id; 565 u32 clk_id_32; 566 } __packed; 567 568 /** 569 * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request 570 * @hdr: Generic Header 571 * @freq_hz: Frequency that the clock is currently on, in Hz. 572 * 573 * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ. 574 */ 575 struct ti_sci_msg_resp_get_clock_freq { 576 struct ti_sci_msg_hdr hdr; 577 u64 freq_hz; 578 } __packed; 579 580 /** 581 * struct tisci_msg_req_prepare_sleep - Request for TISCI_MSG_PREPARE_SLEEP. 582 * 583 * @hdr TISCI header to provide ACK/NAK flags to the host. 584 * @mode Low power mode to enter. 585 * @ctx_lo Low 32-bits of physical pointer to address to use for context save. 586 * @ctx_hi High 32-bits of physical pointer to address to use for context save. 587 * @debug_flags Flags that can be set to halt the sequence during suspend or 588 * resume to allow JTAG connection and debug. 589 * 590 * This message is used as the first step of entering a low power mode. It 591 * allows configurable information, including which state to enter to be 592 * easily shared from the application, as this is a non-secure message and 593 * therefore can be sent by anyone. 594 */ 595 struct ti_sci_msg_req_prepare_sleep { 596 struct ti_sci_msg_hdr hdr; 597 598 #define TISCI_MSG_VALUE_SLEEP_MODE_DM_MANAGED 0xfd 599 u8 mode; 600 u32 ctx_lo; 601 u32 ctx_hi; 602 u32 debug_flags; 603 } __packed; 604 605 /** 606 * struct tisci_msg_set_io_isolation_req - Request for TI_SCI_MSG_SET_IO_ISOLATION. 607 * 608 * @hdr: Generic header 609 * @state: The deseared state of the IO isolation. 610 * 611 * This message is used to enable/disable IO isolation for low power modes. 612 * Response is generic ACK / NACK message. 613 */ 614 struct ti_sci_msg_req_set_io_isolation { 615 struct ti_sci_msg_hdr hdr; 616 u8 state; 617 } __packed; 618 619 /** 620 * struct ti_sci_msg_resp_lpm_wake_reason - Response for TI_SCI_MSG_LPM_WAKE_REASON. 621 * 622 * @hdr: Generic header. 623 * @wake_source: The wake up source that woke soc from LPM. 624 * @wake_timestamp: Timestamp at which soc woke. 625 * @wake_pin: The pin that has triggered wake up. 626 * @mode: The last entered low power mode. 627 * @rsvd: Reserved for future use. 628 * 629 * Response to a generic message with message type TI_SCI_MSG_LPM_WAKE_REASON, 630 * used to query the wake up source, pin and entered low power mode. 631 */ 632 struct ti_sci_msg_resp_lpm_wake_reason { 633 struct ti_sci_msg_hdr hdr; 634 u32 wake_source; 635 u64 wake_timestamp; 636 u8 wake_pin; 637 u8 mode; 638 u32 rsvd[2]; 639 } __packed; 640 641 /** 642 * struct ti_sci_msg_req_lpm_set_device_constraint - Request for 643 * TISCI_MSG_LPM_SET_DEVICE_CONSTRAINT. 644 * 645 * @hdr: TISCI header to provide ACK/NAK flags to the host. 646 * @id: Device ID of device whose constraint has to be modified. 647 * @state: The desired state of device constraint: set or clear. 648 * @rsvd: Reserved for future use. 649 * 650 * This message is used by host to set constraint on the device. This can be 651 * sent anytime after boot before prepare sleep message. Any device can set a 652 * constraint on the low power mode that the SoC can enter. It allows 653 * configurable information to be easily shared from the application, as this 654 * is a non-secure message and therefore can be sent by anyone. By setting a 655 * constraint, the device ensures that it will not be powered off or reset in 656 * the selected mode. Note: Access Restriction: Exclusivity flag of Device will 657 * be honored. If some other host already has constraint on this device ID, 658 * NACK will be returned. 659 */ 660 struct ti_sci_msg_req_lpm_set_device_constraint { 661 struct ti_sci_msg_hdr hdr; 662 u32 id; 663 u8 state; 664 u32 rsvd[2]; 665 } __packed; 666 667 /** 668 * struct ti_sci_msg_req_lpm_set_latency_constraint - Request for 669 * TISCI_MSG_LPM_SET_LATENCY_CONSTRAINT. 670 * 671 * @hdr: TISCI header to provide ACK/NAK flags to the host. 672 * @wkup_latency: The maximum acceptable latency to wake up from low power mode 673 * in milliseconds. The deeper the state, the higher the latency. 674 * @state: The desired state of wakeup latency constraint: set or clear. 675 * @rsvd: Reserved for future use. 676 * 677 * This message is used by host to set wakeup latency from low power mode. This can 678 * be sent anytime after boot before prepare sleep message, and can be sent after 679 * current low power mode is exited. Any device can set a constraint on the low power 680 * mode that the SoC can enter. It allows configurable information to be easily shared 681 * from the application, as this is a non-secure message and therefore can be sent by 682 * anyone. By setting a wakeup latency constraint, the host ensures that the resume time 683 * from selected low power mode will be less than the constraint value. 684 */ 685 struct ti_sci_msg_req_lpm_set_latency_constraint { 686 struct ti_sci_msg_hdr hdr; 687 u16 latency; 688 u8 state; 689 u32 rsvd; 690 } __packed; 691 692 #define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff 693 694 /** 695 * struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned 696 * range of resources. 697 * @hdr: Generic Header 698 * @type: Unique resource assignment type 699 * @subtype: Resource assignment subtype within the resource type. 700 * @secondary_host: Host processing entity to which the resources are 701 * allocated. This is required only when the destination 702 * host id id different from ti sci interface host id, 703 * else TI_SCI_IRQ_SECONDARY_HOST_INVALID can be passed. 704 * 705 * Request type is TI_SCI_MSG_GET_RESOURCE_RANGE. Responded with requested 706 * resource range which is of type TI_SCI_MSG_GET_RESOURCE_RANGE. 707 */ 708 struct ti_sci_msg_req_get_resource_range { 709 struct ti_sci_msg_hdr hdr; 710 #define MSG_RM_RESOURCE_TYPE_MASK GENMASK(9, 0) 711 #define MSG_RM_RESOURCE_SUBTYPE_MASK GENMASK(5, 0) 712 u16 type; 713 u8 subtype; 714 u8 secondary_host; 715 } __packed; 716 717 /** 718 * struct ti_sci_msg_resp_get_resource_range - Response to resource get range. 719 * @hdr: Generic Header 720 * @range_start: Start index of the first resource range. 721 * @range_num: Number of resources in the first range. 722 * @range_start_sec: Start index of the second resource range. 723 * @range_num_sec: Number of resources in the second range. 724 * 725 * Response to request TI_SCI_MSG_GET_RESOURCE_RANGE. 726 */ 727 struct ti_sci_msg_resp_get_resource_range { 728 struct ti_sci_msg_hdr hdr; 729 u16 range_start; 730 u16 range_num; 731 u16 range_start_sec; 732 u16 range_num_sec; 733 } __packed; 734 735 /** 736 * struct ti_sci_msg_req_manage_irq - Request to configure/release the route 737 * between the dev and the host. 738 * @hdr: Generic Header 739 * @valid_params: Bit fields defining the validity of interrupt source 740 * parameters. If a bit is not set, then corresponding 741 * field is not valid and will not be used for route set. 742 * Bit field definitions: 743 * 0 - Valid bit for @dst_id 744 * 1 - Valid bit for @dst_host_irq 745 * 2 - Valid bit for @ia_id 746 * 3 - Valid bit for @vint 747 * 4 - Valid bit for @global_event 748 * 5 - Valid bit for @vint_status_bit_index 749 * 31 - Valid bit for @secondary_host 750 * @src_id: IRQ source peripheral ID. 751 * @src_index: IRQ source index within the peripheral 752 * @dst_id: IRQ Destination ID. Based on the architecture it can be 753 * IRQ controller or host processor ID. 754 * @dst_host_irq: IRQ number of the destination host IRQ controller 755 * @ia_id: Device ID of the interrupt aggregator in which the 756 * vint resides. 757 * @vint: Virtual interrupt number if the interrupt route 758 * is through an interrupt aggregator. 759 * @global_event: Global event that is to be mapped to interrupt 760 * aggregator virtual interrupt status bit. 761 * @vint_status_bit: Virtual interrupt status bit if the interrupt route 762 * utilizes an interrupt aggregator status bit. 763 * @secondary_host: Host ID of the IRQ destination computing entity. This is 764 * required only when destination host id is different 765 * from ti sci interface host id. 766 * 767 * Request type is TI_SCI_MSG_SET/RELEASE_IRQ. 768 * Response is generic ACK / NACK message. 769 */ 770 struct ti_sci_msg_req_manage_irq { 771 struct ti_sci_msg_hdr hdr; 772 #define MSG_FLAG_DST_ID_VALID TI_SCI_MSG_FLAG(0) 773 #define MSG_FLAG_DST_HOST_IRQ_VALID TI_SCI_MSG_FLAG(1) 774 #define MSG_FLAG_IA_ID_VALID TI_SCI_MSG_FLAG(2) 775 #define MSG_FLAG_VINT_VALID TI_SCI_MSG_FLAG(3) 776 #define MSG_FLAG_GLB_EVNT_VALID TI_SCI_MSG_FLAG(4) 777 #define MSG_FLAG_VINT_STS_BIT_VALID TI_SCI_MSG_FLAG(5) 778 #define MSG_FLAG_SHOST_VALID TI_SCI_MSG_FLAG(31) 779 u32 valid_params; 780 u16 src_id; 781 u16 src_index; 782 u16 dst_id; 783 u16 dst_host_irq; 784 u16 ia_id; 785 u16 vint; 786 u16 global_event; 787 u8 vint_status_bit; 788 u8 secondary_host; 789 } __packed; 790 791 /** 792 * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring 793 * 794 * Configures the non-real-time registers of a Navigator Subsystem ring. 795 * @hdr: Generic Header 796 * @valid_params: Bitfield defining validity of ring configuration parameters. 797 * The ring configuration fields are not valid, and will not be used for 798 * ring configuration, if their corresponding valid bit is zero. 799 * Valid bit usage: 800 * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo 801 * 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi 802 * 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count 803 * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode 804 * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size 805 * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id 806 * 6 - Valid bit for @tisci_msg_rm_ring_cfg_req virtid 807 * 7 - Valid bit for @tisci_msg_rm_ring_cfg_req ASEL 808 * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated 809 * @index: ring index to be configured. 810 * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's 811 * RING_BA_LO register 812 * @addr_hi: 16 MSBs of ring base address to be programmed into the ring's 813 * RING_BA_HI register. 814 * @count: Number of ring elements. Must be even if mode is CREDENTIALS or QM 815 * modes. 816 * @mode: Specifies the mode the ring is to be configured. 817 * @size: Specifies encoded ring element size. To calculate the encoded size use 818 * the formula (log2(size_bytes) - 2), where size_bytes cannot be 819 * greater than 256. 820 * @order_id: Specifies the ring's bus order ID. 821 * @virtid: Ring virt ID value 822 * @asel: Ring ASEL (address select) value to be set into the ASEL field of the 823 * ring's RING_BA_HI register. 824 */ 825 struct ti_sci_msg_rm_ring_cfg_req { 826 struct ti_sci_msg_hdr hdr; 827 u32 valid_params; 828 u16 nav_id; 829 u16 index; 830 u32 addr_lo; 831 u32 addr_hi; 832 u32 count; 833 u8 mode; 834 u8 size; 835 u8 order_id; 836 u16 virtid; 837 u8 asel; 838 } __packed; 839 840 /** 841 * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination 842 * thread 843 * @hdr: Generic Header 844 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is 845 * used to pair the source and destination threads. 846 * @src_thread: PSI-L source thread ID within the PSI-L System thread map. 847 * 848 * UDMAP transmit channels mapped to source threads will have their 849 * TCHAN_THRD_ID register programmed with the destination thread if the pairing 850 * is successful. 851 852 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map. 853 * PSI-L destination threads start at index 0x8000. The request is NACK'd if 854 * the destination thread is not greater than or equal to 0x8000. 855 * 856 * UDMAP receive channels mapped to destination threads will have their 857 * RCHAN_THRD_ID register programmed with the source thread if the pairing 858 * is successful. 859 * 860 * Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK 861 * message. 862 */ 863 struct ti_sci_msg_psil_pair { 864 struct ti_sci_msg_hdr hdr; 865 u32 nav_id; 866 u32 src_thread; 867 u32 dst_thread; 868 } __packed; 869 870 /** 871 * struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a 872 * destination thread 873 * @hdr: Generic Header 874 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is 875 * used to unpair the source and destination threads. 876 * @src_thread: PSI-L source thread ID within the PSI-L System thread map. 877 * 878 * UDMAP transmit channels mapped to source threads will have their 879 * TCHAN_THRD_ID register cleared if the unpairing is successful. 880 * 881 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map. 882 * PSI-L destination threads start at index 0x8000. The request is NACK'd if 883 * the destination thread is not greater than or equal to 0x8000. 884 * 885 * UDMAP receive channels mapped to destination threads will have their 886 * RCHAN_THRD_ID register cleared if the unpairing is successful. 887 * 888 * Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK 889 * message. 890 */ 891 struct ti_sci_msg_psil_unpair { 892 struct ti_sci_msg_hdr hdr; 893 u32 nav_id; 894 u32 src_thread; 895 u32 dst_thread; 896 } __packed; 897 898 /** 899 * struct ti_sci_msg_udmap_rx_flow_cfg - UDMAP receive flow configuration 900 * message 901 * @hdr: Generic Header 902 * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is 903 * allocated 904 * @flow_index: UDMAP receive flow index for non-optional configuration. 905 * @rx_ch_index: Specifies the index of the receive channel using the flow_index 906 * @rx_einfo_present: UDMAP receive flow extended packet info present. 907 * @rx_psinfo_present: UDMAP receive flow PS words present. 908 * @rx_error_handling: UDMAP receive flow error handling configuration. Valid 909 * values are TI_SCI_RM_UDMAP_RX_FLOW_ERR_DROP/RETRY. 910 * @rx_desc_type: UDMAP receive flow descriptor type. It can be one of 911 * TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST/MONO. 912 * @rx_sop_offset: UDMAP receive flow start of packet offset. 913 * @rx_dest_qnum: UDMAP receive flow destination queue number. 914 * @rx_ps_location: UDMAP receive flow PS words location. 915 * 0 - end of packet descriptor 916 * 1 - Beginning of the data buffer 917 * @rx_src_tag_hi: UDMAP receive flow source tag high byte constant 918 * @rx_src_tag_lo: UDMAP receive flow source tag low byte constant 919 * @rx_dest_tag_hi: UDMAP receive flow destination tag high byte constant 920 * @rx_dest_tag_lo: UDMAP receive flow destination tag low byte constant 921 * @rx_src_tag_hi_sel: UDMAP receive flow source tag high byte selector 922 * @rx_src_tag_lo_sel: UDMAP receive flow source tag low byte selector 923 * @rx_dest_tag_hi_sel: UDMAP receive flow destination tag high byte selector 924 * @rx_dest_tag_lo_sel: UDMAP receive flow destination tag low byte selector 925 * @rx_size_thresh_en: UDMAP receive flow packet size based free buffer queue 926 * enable. If enabled, the ti_sci_rm_udmap_rx_flow_opt_cfg also need to be 927 * configured and sent. 928 * @rx_fdq0_sz0_qnum: UDMAP receive flow free descriptor queue 0. 929 * @rx_fdq1_qnum: UDMAP receive flow free descriptor queue 1. 930 * @rx_fdq2_qnum: UDMAP receive flow free descriptor queue 2. 931 * @rx_fdq3_qnum: UDMAP receive flow free descriptor queue 3. 932 * 933 * For detailed information on the settings, see the UDMAP section of the TRM. 934 */ 935 struct ti_sci_msg_udmap_rx_flow_cfg { 936 struct ti_sci_msg_hdr hdr; 937 u32 nav_id; 938 u32 flow_index; 939 u32 rx_ch_index; 940 u8 rx_einfo_present; 941 u8 rx_psinfo_present; 942 u8 rx_error_handling; 943 u8 rx_desc_type; 944 u16 rx_sop_offset; 945 u16 rx_dest_qnum; 946 u8 rx_ps_location; 947 u8 rx_src_tag_hi; 948 u8 rx_src_tag_lo; 949 u8 rx_dest_tag_hi; 950 u8 rx_dest_tag_lo; 951 u8 rx_src_tag_hi_sel; 952 u8 rx_src_tag_lo_sel; 953 u8 rx_dest_tag_hi_sel; 954 u8 rx_dest_tag_lo_sel; 955 u8 rx_size_thresh_en; 956 u16 rx_fdq0_sz0_qnum; 957 u16 rx_fdq1_qnum; 958 u16 rx_fdq2_qnum; 959 u16 rx_fdq3_qnum; 960 } __packed; 961 962 /** 963 * struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg - parameters for UDMAP receive 964 * flow optional configuration 965 * @hdr: Generic Header 966 * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is 967 * allocated 968 * @flow_index: UDMAP receive flow index for optional configuration. 969 * @rx_ch_index: Specifies the index of the receive channel using the flow_index 970 * @rx_size_thresh0: UDMAP receive flow packet size threshold 0. 971 * @rx_size_thresh1: UDMAP receive flow packet size threshold 1. 972 * @rx_size_thresh2: UDMAP receive flow packet size threshold 2. 973 * @rx_fdq0_sz1_qnum: UDMAP receive flow free descriptor queue for size 974 * threshold 1. 975 * @rx_fdq0_sz2_qnum: UDMAP receive flow free descriptor queue for size 976 * threshold 2. 977 * @rx_fdq0_sz3_qnum: UDMAP receive flow free descriptor queue for size 978 * threshold 3. 979 * 980 * For detailed information on the settings, see the UDMAP section of the TRM. 981 */ 982 struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg { 983 struct ti_sci_msg_hdr hdr; 984 u32 nav_id; 985 u32 flow_index; 986 u32 rx_ch_index; 987 u16 rx_size_thresh0; 988 u16 rx_size_thresh1; 989 u16 rx_size_thresh2; 990 u16 rx_fdq0_sz1_qnum; 991 u16 rx_fdq0_sz2_qnum; 992 u16 rx_fdq0_sz3_qnum; 993 } __packed; 994 995 /** 996 * Configures a Navigator Subsystem UDMAP transmit channel 997 * 998 * Configures the non-real-time registers of a Navigator Subsystem UDMAP 999 * transmit channel. The channel index must be assigned to the host defined 1000 * in the TISCI header via the RM board configuration resource assignment 1001 * range list. 1002 * 1003 * @hdr: Generic Header 1004 * 1005 * @valid_params: Bitfield defining validity of tx channel configuration 1006 * parameters. The tx channel configuration fields are not valid, and will not 1007 * be used for ch configuration, if their corresponding valid bit is zero. 1008 * Valid bit usage: 1009 * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err 1010 * 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype 1011 * 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type 1012 * 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size 1013 * 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum 1014 * 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority 1015 * 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos 1016 * 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid 1017 * 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority 1018 * 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo 1019 * 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords 1020 * 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt 1021 * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count 1022 * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth 1023 * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size 1024 * 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype 1025 * 16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type 1026 * 1027 * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located 1028 * 1029 * @index: UDMAP transmit channel index. 1030 * 1031 * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to 1032 * be programmed into the tx_pause_on_err field of the channel's TCHAN_TCFG 1033 * register. 1034 * 1035 * @tx_filt_einfo: UDMAP transmit channel extended packet information passing 1036 * configuration to be programmed into the tx_filt_einfo field of the 1037 * channel's TCHAN_TCFG register. 1038 * 1039 * @tx_filt_pswords: UDMAP transmit channel protocol specific word passing 1040 * configuration to be programmed into the tx_filt_pswords field of the 1041 * channel's TCHAN_TCFG register. 1042 * 1043 * @tx_atype: UDMAP transmit channel non Ring Accelerator access pointer 1044 * interpretation configuration to be programmed into the tx_atype field of 1045 * the channel's TCHAN_TCFG register. 1046 * 1047 * @tx_chan_type: UDMAP transmit channel functional channel type and work 1048 * passing mechanism configuration to be programmed into the tx_chan_type 1049 * field of the channel's TCHAN_TCFG register. 1050 * 1051 * @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression 1052 * configuration to be programmed into the tx_supr_tdpkt field of the channel's 1053 * TCHAN_TCFG register. 1054 * 1055 * @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to 1056 * fetch configuration to be programmed into the tx_fetch_size field of the 1057 * channel's TCHAN_TCFG register. The user must make sure to set the maximum 1058 * word count that can pass through the channel for any allowed descriptor type. 1059 * 1060 * @tx_credit_count: UDMAP transmit channel transfer request credit count 1061 * configuration to be programmed into the count field of the TCHAN_TCREDIT 1062 * register. Specifies how many credits for complete TRs are available. 1063 * 1064 * @txcq_qnum: UDMAP transmit channel completion queue configuration to be 1065 * programmed into the txcq_qnum field of the TCHAN_TCQ register. The specified 1066 * completion queue must be assigned to the host, or a subordinate of the host, 1067 * requesting configuration of the transmit channel. 1068 * 1069 * @tx_priority: UDMAP transmit channel transmit priority value to be programmed 1070 * into the priority field of the channel's TCHAN_TPRI_CTRL register. 1071 * 1072 * @tx_qos: UDMAP transmit channel transmit qos value to be programmed into the 1073 * qos field of the channel's TCHAN_TPRI_CTRL register. 1074 * 1075 * @tx_orderid: UDMAP transmit channel bus order id value to be programmed into 1076 * the orderid field of the channel's TCHAN_TPRI_CTRL register. 1077 * 1078 * @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed 1079 * into the fdepth field of the TCHAN_TFIFO_DEPTH register. Sets the number of 1080 * Tx FIFO bytes which are allowed to be stored for the channel. Check the UDMAP 1081 * section of the TRM for restrictions regarding this parameter. 1082 * 1083 * @tx_sched_priority: UDMAP transmit channel tx scheduling priority 1084 * configuration to be programmed into the priority field of the channel's 1085 * TCHAN_TST_SCHED register. 1086 * 1087 * @tx_burst_size: UDMAP transmit channel burst size configuration to be 1088 * programmed into the tx_burst_size field of the TCHAN_TCFG register. 1089 * 1090 * @tx_tdtype: UDMAP transmit channel teardown type configuration to be 1091 * programmed into the tdtype field of the TCHAN_TCFG register: 1092 * 0 - Return immediately 1093 * 1 - Wait for completion message from remote peer 1094 * 1095 * @extended_ch_type: Valid for BCDMA. 1096 * 0 - the channel is split tx channel (tchan) 1097 * 1 - the channel is block copy channel (bchan) 1098 */ 1099 struct ti_sci_msg_rm_udmap_tx_ch_cfg_req { 1100 struct ti_sci_msg_hdr hdr; 1101 u32 valid_params; 1102 u16 nav_id; 1103 u16 index; 1104 u8 tx_pause_on_err; 1105 u8 tx_filt_einfo; 1106 u8 tx_filt_pswords; 1107 u8 tx_atype; 1108 u8 tx_chan_type; 1109 u8 tx_supr_tdpkt; 1110 u16 tx_fetch_size; 1111 u8 tx_credit_count; 1112 u16 txcq_qnum; 1113 u8 tx_priority; 1114 u8 tx_qos; 1115 u8 tx_orderid; 1116 u16 fdepth; 1117 u8 tx_sched_priority; 1118 u8 tx_burst_size; 1119 u8 tx_tdtype; 1120 u8 extended_ch_type; 1121 } __packed; 1122 1123 /** 1124 * Configures a Navigator Subsystem UDMAP receive channel 1125 * 1126 * Configures the non-real-time registers of a Navigator Subsystem UDMAP 1127 * receive channel. The channel index must be assigned to the host defined 1128 * in the TISCI header via the RM board configuration resource assignment 1129 * range list. 1130 * 1131 * @hdr: Generic Header 1132 * 1133 * @valid_params: Bitfield defining validity of rx channel configuration 1134 * parameters. 1135 * The rx channel configuration fields are not valid, and will not be used for 1136 * ch configuration, if their corresponding valid bit is zero. 1137 * Valid bit usage: 1138 * 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err 1139 * 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype 1140 * 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type 1141 * 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size 1142 * 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum 1143 * 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority 1144 * 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos 1145 * 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid 1146 * 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority 1147 * 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start 1148 * 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt 1149 * 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short 1150 * 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long 1151 * 14 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size 1152 * 1153 * @nav_id: SoC device ID of Navigator Subsystem where rx channel is located 1154 * 1155 * @index: UDMAP receive channel index. 1156 * 1157 * @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to 1158 * fetch configuration to be programmed into the rx_fetch_size field of the 1159 * channel's RCHAN_RCFG register. 1160 * 1161 * @rxcq_qnum: UDMAP receive channel completion queue configuration to be 1162 * programmed into the rxcq_qnum field of the RCHAN_RCQ register. 1163 * The specified completion queue must be assigned to the host, or a subordinate 1164 * of the host, requesting configuration of the receive channel. 1165 * 1166 * @rx_priority: UDMAP receive channel receive priority value to be programmed 1167 * into the priority field of the channel's RCHAN_RPRI_CTRL register. 1168 * 1169 * @rx_qos: UDMAP receive channel receive qos value to be programmed into the 1170 * qos field of the channel's RCHAN_RPRI_CTRL register. 1171 * 1172 * @rx_orderid: UDMAP receive channel bus order id value to be programmed into 1173 * the orderid field of the channel's RCHAN_RPRI_CTRL register. 1174 * 1175 * @rx_sched_priority: UDMAP receive channel rx scheduling priority 1176 * configuration to be programmed into the priority field of the channel's 1177 * RCHAN_RST_SCHED register. 1178 * 1179 * @flowid_start: UDMAP receive channel additional flows starting index 1180 * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG 1181 * register. Specifies the starting index for flow IDs the receive channel is to 1182 * make use of beyond the default flow. flowid_start and @ref flowid_cnt must be 1183 * set as valid and configured together. The starting flow ID set by 1184 * @ref flowid_cnt must be a flow index within the Navigator Subsystem's subset 1185 * of flows beyond the default flows statically mapped to receive channels. 1186 * The additional flows must be assigned to the host, or a subordinate of the 1187 * host, requesting configuration of the receive channel. 1188 * 1189 * @flowid_cnt: UDMAP receive channel additional flows count configuration to 1190 * program into the flowid_cnt field of the RCHAN_RFLOW_RNG register. 1191 * This field specifies how many flow IDs are in the additional contiguous range 1192 * of legal flow IDs for the channel. @ref flowid_start and flowid_cnt must be 1193 * set as valid and configured together. Disabling the valid_params field bit 1194 * for flowid_cnt indicates no flow IDs other than the default are to be 1195 * allocated and used by the receive channel. @ref flowid_start plus flowid_cnt 1196 * cannot be greater than the number of receive flows in the receive channel's 1197 * Navigator Subsystem. The additional flows must be assigned to the host, or a 1198 * subordinate of the host, requesting configuration of the receive channel. 1199 * 1200 * @rx_pause_on_err: UDMAP receive channel pause on error configuration to be 1201 * programmed into the rx_pause_on_err field of the channel's RCHAN_RCFG 1202 * register. 1203 * 1204 * @rx_atype: UDMAP receive channel non Ring Accelerator access pointer 1205 * interpretation configuration to be programmed into the rx_atype field of the 1206 * channel's RCHAN_RCFG register. 1207 * 1208 * @rx_chan_type: UDMAP receive channel functional channel type and work passing 1209 * mechanism configuration to be programmed into the rx_chan_type field of the 1210 * channel's RCHAN_RCFG register. 1211 * 1212 * @rx_ignore_short: UDMAP receive channel short packet treatment configuration 1213 * to be programmed into the rx_ignore_short field of the RCHAN_RCFG register. 1214 * 1215 * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to 1216 * be programmed into the rx_ignore_long field of the RCHAN_RCFG register. 1217 * 1218 * @rx_burst_size: UDMAP receive channel burst size configuration to be 1219 * programmed into the rx_burst_size field of the RCHAN_RCFG register. 1220 */ 1221 struct ti_sci_msg_rm_udmap_rx_ch_cfg_req { 1222 struct ti_sci_msg_hdr hdr; 1223 u32 valid_params; 1224 u16 nav_id; 1225 u16 index; 1226 u16 rx_fetch_size; 1227 u16 rxcq_qnum; 1228 u8 rx_priority; 1229 u8 rx_qos; 1230 u8 rx_orderid; 1231 u8 rx_sched_priority; 1232 u16 flowid_start; 1233 u16 flowid_cnt; 1234 u8 rx_pause_on_err; 1235 u8 rx_atype; 1236 u8 rx_chan_type; 1237 u8 rx_ignore_short; 1238 u8 rx_ignore_long; 1239 u8 rx_burst_size; 1240 } __packed; 1241 1242 /** 1243 * Configures a Navigator Subsystem UDMAP receive flow 1244 * 1245 * Configures a Navigator Subsystem UDMAP receive flow's registers. 1246 * Configuration does not include the flow registers which handle size-based 1247 * free descriptor queue routing. 1248 * 1249 * The flow index must be assigned to the host defined in the TISCI header via 1250 * the RM board configuration resource assignment range list. 1251 * 1252 * @hdr: Standard TISCI header 1253 * 1254 * @valid_params 1255 * Bitfield defining validity of rx flow configuration parameters. The 1256 * rx flow configuration fields are not valid, and will not be used for flow 1257 * configuration, if their corresponding valid bit is zero. Valid bit usage: 1258 * 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present 1259 * 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present 1260 * 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling 1261 * 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type 1262 * 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset 1263 * 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum 1264 * 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi 1265 * 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo 1266 * 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi 1267 * 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo 1268 * 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel 1269 * 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel 1270 * 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel 1271 * 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel 1272 * 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum 1273 * 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum 1274 * 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum 1275 * 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum 1276 * 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location 1277 * 1278 * @nav_id: SoC device ID of Navigator Subsystem from which the receive flow is 1279 * allocated 1280 * 1281 * @flow_index: UDMAP receive flow index for non-optional configuration. 1282 * 1283 * @rx_einfo_present: 1284 * UDMAP receive flow extended packet info present configuration to be 1285 * programmed into the rx_einfo_present field of the flow's RFLOW_RFA register. 1286 * 1287 * @rx_psinfo_present: 1288 * UDMAP receive flow PS words present configuration to be programmed into the 1289 * rx_psinfo_present field of the flow's RFLOW_RFA register. 1290 * 1291 * @rx_error_handling: 1292 * UDMAP receive flow error handling configuration to be programmed into the 1293 * rx_error_handling field of the flow's RFLOW_RFA register. 1294 * 1295 * @rx_desc_type: 1296 * UDMAP receive flow descriptor type configuration to be programmed into the 1297 * rx_desc_type field field of the flow's RFLOW_RFA register. 1298 * 1299 * @rx_sop_offset: 1300 * UDMAP receive flow start of packet offset configuration to be programmed 1301 * into the rx_sop_offset field of the RFLOW_RFA register. See the UDMAP 1302 * section of the TRM for more information on this setting. Valid values for 1303 * this field are 0-255 bytes. 1304 * 1305 * @rx_dest_qnum: 1306 * UDMAP receive flow destination queue configuration to be programmed into the 1307 * rx_dest_qnum field of the flow's RFLOW_RFA register. The specified 1308 * destination queue must be valid within the Navigator Subsystem and must be 1309 * owned by the host, or a subordinate of the host, requesting allocation and 1310 * configuration of the receive flow. 1311 * 1312 * @rx_src_tag_hi: 1313 * UDMAP receive flow source tag high byte constant configuration to be 1314 * programmed into the rx_src_tag_hi field of the flow's RFLOW_RFB register. 1315 * See the UDMAP section of the TRM for more information on this setting. 1316 * 1317 * @rx_src_tag_lo: 1318 * UDMAP receive flow source tag low byte constant configuration to be 1319 * programmed into the rx_src_tag_lo field of the flow's RFLOW_RFB register. 1320 * See the UDMAP section of the TRM for more information on this setting. 1321 * 1322 * @rx_dest_tag_hi: 1323 * UDMAP receive flow destination tag high byte constant configuration to be 1324 * programmed into the rx_dest_tag_hi field of the flow's RFLOW_RFB register. 1325 * See the UDMAP section of the TRM for more information on this setting. 1326 * 1327 * @rx_dest_tag_lo: 1328 * UDMAP receive flow destination tag low byte constant configuration to be 1329 * programmed into the rx_dest_tag_lo field of the flow's RFLOW_RFB register. 1330 * See the UDMAP section of the TRM for more information on this setting. 1331 * 1332 * @rx_src_tag_hi_sel: 1333 * UDMAP receive flow source tag high byte selector configuration to be 1334 * programmed into the rx_src_tag_hi_sel field of the RFLOW_RFC register. See 1335 * the UDMAP section of the TRM for more information on this setting. 1336 * 1337 * @rx_src_tag_lo_sel: 1338 * UDMAP receive flow source tag low byte selector configuration to be 1339 * programmed into the rx_src_tag_lo_sel field of the RFLOW_RFC register. See 1340 * the UDMAP section of the TRM for more information on this setting. 1341 * 1342 * @rx_dest_tag_hi_sel: 1343 * UDMAP receive flow destination tag high byte selector configuration to be 1344 * programmed into the rx_dest_tag_hi_sel field of the RFLOW_RFC register. See 1345 * the UDMAP section of the TRM for more information on this setting. 1346 * 1347 * @rx_dest_tag_lo_sel: 1348 * UDMAP receive flow destination tag low byte selector configuration to be 1349 * programmed into the rx_dest_tag_lo_sel field of the RFLOW_RFC register. See 1350 * the UDMAP section of the TRM for more information on this setting. 1351 * 1352 * @rx_fdq0_sz0_qnum: 1353 * UDMAP receive flow free descriptor queue 0 configuration to be programmed 1354 * into the rx_fdq0_sz0_qnum field of the flow's RFLOW_RFD register. See the 1355 * UDMAP section of the TRM for more information on this setting. The specified 1356 * free queue must be valid within the Navigator Subsystem and must be owned 1357 * by the host, or a subordinate of the host, requesting allocation and 1358 * configuration of the receive flow. 1359 * 1360 * @rx_fdq1_qnum: 1361 * UDMAP receive flow free descriptor queue 1 configuration to be programmed 1362 * into the rx_fdq1_qnum field of the flow's RFLOW_RFD register. See the 1363 * UDMAP section of the TRM for more information on this setting. The specified 1364 * free queue must be valid within the Navigator Subsystem and must be owned 1365 * by the host, or a subordinate of the host, requesting allocation and 1366 * configuration of the receive flow. 1367 * 1368 * @rx_fdq2_qnum: 1369 * UDMAP receive flow free descriptor queue 2 configuration to be programmed 1370 * into the rx_fdq2_qnum field of the flow's RFLOW_RFE register. See the 1371 * UDMAP section of the TRM for more information on this setting. The specified 1372 * free queue must be valid within the Navigator Subsystem and must be owned 1373 * by the host, or a subordinate of the host, requesting allocation and 1374 * configuration of the receive flow. 1375 * 1376 * @rx_fdq3_qnum: 1377 * UDMAP receive flow free descriptor queue 3 configuration to be programmed 1378 * into the rx_fdq3_qnum field of the flow's RFLOW_RFE register. See the 1379 * UDMAP section of the TRM for more information on this setting. The specified 1380 * free queue must be valid within the Navigator Subsystem and must be owned 1381 * by the host, or a subordinate of the host, requesting allocation and 1382 * configuration of the receive flow. 1383 * 1384 * @rx_ps_location: 1385 * UDMAP receive flow PS words location configuration to be programmed into the 1386 * rx_ps_location field of the flow's RFLOW_RFA register. 1387 */ 1388 struct ti_sci_msg_rm_udmap_flow_cfg_req { 1389 struct ti_sci_msg_hdr hdr; 1390 u32 valid_params; 1391 u16 nav_id; 1392 u16 flow_index; 1393 u8 rx_einfo_present; 1394 u8 rx_psinfo_present; 1395 u8 rx_error_handling; 1396 u8 rx_desc_type; 1397 u16 rx_sop_offset; 1398 u16 rx_dest_qnum; 1399 u8 rx_src_tag_hi; 1400 u8 rx_src_tag_lo; 1401 u8 rx_dest_tag_hi; 1402 u8 rx_dest_tag_lo; 1403 u8 rx_src_tag_hi_sel; 1404 u8 rx_src_tag_lo_sel; 1405 u8 rx_dest_tag_hi_sel; 1406 u8 rx_dest_tag_lo_sel; 1407 u16 rx_fdq0_sz0_qnum; 1408 u16 rx_fdq1_qnum; 1409 u16 rx_fdq2_qnum; 1410 u16 rx_fdq3_qnum; 1411 u8 rx_ps_location; 1412 } __packed; 1413 1414 /** 1415 * struct ti_sci_msg_req_proc_request - Request a processor 1416 * @hdr: Generic Header 1417 * @processor_id: ID of processor being requested 1418 * 1419 * Request type is TI_SCI_MSG_PROC_REQUEST, response is a generic ACK/NACK 1420 * message. 1421 */ 1422 struct ti_sci_msg_req_proc_request { 1423 struct ti_sci_msg_hdr hdr; 1424 u8 processor_id; 1425 } __packed; 1426 1427 /** 1428 * struct ti_sci_msg_req_proc_release - Release a processor 1429 * @hdr: Generic Header 1430 * @processor_id: ID of processor being released 1431 * 1432 * Request type is TI_SCI_MSG_PROC_RELEASE, response is a generic ACK/NACK 1433 * message. 1434 */ 1435 struct ti_sci_msg_req_proc_release { 1436 struct ti_sci_msg_hdr hdr; 1437 u8 processor_id; 1438 } __packed; 1439 1440 /** 1441 * struct ti_sci_msg_req_proc_handover - Handover a processor to a host 1442 * @hdr: Generic Header 1443 * @processor_id: ID of processor being handed over 1444 * @host_id: Host ID the control needs to be transferred to 1445 * 1446 * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK 1447 * message. 1448 */ 1449 struct ti_sci_msg_req_proc_handover { 1450 struct ti_sci_msg_hdr hdr; 1451 u8 processor_id; 1452 u8 host_id; 1453 } __packed; 1454 1455 /* Boot Vector masks */ 1456 #define TI_SCI_ADDR_LOW_MASK GENMASK_ULL(31, 0) 1457 #define TI_SCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32) 1458 #define TI_SCI_ADDR_HIGH_SHIFT 32 1459 1460 /** 1461 * struct ti_sci_msg_req_set_config - Set Processor boot configuration 1462 * @hdr: Generic Header 1463 * @processor_id: ID of processor being configured 1464 * @bootvector_low: Lower 32 bit address (Little Endian) of boot vector 1465 * @bootvector_high: Higher 32 bit address (Little Endian) of boot vector 1466 * @config_flags_set: Optional Processor specific Config Flags to set. 1467 * Setting a bit here implies the corresponding mode 1468 * will be set 1469 * @config_flags_clear: Optional Processor specific Config Flags to clear. 1470 * Setting a bit here implies the corresponding mode 1471 * will be cleared 1472 * 1473 * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK 1474 * message. 1475 */ 1476 struct ti_sci_msg_req_set_config { 1477 struct ti_sci_msg_hdr hdr; 1478 u8 processor_id; 1479 u32 bootvector_low; 1480 u32 bootvector_high; 1481 u32 config_flags_set; 1482 u32 config_flags_clear; 1483 } __packed; 1484 1485 /** 1486 * struct ti_sci_msg_req_set_ctrl - Set Processor boot control flags 1487 * @hdr: Generic Header 1488 * @processor_id: ID of processor being configured 1489 * @control_flags_set: Optional Processor specific Control Flags to set. 1490 * Setting a bit here implies the corresponding mode 1491 * will be set 1492 * @control_flags_clear:Optional Processor specific Control Flags to clear. 1493 * Setting a bit here implies the corresponding mode 1494 * will be cleared 1495 * 1496 * Request type is TI_SCI_MSG_SET_CTRL, response is a generic ACK/NACK 1497 * message. 1498 */ 1499 struct ti_sci_msg_req_set_ctrl { 1500 struct ti_sci_msg_hdr hdr; 1501 u8 processor_id; 1502 u32 control_flags_set; 1503 u32 control_flags_clear; 1504 } __packed; 1505 1506 /** 1507 * struct ti_sci_msg_req_get_status - Processor boot status request 1508 * @hdr: Generic Header 1509 * @processor_id: ID of processor whose status is being requested 1510 * 1511 * Request type is TI_SCI_MSG_GET_STATUS, response is an appropriate 1512 * message, or NACK in case of inability to satisfy request. 1513 */ 1514 struct ti_sci_msg_req_get_status { 1515 struct ti_sci_msg_hdr hdr; 1516 u8 processor_id; 1517 } __packed; 1518 1519 /** 1520 * struct ti_sci_msg_resp_get_status - Processor boot status response 1521 * @hdr: Generic Header 1522 * @processor_id: ID of processor whose status is returned 1523 * @bootvector_low: Lower 32 bit address (Little Endian) of boot vector 1524 * @bootvector_high: Higher 32 bit address (Little Endian) of boot vector 1525 * @config_flags: Optional Processor specific Config Flags set currently 1526 * @control_flags: Optional Processor specific Control Flags set currently 1527 * @status_flags: Optional Processor specific Status Flags set currently 1528 * 1529 * Response structure to a TI_SCI_MSG_GET_STATUS request. 1530 */ 1531 struct ti_sci_msg_resp_get_status { 1532 struct ti_sci_msg_hdr hdr; 1533 u8 processor_id; 1534 u32 bootvector_low; 1535 u32 bootvector_high; 1536 u32 config_flags; 1537 u32 control_flags; 1538 u32 status_flags; 1539 } __packed; 1540 1541 #endif /* __TI_SCI_H */ 1542