1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2010,2015,2019 The Linux Foundation. All rights reserved. 3 * Copyright (C) 2015 Linaro Ltd. 4 */ 5 6 #include <linux/arm-smccc.h> 7 #include <linux/bitfield.h> 8 #include <linux/bits.h> 9 #include <linux/cleanup.h> 10 #include <linux/clk.h> 11 #include <linux/completion.h> 12 #include <linux/cpumask.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/err.h> 15 #include <linux/export.h> 16 #include <linux/firmware/qcom/qcom_pas.h> 17 #include <linux/firmware/qcom/qcom_scm.h> 18 #include <linux/firmware/qcom/qcom_tzmem.h> 19 #include <linux/init.h> 20 #include <linux/interconnect.h> 21 #include <linux/interrupt.h> 22 #include <linux/kstrtox.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/of_address.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_platform.h> 28 #include <linux/of_reserved_mem.h> 29 #include <linux/platform_device.h> 30 #include <linux/reset-controller.h> 31 #include <linux/remoteproc.h> 32 #include <linux/sizes.h> 33 #include <linux/types.h> 34 35 #include <dt-bindings/interrupt-controller/arm-gic.h> 36 37 #include "qcom_pas.h" 38 #include "qcom_scm.h" 39 #include "qcom_tzmem.h" 40 41 static u32 download_mode; 42 43 #define GIC_SPI_BASE 32 44 #define GIC_MAX_SPI 1019 // SPIs in GICv3 spec range from 32..1019 45 #define GIC_ESPI_BASE 4096 46 #define GIC_MAX_ESPI 5119 // ESPIs in GICv3 spec range from 4096..5119 47 48 struct qcom_scm { 49 struct device *dev; 50 struct clk *core_clk; 51 struct clk *iface_clk; 52 struct clk *bus_clk; 53 struct icc_path *path; 54 struct completion *waitq_comps; 55 struct reset_controller_dev reset; 56 57 /* control access to the interconnect path */ 58 struct mutex scm_bw_lock; 59 int scm_vote_count; 60 61 u64 dload_mode_addr; 62 63 struct qcom_tzmem_pool *mempool; 64 unsigned int wq_cnt; 65 }; 66 67 struct qcom_scm_current_perm_info { 68 __le32 vmid; 69 __le32 perm; 70 __le64 ctx; 71 __le32 ctx_size; 72 __le32 unused; 73 }; 74 75 struct qcom_scm_mem_map_info { 76 __le64 mem_addr; 77 __le64 mem_size; 78 }; 79 80 /** 81 * struct qcom_scm_qseecom_resp - QSEECOM SCM call response. 82 * @result: Result or status of the SCM call. See &enum qcom_scm_qseecom_result. 83 * @resp_type: Type of the response. See &enum qcom_scm_qseecom_resp_type. 84 * @data: Response data. The type of this data is given in @resp_type. 85 */ 86 struct qcom_scm_qseecom_resp { 87 u64 result; 88 u64 resp_type; 89 u64 data; 90 }; 91 92 enum qcom_scm_qseecom_result { 93 QSEECOM_RESULT_SUCCESS = 0, 94 QSEECOM_RESULT_INCOMPLETE = 1, 95 QSEECOM_RESULT_BLOCKED_ON_LISTENER = 2, 96 QSEECOM_RESULT_FAILURE = 0xFFFFFFFF, 97 }; 98 99 enum qcom_scm_qseecom_resp_type { 100 QSEECOM_SCM_RES_APP_ID = 0xEE01, 101 QSEECOM_SCM_RES_QSEOS_LISTENER_ID = 0xEE02, 102 }; 103 104 enum qcom_scm_qseecom_tz_owner { 105 QSEECOM_TZ_OWNER_SIP = 2, 106 QSEECOM_TZ_OWNER_TZ_APPS = 48, 107 QSEECOM_TZ_OWNER_QSEE_OS = 50 108 }; 109 110 enum qcom_scm_qseecom_tz_svc { 111 QSEECOM_TZ_SVC_APP_ID_PLACEHOLDER = 0, 112 QSEECOM_TZ_SVC_APP_MGR = 1, 113 QSEECOM_TZ_SVC_INFO = 6, 114 }; 115 116 enum qcom_scm_qseecom_tz_cmd_app { 117 QSEECOM_TZ_CMD_APP_SEND = 1, 118 QSEECOM_TZ_CMD_APP_LOOKUP = 3, 119 }; 120 121 enum qcom_scm_qseecom_tz_cmd_info { 122 QSEECOM_TZ_CMD_INFO_VERSION = 3, 123 }; 124 125 #define RSCTABLE_BUFFER_NOT_SUFFICIENT 20 126 127 #define QSEECOM_MAX_APP_NAME_SIZE 64 128 #define SHMBRIDGE_RESULT_NOTSUPP 4 129 130 /* Each bit configures cold/warm boot address for one of the 4 CPUs */ 131 static const u8 qcom_scm_cpu_cold_bits[QCOM_SCM_BOOT_MAX_CPUS] = { 132 0, BIT(0), BIT(3), BIT(5) 133 }; 134 static const u8 qcom_scm_cpu_warm_bits[QCOM_SCM_BOOT_MAX_CPUS] = { 135 BIT(2), BIT(1), BIT(4), BIT(6) 136 }; 137 138 #define QCOM_SMC_WAITQ_FLAG_WAKE_ONE BIT(0) 139 140 #define QCOM_DLOAD_MASK GENMASK(5, 4) 141 #define QCOM_DLOAD_NODUMP 0 142 #define QCOM_DLOAD_FULLDUMP 1 143 #define QCOM_DLOAD_MINIDUMP 2 144 #define QCOM_DLOAD_BOTHDUMP 3 145 146 #define QCOM_SCM_DEFAULT_WAITQ_COUNT 1 147 148 static const char * const qcom_scm_convention_names[] = { 149 [SMC_CONVENTION_UNKNOWN] = "unknown", 150 [SMC_CONVENTION_ARM_32] = "smc arm 32", 151 [SMC_CONVENTION_ARM_64] = "smc arm 64", 152 [SMC_CONVENTION_LEGACY] = "smc legacy", 153 }; 154 155 static const char * const download_mode_name[] = { 156 [QCOM_DLOAD_NODUMP] = "off", 157 [QCOM_DLOAD_FULLDUMP] = "full", 158 [QCOM_DLOAD_MINIDUMP] = "mini", 159 [QCOM_DLOAD_BOTHDUMP] = "full,mini", 160 }; 161 162 static struct qcom_scm *__scm; 163 164 static int qcom_scm_clk_enable(void) 165 { 166 int ret; 167 168 ret = clk_prepare_enable(__scm->core_clk); 169 if (ret) 170 goto bail; 171 172 ret = clk_prepare_enable(__scm->iface_clk); 173 if (ret) 174 goto disable_core; 175 176 ret = clk_prepare_enable(__scm->bus_clk); 177 if (ret) 178 goto disable_iface; 179 180 return 0; 181 182 disable_iface: 183 clk_disable_unprepare(__scm->iface_clk); 184 disable_core: 185 clk_disable_unprepare(__scm->core_clk); 186 bail: 187 return ret; 188 } 189 190 static void qcom_scm_clk_disable(void) 191 { 192 clk_disable_unprepare(__scm->core_clk); 193 clk_disable_unprepare(__scm->iface_clk); 194 clk_disable_unprepare(__scm->bus_clk); 195 } 196 197 static int qcom_scm_bw_enable(void) 198 { 199 int ret = 0; 200 201 if (!__scm->path) 202 return 0; 203 204 guard(mutex)(&__scm->scm_bw_lock); 205 206 if (!__scm->scm_vote_count) { 207 ret = icc_set_bw(__scm->path, 0, UINT_MAX); 208 if (ret < 0) { 209 dev_err(__scm->dev, "failed to set bandwidth request\n"); 210 return ret; 211 } 212 } 213 __scm->scm_vote_count++; 214 215 return 0; 216 } 217 218 static void qcom_scm_bw_disable(void) 219 { 220 if (!__scm->path) 221 return; 222 223 mutex_lock(&__scm->scm_bw_lock); 224 if (__scm->scm_vote_count-- == 1) 225 icc_set_bw(__scm->path, 0, 0); 226 mutex_unlock(&__scm->scm_bw_lock); 227 } 228 229 enum qcom_scm_convention qcom_scm_convention = SMC_CONVENTION_UNKNOWN; 230 static DEFINE_SPINLOCK(scm_query_lock); 231 232 struct qcom_tzmem_pool *qcom_scm_get_tzmem_pool(void) 233 { 234 if (!qcom_scm_is_available()) 235 return NULL; 236 237 return __scm->mempool; 238 } 239 240 static enum qcom_scm_convention __get_convention(void) 241 { 242 unsigned long flags; 243 struct qcom_scm_desc desc = { 244 .svc = QCOM_SCM_SVC_INFO, 245 .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL, 246 .args[0] = SCM_SMC_FNID(QCOM_SCM_SVC_INFO, 247 QCOM_SCM_INFO_IS_CALL_AVAIL) | 248 (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT), 249 .arginfo = QCOM_SCM_ARGS(1), 250 .owner = ARM_SMCCC_OWNER_SIP, 251 }; 252 struct qcom_scm_res res; 253 enum qcom_scm_convention probed_convention; 254 int ret; 255 bool forced = false; 256 257 if (likely(qcom_scm_convention != SMC_CONVENTION_UNKNOWN)) 258 return qcom_scm_convention; 259 260 /* 261 * Per the "SMC calling convention specification", the 64-bit calling 262 * convention can only be used when the client is 64-bit, otherwise 263 * system will encounter the undefined behaviour. 264 */ 265 #if IS_ENABLED(CONFIG_ARM64) 266 /* 267 * Device isn't required as there is only one argument - no device 268 * needed to dma_map_single to secure world 269 */ 270 probed_convention = SMC_CONVENTION_ARM_64; 271 ret = __scm_smc_call(NULL, &desc, probed_convention, &res, true); 272 if (!ret && res.result[0] == 1) 273 goto found; 274 275 /* 276 * Some SC7180 firmwares didn't implement the 277 * QCOM_SCM_INFO_IS_CALL_AVAIL call, so we fallback to forcing ARM_64 278 * calling conventions on these firmwares. Luckily we don't make any 279 * early calls into the firmware on these SoCs so the device pointer 280 * will be valid here to check if the compatible matches. 281 */ 282 if (of_device_is_compatible(__scm ? __scm->dev->of_node : NULL, "qcom,scm-sc7180")) { 283 forced = true; 284 goto found; 285 } 286 #endif 287 288 probed_convention = SMC_CONVENTION_ARM_32; 289 ret = __scm_smc_call(NULL, &desc, probed_convention, &res, true); 290 if (!ret && res.result[0] == 1) 291 goto found; 292 293 probed_convention = SMC_CONVENTION_LEGACY; 294 found: 295 spin_lock_irqsave(&scm_query_lock, flags); 296 if (probed_convention != qcom_scm_convention) { 297 qcom_scm_convention = probed_convention; 298 pr_info("qcom_scm: convention: %s%s\n", 299 qcom_scm_convention_names[qcom_scm_convention], 300 forced ? " (forced)" : ""); 301 } 302 spin_unlock_irqrestore(&scm_query_lock, flags); 303 304 return qcom_scm_convention; 305 } 306 307 /** 308 * qcom_scm_call() - Invoke a syscall in the secure world 309 * @dev: device 310 * @desc: Descriptor structure containing arguments and return values 311 * @res: Structure containing results from SMC/HVC call 312 * 313 * Sends a command to the SCM and waits for the command to finish processing. 314 * This should *only* be called in pre-emptible context. 315 */ 316 static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc, 317 struct qcom_scm_res *res) 318 { 319 might_sleep(); 320 switch (__get_convention()) { 321 case SMC_CONVENTION_ARM_32: 322 case SMC_CONVENTION_ARM_64: 323 return scm_smc_call(dev, desc, res, false); 324 case SMC_CONVENTION_LEGACY: 325 return scm_legacy_call(dev, desc, res); 326 default: 327 pr_err("Unknown current SCM calling convention.\n"); 328 return -EINVAL; 329 } 330 } 331 332 /** 333 * qcom_scm_call_atomic() - atomic variation of qcom_scm_call() 334 * @dev: device 335 * @desc: Descriptor structure containing arguments and return values 336 * @res: Structure containing results from SMC/HVC call 337 * 338 * Sends a command to the SCM and waits for the command to finish processing. 339 * This can be called in atomic context. 340 */ 341 static int qcom_scm_call_atomic(struct device *dev, 342 const struct qcom_scm_desc *desc, 343 struct qcom_scm_res *res) 344 { 345 switch (__get_convention()) { 346 case SMC_CONVENTION_ARM_32: 347 case SMC_CONVENTION_ARM_64: 348 return scm_smc_call(dev, desc, res, true); 349 case SMC_CONVENTION_LEGACY: 350 return scm_legacy_call_atomic(dev, desc, res); 351 default: 352 pr_err("Unknown current SCM calling convention.\n"); 353 return -EINVAL; 354 } 355 } 356 357 static bool __qcom_scm_is_call_available(struct device *dev, u32 svc_id, 358 u32 cmd_id) 359 { 360 int ret; 361 struct qcom_scm_desc desc = { 362 .svc = QCOM_SCM_SVC_INFO, 363 .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL, 364 .owner = ARM_SMCCC_OWNER_SIP, 365 }; 366 struct qcom_scm_res res; 367 368 desc.arginfo = QCOM_SCM_ARGS(1); 369 switch (__get_convention()) { 370 case SMC_CONVENTION_ARM_32: 371 case SMC_CONVENTION_ARM_64: 372 desc.args[0] = SCM_SMC_FNID(svc_id, cmd_id) | 373 (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT); 374 break; 375 case SMC_CONVENTION_LEGACY: 376 desc.args[0] = SCM_LEGACY_FNID(svc_id, cmd_id); 377 break; 378 default: 379 pr_err("Unknown SMC convention being used\n"); 380 return false; 381 } 382 383 ret = qcom_scm_call(dev, &desc, &res); 384 385 return ret ? false : !!res.result[0]; 386 } 387 388 static int qcom_scm_set_boot_addr(void *entry, const u8 *cpu_bits) 389 { 390 int cpu; 391 unsigned int flags = 0; 392 struct qcom_scm_desc desc = { 393 .svc = QCOM_SCM_SVC_BOOT, 394 .cmd = QCOM_SCM_BOOT_SET_ADDR, 395 .arginfo = QCOM_SCM_ARGS(2), 396 .owner = ARM_SMCCC_OWNER_SIP, 397 }; 398 399 for_each_present_cpu(cpu) { 400 if (cpu >= QCOM_SCM_BOOT_MAX_CPUS) 401 return -EINVAL; 402 flags |= cpu_bits[cpu]; 403 } 404 405 desc.args[0] = flags; 406 desc.args[1] = virt_to_phys(entry); 407 408 return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL); 409 } 410 411 static int qcom_scm_set_boot_addr_mc(void *entry, unsigned int flags) 412 { 413 struct qcom_scm_desc desc = { 414 .svc = QCOM_SCM_SVC_BOOT, 415 .cmd = QCOM_SCM_BOOT_SET_ADDR_MC, 416 .owner = ARM_SMCCC_OWNER_SIP, 417 .arginfo = QCOM_SCM_ARGS(6), 418 .args = { 419 virt_to_phys(entry), 420 /* Apply to all CPUs in all affinity levels */ 421 ~0ULL, ~0ULL, ~0ULL, ~0ULL, 422 flags, 423 }, 424 }; 425 426 /* Need a device for DMA of the additional arguments */ 427 if (!__scm || __get_convention() == SMC_CONVENTION_LEGACY) 428 return -EOPNOTSUPP; 429 430 return qcom_scm_call(__scm->dev, &desc, NULL); 431 } 432 433 /** 434 * qcom_scm_set_warm_boot_addr() - Set the warm boot address for all cpus 435 * @entry: Entry point function for the cpus 436 * 437 * Set the Linux entry point for the SCM to transfer control to when coming 438 * out of a power down. CPU power down may be executed on cpuidle or hotplug. 439 */ 440 int qcom_scm_set_warm_boot_addr(void *entry) 441 { 442 if (qcom_scm_set_boot_addr_mc(entry, QCOM_SCM_BOOT_MC_FLAG_WARMBOOT)) 443 /* Fallback to old SCM call */ 444 return qcom_scm_set_boot_addr(entry, qcom_scm_cpu_warm_bits); 445 return 0; 446 } 447 EXPORT_SYMBOL_GPL(qcom_scm_set_warm_boot_addr); 448 449 /** 450 * qcom_scm_set_cold_boot_addr() - Set the cold boot address for all cpus 451 * @entry: Entry point function for the cpus 452 */ 453 int qcom_scm_set_cold_boot_addr(void *entry) 454 { 455 if (qcom_scm_set_boot_addr_mc(entry, QCOM_SCM_BOOT_MC_FLAG_COLDBOOT)) 456 /* Fallback to old SCM call */ 457 return qcom_scm_set_boot_addr(entry, qcom_scm_cpu_cold_bits); 458 return 0; 459 } 460 EXPORT_SYMBOL_GPL(qcom_scm_set_cold_boot_addr); 461 462 /** 463 * qcom_scm_cpu_power_down() - Power down the cpu 464 * @flags: Flags to flush cache 465 * 466 * This is an end point to power down cpu. If there was a pending interrupt, 467 * the control would return from this function, otherwise, the cpu jumps to the 468 * warm boot entry point set for this cpu upon reset. 469 */ 470 void qcom_scm_cpu_power_down(u32 flags) 471 { 472 struct qcom_scm_desc desc = { 473 .svc = QCOM_SCM_SVC_BOOT, 474 .cmd = QCOM_SCM_BOOT_TERMINATE_PC, 475 .args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK, 476 .arginfo = QCOM_SCM_ARGS(1), 477 .owner = ARM_SMCCC_OWNER_SIP, 478 }; 479 480 qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL); 481 } 482 EXPORT_SYMBOL_GPL(qcom_scm_cpu_power_down); 483 484 static int qcom_scm_disable_sdi(void) 485 { 486 int ret; 487 struct qcom_scm_desc desc = { 488 .svc = QCOM_SCM_SVC_BOOT, 489 .cmd = QCOM_SCM_BOOT_SDI_CONFIG, 490 .args[0] = 1, /* Disable watchdog debug */ 491 .args[1] = 0, /* Disable SDI */ 492 .arginfo = QCOM_SCM_ARGS(2), 493 .owner = ARM_SMCCC_OWNER_SIP, 494 }; 495 struct qcom_scm_res res; 496 497 ret = qcom_scm_clk_enable(); 498 if (ret) 499 return ret; 500 ret = qcom_scm_call(__scm->dev, &desc, &res); 501 502 qcom_scm_clk_disable(); 503 504 return ret ? : res.result[0]; 505 } 506 507 static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) 508 { 509 struct qcom_scm_desc desc = { 510 .svc = QCOM_SCM_SVC_BOOT, 511 .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE, 512 .arginfo = QCOM_SCM_ARGS(2), 513 .args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE, 514 .owner = ARM_SMCCC_OWNER_SIP, 515 }; 516 517 desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0; 518 519 return qcom_scm_call_atomic(__scm->dev, &desc, NULL); 520 } 521 522 static int qcom_scm_io_rmw(phys_addr_t addr, unsigned int mask, unsigned int val) 523 { 524 unsigned int old; 525 unsigned int new; 526 int ret; 527 528 ret = qcom_scm_io_readl(addr, &old); 529 if (ret) 530 return ret; 531 532 new = (old & ~mask) | (val & mask); 533 534 return qcom_scm_io_writel(addr, new); 535 } 536 537 static void qcom_scm_set_download_mode(u32 dload_mode) 538 { 539 int ret = 0; 540 541 if (__scm->dload_mode_addr) { 542 ret = qcom_scm_io_rmw(__scm->dload_mode_addr, QCOM_DLOAD_MASK, 543 FIELD_PREP(QCOM_DLOAD_MASK, dload_mode)); 544 } else if (__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_BOOT, 545 QCOM_SCM_BOOT_SET_DLOAD_MODE)) { 546 ret = __qcom_scm_set_dload_mode(__scm->dev, !!dload_mode); 547 } else if (dload_mode) { 548 dev_err(__scm->dev, 549 "No available mechanism for setting download mode\n"); 550 } 551 552 if (ret) 553 dev_err(__scm->dev, "failed to set download mode: %d\n", ret); 554 } 555 556 struct qcom_scm_pas_context *devm_qcom_scm_pas_context_alloc(struct device *dev, 557 u32 pas_id, 558 phys_addr_t mem_phys, 559 size_t mem_size) 560 { 561 struct qcom_pas_context *ctx; 562 563 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 564 if (!ctx) 565 return ERR_PTR(-ENOMEM); 566 567 ctx->dev = dev; 568 ctx->pas_id = pas_id; 569 ctx->mem_phys = mem_phys; 570 ctx->mem_size = mem_size; 571 572 return (struct qcom_scm_pas_context *)ctx; 573 } 574 EXPORT_SYMBOL_GPL(devm_qcom_scm_pas_context_alloc); 575 576 static int __qcom_scm_pas_init_image(struct device *dev, u32 pas_id, 577 dma_addr_t mdata_phys, 578 struct qcom_scm_res *res) 579 { 580 struct qcom_scm_desc desc = { 581 .svc = QCOM_SCM_SVC_PIL, 582 .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE, 583 .arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW), 584 .args[0] = pas_id, 585 .owner = ARM_SMCCC_OWNER_SIP, 586 }; 587 int ret; 588 589 ret = qcom_scm_clk_enable(); 590 if (ret) 591 return ret; 592 593 ret = qcom_scm_bw_enable(); 594 if (ret) 595 goto disable_clk; 596 597 desc.args[1] = mdata_phys; 598 599 ret = qcom_scm_call(dev, &desc, res); 600 qcom_scm_bw_disable(); 601 602 disable_clk: 603 qcom_scm_clk_disable(); 604 605 return ret; 606 } 607 608 static int qcom_scm_pas_prep_and_init_image(struct device *dev, 609 struct qcom_pas_context *ctx, 610 const void *metadata, size_t size) 611 { 612 struct qcom_scm_res res; 613 phys_addr_t mdata_phys; 614 void *mdata_buf; 615 int ret; 616 617 mdata_buf = qcom_tzmem_alloc(__scm->mempool, size, GFP_KERNEL); 618 if (!mdata_buf) 619 return -ENOMEM; 620 621 memcpy(mdata_buf, metadata, size); 622 mdata_phys = qcom_tzmem_to_phys(mdata_buf); 623 624 ret = __qcom_scm_pas_init_image(dev, ctx->pas_id, mdata_phys, &res); 625 if (ret < 0) 626 qcom_tzmem_free(mdata_buf); 627 else 628 ctx->ptr = mdata_buf; 629 630 return ret ? : res.result[0]; 631 } 632 633 static int __qcom_scm_pas_init_image2(struct device *dev, u32 pas_id, 634 const void *metadata, size_t size, 635 struct qcom_pas_context *ctx) 636 { 637 struct qcom_scm_res res; 638 dma_addr_t mdata_phys; 639 void *mdata_buf; 640 int ret; 641 642 if (ctx && ctx->use_tzmem) 643 return qcom_scm_pas_prep_and_init_image(dev, ctx, metadata, size); 644 645 /* 646 * During the scm call memory protection will be enabled for the meta 647 * data blob, so make sure it's physically contiguous, 4K aligned and 648 * non-cachable to avoid XPU violations. 649 * 650 * For PIL calls the hypervisor creates SHM Bridges for the blob 651 * buffers on behalf of Linux so we must not do it ourselves hence 652 * not using the TZMem allocator here. 653 * 654 * If we pass a buffer that is already part of an SHM Bridge to this 655 * call, it will fail. 656 */ 657 mdata_buf = dma_alloc_coherent(dev, size, &mdata_phys, GFP_KERNEL); 658 if (!mdata_buf) 659 return -ENOMEM; 660 661 memcpy(mdata_buf, metadata, size); 662 663 ret = __qcom_scm_pas_init_image(dev, pas_id, mdata_phys, &res); 664 if (ret < 0 || !ctx) { 665 dma_free_coherent(dev, size, mdata_buf, mdata_phys); 666 } else if (ctx) { 667 ctx->ptr = mdata_buf; 668 ctx->phys = mdata_phys; 669 ctx->size = size; 670 } 671 672 return ret ? : res.result[0]; 673 } 674 675 int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size, 676 struct qcom_scm_pas_context *ctx) 677 { 678 return __qcom_scm_pas_init_image2(__scm->dev, pas_id, metadata, size, 679 (struct qcom_pas_context *)ctx); 680 } 681 EXPORT_SYMBOL_GPL(qcom_scm_pas_init_image); 682 683 static void __qcom_scm_pas_metadata_release(struct device *dev, 684 struct qcom_pas_context *ctx) 685 { 686 if (ctx->use_tzmem) 687 qcom_tzmem_free(ctx->ptr); 688 else 689 dma_free_coherent(dev, ctx->size, ctx->ptr, ctx->phys); 690 691 ctx->ptr = NULL; 692 } 693 694 void qcom_scm_pas_metadata_release(struct qcom_scm_pas_context *ctx) 695 { 696 __qcom_scm_pas_metadata_release(__scm->dev, 697 (struct qcom_pas_context *)ctx); 698 } 699 EXPORT_SYMBOL_GPL(qcom_scm_pas_metadata_release); 700 701 static int __qcom_scm_pas_mem_setup(struct device *dev, u32 pas_id, 702 phys_addr_t addr, phys_addr_t size) 703 { 704 int ret; 705 struct qcom_scm_desc desc = { 706 .svc = QCOM_SCM_SVC_PIL, 707 .cmd = QCOM_SCM_PIL_PAS_MEM_SETUP, 708 .arginfo = QCOM_SCM_ARGS(3), 709 .args[0] = pas_id, 710 .args[1] = addr, 711 .args[2] = size, 712 .owner = ARM_SMCCC_OWNER_SIP, 713 }; 714 struct qcom_scm_res res; 715 716 ret = qcom_scm_clk_enable(); 717 if (ret) 718 return ret; 719 720 ret = qcom_scm_bw_enable(); 721 if (ret) 722 goto disable_clk; 723 724 ret = qcom_scm_call(dev, &desc, &res); 725 qcom_scm_bw_disable(); 726 727 disable_clk: 728 qcom_scm_clk_disable(); 729 730 return ret ? : res.result[0]; 731 } 732 733 int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size) 734 { 735 return __qcom_scm_pas_mem_setup(__scm->dev, pas_id, addr, size); 736 } 737 EXPORT_SYMBOL_GPL(qcom_scm_pas_mem_setup); 738 739 static void *__qcom_scm_pas_get_rsc_table(struct device *dev, u32 pas_id, 740 void *input_rt_tzm, 741 size_t input_rt_size, 742 size_t *output_rt_size) 743 { 744 struct qcom_scm_desc desc = { 745 .svc = QCOM_SCM_SVC_PIL, 746 .cmd = QCOM_SCM_PIL_PAS_GET_RSCTABLE, 747 .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_VAL, QCOM_SCM_RO, QCOM_SCM_VAL, 748 QCOM_SCM_RW, QCOM_SCM_VAL), 749 .args[0] = pas_id, 750 .owner = ARM_SMCCC_OWNER_SIP, 751 }; 752 struct qcom_scm_res res; 753 void *output_rt_tzm; 754 int ret; 755 756 output_rt_tzm = qcom_tzmem_alloc(__scm->mempool, *output_rt_size, GFP_KERNEL); 757 if (!output_rt_tzm) 758 return ERR_PTR(-ENOMEM); 759 760 desc.args[1] = qcom_tzmem_to_phys(input_rt_tzm); 761 desc.args[2] = input_rt_size; 762 desc.args[3] = qcom_tzmem_to_phys(output_rt_tzm); 763 desc.args[4] = *output_rt_size; 764 765 /* 766 * Whether SMC fail or pass, res.result[2] will hold actual resource table 767 * size. 768 * 769 * If passed 'output_rt_size' buffer size is not sufficient to hold the 770 * resource table TrustZone sends, response code in res.result[1] as 771 * RSCTABLE_BUFFER_NOT_SUFFICIENT so that caller can retry this SMC call 772 * with output_rt_tzm buffer with res.result[2] size however, It should not 773 * be of unresonable size. 774 */ 775 ret = qcom_scm_call(dev, &desc, &res); 776 if (!ret && res.result[2] > SZ_1G) { 777 ret = -E2BIG; 778 goto free_output_rt; 779 } 780 781 *output_rt_size = res.result[2]; 782 if (ret && res.result[1] == RSCTABLE_BUFFER_NOT_SUFFICIENT) 783 ret = -EOVERFLOW; 784 785 free_output_rt: 786 if (ret) 787 qcom_tzmem_free(output_rt_tzm); 788 789 return ret ? ERR_PTR(ret) : output_rt_tzm; 790 } 791 792 static void *__qcom_scm_pas_get_rsc_table2(struct device *dev, 793 struct qcom_pas_context *ctx, 794 void *input_rt, 795 size_t input_rt_size, 796 size_t *output_rt_size) 797 { 798 struct resource_table empty_rsc = {}; 799 size_t size = SZ_16K; 800 void *output_rt_tzm; 801 void *input_rt_tzm; 802 void *tbl_ptr; 803 int ret; 804 805 ret = qcom_scm_clk_enable(); 806 if (ret) 807 return ERR_PTR(ret); 808 809 ret = qcom_scm_bw_enable(); 810 if (ret) 811 goto disable_clk; 812 813 /* 814 * TrustZone can not accept buffer as NULL value as argument hence, 815 * we need to pass a input buffer indicating that subsystem firmware 816 * does not have resource table by filling resource table structure. 817 */ 818 if (!input_rt) { 819 input_rt = &empty_rsc; 820 input_rt_size = sizeof(empty_rsc); 821 } 822 823 input_rt_tzm = qcom_tzmem_alloc(__scm->mempool, input_rt_size, GFP_KERNEL); 824 if (!input_rt_tzm) { 825 ret = -ENOMEM; 826 goto disable_scm_bw; 827 } 828 829 memcpy(input_rt_tzm, input_rt, input_rt_size); 830 831 output_rt_tzm = __qcom_scm_pas_get_rsc_table(dev, ctx->pas_id, 832 input_rt_tzm, 833 input_rt_size, &size); 834 if (PTR_ERR(output_rt_tzm) == -EOVERFLOW) 835 /* Try again with the size requested by the TZ */ 836 output_rt_tzm = __qcom_scm_pas_get_rsc_table(dev, ctx->pas_id, 837 input_rt_tzm, 838 input_rt_size, 839 &size); 840 if (IS_ERR(output_rt_tzm)) { 841 ret = PTR_ERR(output_rt_tzm); 842 goto free_input_rt; 843 } 844 845 tbl_ptr = kmemdup(output_rt_tzm, size, GFP_KERNEL); 846 if (!tbl_ptr) { 847 qcom_tzmem_free(output_rt_tzm); 848 ret = -ENOMEM; 849 goto free_input_rt; 850 } 851 852 *output_rt_size = size; 853 qcom_tzmem_free(output_rt_tzm); 854 855 free_input_rt: 856 qcom_tzmem_free(input_rt_tzm); 857 858 disable_scm_bw: 859 qcom_scm_bw_disable(); 860 861 disable_clk: 862 qcom_scm_clk_disable(); 863 864 return ret ? ERR_PTR(ret) : tbl_ptr; 865 } 866 867 struct resource_table *qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_context *ctx, 868 void *input_rt, 869 size_t input_rt_size, 870 size_t *output_rt_size) 871 { 872 return __qcom_scm_pas_get_rsc_table2(__scm->dev, 873 (struct qcom_pas_context *)ctx, 874 input_rt, input_rt_size, 875 output_rt_size); 876 } 877 EXPORT_SYMBOL_GPL(qcom_scm_pas_get_rsc_table); 878 879 static int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 pas_id) 880 { 881 int ret; 882 struct qcom_scm_desc desc = { 883 .svc = QCOM_SCM_SVC_PIL, 884 .cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET, 885 .arginfo = QCOM_SCM_ARGS(1), 886 .args[0] = pas_id, 887 .owner = ARM_SMCCC_OWNER_SIP, 888 }; 889 struct qcom_scm_res res; 890 891 ret = qcom_scm_clk_enable(); 892 if (ret) 893 return ret; 894 895 ret = qcom_scm_bw_enable(); 896 if (ret) 897 goto disable_clk; 898 899 ret = qcom_scm_call(dev, &desc, &res); 900 qcom_scm_bw_disable(); 901 902 disable_clk: 903 qcom_scm_clk_disable(); 904 905 return ret ? : res.result[0]; 906 } 907 908 int qcom_scm_pas_auth_and_reset(u32 pas_id) 909 { 910 return __qcom_scm_pas_auth_and_reset(__scm->dev, pas_id); 911 } 912 EXPORT_SYMBOL_GPL(qcom_scm_pas_auth_and_reset); 913 914 static int __qcom_scm_pas_prepare_and_auth_reset(struct device *dev, 915 struct qcom_pas_context *ctx) 916 { 917 u64 handle; 918 int ret; 919 920 /* 921 * When Linux running @ EL1, Gunyah hypervisor running @ EL2 traps the 922 * auth_and_reset call and create an shmbridge on the remote subsystem 923 * memory region and then invokes a call to TrustZone to authenticate. 924 */ 925 if (!ctx->use_tzmem) 926 return __qcom_scm_pas_auth_and_reset(dev, ctx->pas_id); 927 928 /* 929 * When Linux runs @ EL2 Linux must create the shmbridge itself and then 930 * subsequently call TrustZone for authenticate and reset. 931 */ 932 ret = qcom_tzmem_shm_bridge_create(ctx->mem_phys, ctx->mem_size, &handle); 933 if (ret) 934 return ret; 935 936 ret = __qcom_scm_pas_auth_and_reset(dev, ctx->pas_id); 937 qcom_tzmem_shm_bridge_delete(handle); 938 939 return ret; 940 } 941 942 int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_context *ctx) 943 { 944 return __qcom_scm_pas_prepare_and_auth_reset(__scm->dev, 945 (struct qcom_pas_context *)ctx); 946 } 947 EXPORT_SYMBOL_GPL(qcom_scm_pas_prepare_and_auth_reset); 948 949 static int __qcom_scm_pas_set_remote_state(struct device *dev, u32 state, 950 u32 pas_id) 951 { 952 struct qcom_scm_desc desc = { 953 .svc = QCOM_SCM_SVC_BOOT, 954 .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE, 955 .arginfo = QCOM_SCM_ARGS(2), 956 .args[0] = state, 957 .args[1] = pas_id, 958 .owner = ARM_SMCCC_OWNER_SIP, 959 }; 960 struct qcom_scm_res res; 961 int ret; 962 963 ret = qcom_scm_call(dev, &desc, &res); 964 965 return ret ? : res.result[0]; 966 } 967 968 int qcom_scm_set_remote_state(u32 state, u32 id) 969 { 970 return __qcom_scm_pas_set_remote_state(__scm->dev, state, id); 971 } 972 EXPORT_SYMBOL_GPL(qcom_scm_set_remote_state); 973 974 static int __qcom_scm_pas_shutdown(struct device *dev, u32 pas_id) 975 { 976 int ret; 977 struct qcom_scm_desc desc = { 978 .svc = QCOM_SCM_SVC_PIL, 979 .cmd = QCOM_SCM_PIL_PAS_SHUTDOWN, 980 .arginfo = QCOM_SCM_ARGS(1), 981 .args[0] = pas_id, 982 .owner = ARM_SMCCC_OWNER_SIP, 983 }; 984 struct qcom_scm_res res; 985 986 ret = qcom_scm_clk_enable(); 987 if (ret) 988 return ret; 989 990 ret = qcom_scm_bw_enable(); 991 if (ret) 992 goto disable_clk; 993 994 ret = qcom_scm_call(dev, &desc, &res); 995 qcom_scm_bw_disable(); 996 997 disable_clk: 998 qcom_scm_clk_disable(); 999 1000 return ret ? : res.result[0]; 1001 } 1002 1003 int qcom_scm_pas_shutdown(u32 pas_id) 1004 { 1005 return __qcom_scm_pas_shutdown(__scm->dev, pas_id); 1006 } 1007 EXPORT_SYMBOL_GPL(qcom_scm_pas_shutdown); 1008 1009 static bool __qcom_scm_pas_supported(struct device *dev, u32 pas_id) 1010 { 1011 int ret; 1012 struct qcom_scm_desc desc = { 1013 .svc = QCOM_SCM_SVC_PIL, 1014 .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED, 1015 .arginfo = QCOM_SCM_ARGS(1), 1016 .args[0] = pas_id, 1017 .owner = ARM_SMCCC_OWNER_SIP, 1018 }; 1019 struct qcom_scm_res res; 1020 1021 if (!__qcom_scm_is_call_available(dev, QCOM_SCM_SVC_PIL, 1022 QCOM_SCM_PIL_PAS_IS_SUPPORTED)) 1023 return false; 1024 1025 ret = qcom_scm_call(dev, &desc, &res); 1026 1027 return ret ? false : !!res.result[0]; 1028 } 1029 1030 bool qcom_scm_pas_supported(u32 pas_id) 1031 { 1032 return __qcom_scm_pas_supported(__scm->dev, pas_id); 1033 } 1034 EXPORT_SYMBOL_GPL(qcom_scm_pas_supported); 1035 1036 static struct qcom_pas_ops qcom_pas_ops_scm = { 1037 .drv_name = "qcom_scm", 1038 .supported = __qcom_scm_pas_supported, 1039 .init_image = __qcom_scm_pas_init_image2, 1040 .mem_setup = __qcom_scm_pas_mem_setup, 1041 .get_rsc_table = __qcom_scm_pas_get_rsc_table2, 1042 .auth_and_reset = __qcom_scm_pas_auth_and_reset, 1043 .prepare_and_auth_reset = __qcom_scm_pas_prepare_and_auth_reset, 1044 .set_remote_state = __qcom_scm_pas_set_remote_state, 1045 .shutdown = __qcom_scm_pas_shutdown, 1046 .metadata_release = __qcom_scm_pas_metadata_release, 1047 }; 1048 1049 /** 1050 * qcom_scm_is_pas_available() - Check if the peripheral authentication service 1051 * is available via SCM or not 1052 * 1053 * Returns true if PAS is available, otherwise false. 1054 */ 1055 static bool qcom_scm_is_pas_available(void) 1056 { 1057 if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL, 1058 QCOM_SCM_PIL_PAS_AUTH_AND_RESET)) 1059 return false; 1060 1061 return true; 1062 } 1063 1064 static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) 1065 { 1066 struct qcom_scm_desc desc = { 1067 .svc = QCOM_SCM_SVC_PIL, 1068 .cmd = QCOM_SCM_PIL_PAS_MSS_RESET, 1069 .arginfo = QCOM_SCM_ARGS(2), 1070 .args[0] = reset, 1071 .args[1] = 0, 1072 .owner = ARM_SMCCC_OWNER_SIP, 1073 }; 1074 struct qcom_scm_res res; 1075 int ret; 1076 1077 ret = qcom_scm_call(__scm->dev, &desc, &res); 1078 1079 return ret ? : res.result[0]; 1080 } 1081 1082 static int qcom_scm_pas_reset_assert(struct reset_controller_dev *rcdev, 1083 unsigned long idx) 1084 { 1085 if (idx != 0) 1086 return -EINVAL; 1087 1088 return __qcom_scm_pas_mss_reset(__scm->dev, 1); 1089 } 1090 1091 static int qcom_scm_pas_reset_deassert(struct reset_controller_dev *rcdev, 1092 unsigned long idx) 1093 { 1094 if (idx != 0) 1095 return -EINVAL; 1096 1097 return __qcom_scm_pas_mss_reset(__scm->dev, 0); 1098 } 1099 1100 static const struct reset_control_ops qcom_scm_pas_reset_ops = { 1101 .assert = qcom_scm_pas_reset_assert, 1102 .deassert = qcom_scm_pas_reset_deassert, 1103 }; 1104 1105 int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) 1106 { 1107 struct qcom_scm_desc desc = { 1108 .svc = QCOM_SCM_SVC_IO, 1109 .cmd = QCOM_SCM_IO_READ, 1110 .arginfo = QCOM_SCM_ARGS(1), 1111 .args[0] = addr, 1112 .owner = ARM_SMCCC_OWNER_SIP, 1113 }; 1114 struct qcom_scm_res res; 1115 int ret; 1116 1117 1118 ret = qcom_scm_call_atomic(__scm->dev, &desc, &res); 1119 if (ret >= 0) 1120 *val = res.result[0]; 1121 1122 return ret < 0 ? ret : 0; 1123 } 1124 EXPORT_SYMBOL_GPL(qcom_scm_io_readl); 1125 1126 int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) 1127 { 1128 struct qcom_scm_desc desc = { 1129 .svc = QCOM_SCM_SVC_IO, 1130 .cmd = QCOM_SCM_IO_WRITE, 1131 .arginfo = QCOM_SCM_ARGS(2), 1132 .args[0] = addr, 1133 .args[1] = val, 1134 .owner = ARM_SMCCC_OWNER_SIP, 1135 }; 1136 1137 return qcom_scm_call_atomic(__scm->dev, &desc, NULL); 1138 } 1139 EXPORT_SYMBOL_GPL(qcom_scm_io_writel); 1140 1141 /** 1142 * qcom_scm_restore_sec_cfg_available() - Check if secure environment 1143 * supports restore security config interface. 1144 * 1145 * Return true if restore-cfg interface is supported, false if not. 1146 */ 1147 bool qcom_scm_restore_sec_cfg_available(void) 1148 { 1149 return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_MP, 1150 QCOM_SCM_MP_RESTORE_SEC_CFG); 1151 } 1152 EXPORT_SYMBOL_GPL(qcom_scm_restore_sec_cfg_available); 1153 1154 int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) 1155 { 1156 struct qcom_scm_desc desc = { 1157 .svc = QCOM_SCM_SVC_MP, 1158 .cmd = QCOM_SCM_MP_RESTORE_SEC_CFG, 1159 .arginfo = QCOM_SCM_ARGS(2), 1160 .args[0] = device_id, 1161 .args[1] = spare, 1162 .owner = ARM_SMCCC_OWNER_SIP, 1163 }; 1164 struct qcom_scm_res res; 1165 int ret; 1166 1167 ret = qcom_scm_call(__scm->dev, &desc, &res); 1168 1169 return ret ? : res.result[0]; 1170 } 1171 EXPORT_SYMBOL_GPL(qcom_scm_restore_sec_cfg); 1172 1173 #define QCOM_SCM_CP_APERTURE_CONTEXT_MASK GENMASK(7, 0) 1174 1175 bool qcom_scm_set_gpu_smmu_aperture_is_available(void) 1176 { 1177 return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_MP, 1178 QCOM_SCM_MP_CP_SMMU_APERTURE_ID); 1179 } 1180 EXPORT_SYMBOL_GPL(qcom_scm_set_gpu_smmu_aperture_is_available); 1181 1182 int qcom_scm_set_gpu_smmu_aperture(unsigned int context_bank) 1183 { 1184 struct qcom_scm_desc desc = { 1185 .svc = QCOM_SCM_SVC_MP, 1186 .cmd = QCOM_SCM_MP_CP_SMMU_APERTURE_ID, 1187 .arginfo = QCOM_SCM_ARGS(4), 1188 .args[0] = 0xffff0000 | FIELD_PREP(QCOM_SCM_CP_APERTURE_CONTEXT_MASK, context_bank), 1189 .args[1] = 0xffffffff, 1190 .args[2] = 0xffffffff, 1191 .args[3] = 0xffffffff, 1192 .owner = ARM_SMCCC_OWNER_SIP 1193 }; 1194 1195 return qcom_scm_call(__scm->dev, &desc, NULL); 1196 } 1197 EXPORT_SYMBOL_GPL(qcom_scm_set_gpu_smmu_aperture); 1198 1199 int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) 1200 { 1201 struct qcom_scm_desc desc = { 1202 .svc = QCOM_SCM_SVC_MP, 1203 .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE, 1204 .arginfo = QCOM_SCM_ARGS(1), 1205 .args[0] = spare, 1206 .owner = ARM_SMCCC_OWNER_SIP, 1207 }; 1208 struct qcom_scm_res res; 1209 int ret; 1210 1211 ret = qcom_scm_call(__scm->dev, &desc, &res); 1212 1213 if (size) 1214 *size = res.result[0]; 1215 1216 return ret ? : res.result[1]; 1217 } 1218 EXPORT_SYMBOL_GPL(qcom_scm_iommu_secure_ptbl_size); 1219 1220 int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) 1221 { 1222 struct qcom_scm_desc desc = { 1223 .svc = QCOM_SCM_SVC_MP, 1224 .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT, 1225 .arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL, 1226 QCOM_SCM_VAL), 1227 .args[0] = addr, 1228 .args[1] = size, 1229 .args[2] = spare, 1230 .owner = ARM_SMCCC_OWNER_SIP, 1231 }; 1232 int ret; 1233 1234 ret = qcom_scm_call(__scm->dev, &desc, NULL); 1235 1236 /* the pg table has been initialized already, ignore the error */ 1237 if (ret == -EPERM) 1238 ret = 0; 1239 1240 return ret; 1241 } 1242 EXPORT_SYMBOL_GPL(qcom_scm_iommu_secure_ptbl_init); 1243 1244 int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size) 1245 { 1246 struct qcom_scm_desc desc = { 1247 .svc = QCOM_SCM_SVC_MP, 1248 .cmd = QCOM_SCM_MP_IOMMU_SET_CP_POOL_SIZE, 1249 .arginfo = QCOM_SCM_ARGS(2), 1250 .args[0] = size, 1251 .args[1] = spare, 1252 .owner = ARM_SMCCC_OWNER_SIP, 1253 }; 1254 1255 return qcom_scm_call(__scm->dev, &desc, NULL); 1256 } 1257 EXPORT_SYMBOL_GPL(qcom_scm_iommu_set_cp_pool_size); 1258 1259 int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size, 1260 u32 cp_nonpixel_start, 1261 u32 cp_nonpixel_size) 1262 { 1263 int ret; 1264 struct qcom_scm_desc desc = { 1265 .svc = QCOM_SCM_SVC_MP, 1266 .cmd = QCOM_SCM_MP_VIDEO_VAR, 1267 .arginfo = QCOM_SCM_ARGS(4, QCOM_SCM_VAL, QCOM_SCM_VAL, 1268 QCOM_SCM_VAL, QCOM_SCM_VAL), 1269 .args[0] = cp_start, 1270 .args[1] = cp_size, 1271 .args[2] = cp_nonpixel_start, 1272 .args[3] = cp_nonpixel_size, 1273 .owner = ARM_SMCCC_OWNER_SIP, 1274 }; 1275 struct qcom_scm_res res; 1276 1277 ret = qcom_scm_call(__scm->dev, &desc, &res); 1278 1279 return ret ? : res.result[0]; 1280 } 1281 EXPORT_SYMBOL_GPL(qcom_scm_mem_protect_video_var); 1282 1283 static int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, 1284 size_t mem_sz, phys_addr_t src, size_t src_sz, 1285 phys_addr_t dest, size_t dest_sz) 1286 { 1287 int ret; 1288 struct qcom_scm_desc desc = { 1289 .svc = QCOM_SCM_SVC_MP, 1290 .cmd = QCOM_SCM_MP_ASSIGN, 1291 .arginfo = QCOM_SCM_ARGS(7, QCOM_SCM_RO, QCOM_SCM_VAL, 1292 QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO, 1293 QCOM_SCM_VAL, QCOM_SCM_VAL), 1294 .args[0] = mem_region, 1295 .args[1] = mem_sz, 1296 .args[2] = src, 1297 .args[3] = src_sz, 1298 .args[4] = dest, 1299 .args[5] = dest_sz, 1300 .args[6] = 0, 1301 .owner = ARM_SMCCC_OWNER_SIP, 1302 }; 1303 struct qcom_scm_res res; 1304 1305 ret = qcom_scm_call(dev, &desc, &res); 1306 1307 return ret ? : res.result[0]; 1308 } 1309 1310 /** 1311 * qcom_scm_assign_mem() - Make a secure call to reassign memory ownership 1312 * @mem_addr: mem region whose ownership need to be reassigned 1313 * @mem_sz: size of the region. 1314 * @srcvm: vmid for current set of owners, each set bit in 1315 * flag indicate a unique owner 1316 * @newvm: array having new owners and corresponding permission 1317 * flags 1318 * @dest_cnt: number of owners in next set. 1319 * 1320 * Return negative errno on failure or 0 on success with @srcvm updated. 1321 */ 1322 int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, 1323 u64 *srcvm, 1324 const struct qcom_scm_vmperm *newvm, 1325 unsigned int dest_cnt) 1326 { 1327 struct qcom_scm_current_perm_info *destvm; 1328 struct qcom_scm_mem_map_info *mem_to_map; 1329 phys_addr_t mem_to_map_phys; 1330 phys_addr_t dest_phys; 1331 phys_addr_t ptr_phys; 1332 size_t mem_to_map_sz; 1333 size_t dest_sz; 1334 size_t src_sz; 1335 size_t ptr_sz; 1336 int next_vm; 1337 __le32 *src; 1338 int ret, i, b; 1339 u64 srcvm_bits = *srcvm; 1340 1341 src_sz = hweight64(srcvm_bits) * sizeof(*src); 1342 mem_to_map_sz = sizeof(*mem_to_map); 1343 dest_sz = dest_cnt * sizeof(*destvm); 1344 ptr_sz = ALIGN(src_sz, SZ_64) + ALIGN(mem_to_map_sz, SZ_64) + 1345 ALIGN(dest_sz, SZ_64); 1346 1347 void *ptr __free(qcom_tzmem) = qcom_tzmem_alloc(__scm->mempool, 1348 ptr_sz, GFP_KERNEL); 1349 if (!ptr) 1350 return -ENOMEM; 1351 1352 ptr_phys = qcom_tzmem_to_phys(ptr); 1353 1354 /* Fill source vmid detail */ 1355 src = ptr; 1356 i = 0; 1357 for (b = 0; b < BITS_PER_TYPE(u64); b++) { 1358 if (srcvm_bits & BIT(b)) 1359 src[i++] = cpu_to_le32(b); 1360 } 1361 1362 /* Fill details of mem buff to map */ 1363 mem_to_map = ptr + ALIGN(src_sz, SZ_64); 1364 mem_to_map_phys = ptr_phys + ALIGN(src_sz, SZ_64); 1365 mem_to_map->mem_addr = cpu_to_le64(mem_addr); 1366 mem_to_map->mem_size = cpu_to_le64(mem_sz); 1367 1368 next_vm = 0; 1369 /* Fill details of next vmid detail */ 1370 destvm = ptr + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64); 1371 dest_phys = ptr_phys + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64); 1372 for (i = 0; i < dest_cnt; i++, destvm++, newvm++) { 1373 destvm->vmid = cpu_to_le32(newvm->vmid); 1374 destvm->perm = cpu_to_le32(newvm->perm); 1375 destvm->ctx = 0; 1376 destvm->ctx_size = 0; 1377 next_vm |= BIT(newvm->vmid); 1378 } 1379 1380 ret = __qcom_scm_assign_mem(__scm->dev, mem_to_map_phys, mem_to_map_sz, 1381 ptr_phys, src_sz, dest_phys, dest_sz); 1382 if (ret) { 1383 dev_err(__scm->dev, 1384 "Assign memory protection call failed %d\n", ret); 1385 return ret; 1386 } 1387 1388 *srcvm = next_vm; 1389 return 0; 1390 } 1391 EXPORT_SYMBOL_GPL(qcom_scm_assign_mem); 1392 1393 /** 1394 * qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available 1395 */ 1396 bool qcom_scm_ocmem_lock_available(void) 1397 { 1398 return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_OCMEM, 1399 QCOM_SCM_OCMEM_LOCK_CMD); 1400 } 1401 EXPORT_SYMBOL_GPL(qcom_scm_ocmem_lock_available); 1402 1403 /** 1404 * qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM 1405 * region to the specified initiator 1406 * 1407 * @id: tz initiator id 1408 * @offset: OCMEM offset 1409 * @size: OCMEM size 1410 * @mode: access mode (WIDE/NARROW) 1411 */ 1412 int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size, 1413 u32 mode) 1414 { 1415 struct qcom_scm_desc desc = { 1416 .svc = QCOM_SCM_SVC_OCMEM, 1417 .cmd = QCOM_SCM_OCMEM_LOCK_CMD, 1418 .args[0] = id, 1419 .args[1] = offset, 1420 .args[2] = size, 1421 .args[3] = mode, 1422 .arginfo = QCOM_SCM_ARGS(4), 1423 }; 1424 1425 return qcom_scm_call(__scm->dev, &desc, NULL); 1426 } 1427 EXPORT_SYMBOL_GPL(qcom_scm_ocmem_lock); 1428 1429 /** 1430 * qcom_scm_ocmem_unlock() - call OCMEM unlock interface to release an OCMEM 1431 * region from the specified initiator 1432 * 1433 * @id: tz initiator id 1434 * @offset: OCMEM offset 1435 * @size: OCMEM size 1436 */ 1437 int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size) 1438 { 1439 struct qcom_scm_desc desc = { 1440 .svc = QCOM_SCM_SVC_OCMEM, 1441 .cmd = QCOM_SCM_OCMEM_UNLOCK_CMD, 1442 .args[0] = id, 1443 .args[1] = offset, 1444 .args[2] = size, 1445 .arginfo = QCOM_SCM_ARGS(3), 1446 }; 1447 1448 return qcom_scm_call(__scm->dev, &desc, NULL); 1449 } 1450 EXPORT_SYMBOL_GPL(qcom_scm_ocmem_unlock); 1451 1452 /** 1453 * qcom_scm_ice_available() - Is the ICE key programming interface available? 1454 * 1455 * Return: true iff the SCM calls wrapped by qcom_scm_ice_invalidate_key() and 1456 * qcom_scm_ice_set_key() are available. 1457 */ 1458 bool qcom_scm_ice_available(void) 1459 { 1460 return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES, 1461 QCOM_SCM_ES_INVALIDATE_ICE_KEY) && 1462 __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES, 1463 QCOM_SCM_ES_CONFIG_SET_ICE_KEY); 1464 } 1465 EXPORT_SYMBOL_GPL(qcom_scm_ice_available); 1466 1467 /** 1468 * qcom_scm_ice_invalidate_key() - Invalidate an inline encryption key 1469 * @index: the keyslot to invalidate 1470 * 1471 * The UFSHCI and eMMC standards define a standard way to do this, but it 1472 * doesn't work on these SoCs; only this SCM call does. 1473 * 1474 * It is assumed that the SoC has only one ICE instance being used, as this SCM 1475 * call doesn't specify which ICE instance the keyslot belongs to. 1476 * 1477 * Return: 0 on success; -errno on failure. 1478 */ 1479 int qcom_scm_ice_invalidate_key(u32 index) 1480 { 1481 struct qcom_scm_desc desc = { 1482 .svc = QCOM_SCM_SVC_ES, 1483 .cmd = QCOM_SCM_ES_INVALIDATE_ICE_KEY, 1484 .arginfo = QCOM_SCM_ARGS(1), 1485 .args[0] = index, 1486 .owner = ARM_SMCCC_OWNER_SIP, 1487 }; 1488 1489 return qcom_scm_call(__scm->dev, &desc, NULL); 1490 } 1491 EXPORT_SYMBOL_GPL(qcom_scm_ice_invalidate_key); 1492 1493 /** 1494 * qcom_scm_ice_set_key() - Set an inline encryption key 1495 * @index: the keyslot into which to set the key 1496 * @key: the key to program 1497 * @key_size: the size of the key in bytes 1498 * @cipher: the encryption algorithm the key is for 1499 * @data_unit_size: the encryption data unit size, i.e. the size of each 1500 * individual plaintext and ciphertext. Given in 512-byte 1501 * units, e.g. 1 = 512 bytes, 8 = 4096 bytes, etc. 1502 * 1503 * Program a key into a keyslot of Qualcomm ICE (Inline Crypto Engine), where it 1504 * can then be used to encrypt/decrypt UFS or eMMC I/O requests inline. 1505 * 1506 * The UFSHCI and eMMC standards define a standard way to do this, but it 1507 * doesn't work on these SoCs; only this SCM call does. 1508 * 1509 * It is assumed that the SoC has only one ICE instance being used, as this SCM 1510 * call doesn't specify which ICE instance the keyslot belongs to. 1511 * 1512 * Return: 0 on success; -errno on failure. 1513 */ 1514 int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size, 1515 enum qcom_scm_ice_cipher cipher, u32 data_unit_size) 1516 { 1517 struct qcom_scm_desc desc = { 1518 .svc = QCOM_SCM_SVC_ES, 1519 .cmd = QCOM_SCM_ES_CONFIG_SET_ICE_KEY, 1520 .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_VAL, QCOM_SCM_RW, 1521 QCOM_SCM_VAL, QCOM_SCM_VAL, 1522 QCOM_SCM_VAL), 1523 .args[0] = index, 1524 .args[2] = key_size, 1525 .args[3] = cipher, 1526 .args[4] = data_unit_size, 1527 .owner = ARM_SMCCC_OWNER_SIP, 1528 }; 1529 1530 int ret; 1531 1532 void *keybuf __free(qcom_tzmem) = qcom_tzmem_alloc(__scm->mempool, 1533 key_size, 1534 GFP_KERNEL); 1535 if (!keybuf) 1536 return -ENOMEM; 1537 memcpy(keybuf, key, key_size); 1538 desc.args[1] = qcom_tzmem_to_phys(keybuf); 1539 1540 ret = qcom_scm_call(__scm->dev, &desc, NULL); 1541 1542 memzero_explicit(keybuf, key_size); 1543 1544 return ret; 1545 } 1546 EXPORT_SYMBOL_GPL(qcom_scm_ice_set_key); 1547 1548 bool qcom_scm_has_wrapped_key_support(void) 1549 { 1550 return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES, 1551 QCOM_SCM_ES_DERIVE_SW_SECRET) && 1552 __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES, 1553 QCOM_SCM_ES_GENERATE_ICE_KEY) && 1554 __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES, 1555 QCOM_SCM_ES_PREPARE_ICE_KEY) && 1556 __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES, 1557 QCOM_SCM_ES_IMPORT_ICE_KEY); 1558 } 1559 EXPORT_SYMBOL_GPL(qcom_scm_has_wrapped_key_support); 1560 1561 /** 1562 * qcom_scm_derive_sw_secret() - Derive software secret from wrapped key 1563 * @eph_key: an ephemerally-wrapped key 1564 * @eph_key_size: size of @eph_key in bytes 1565 * @sw_secret: output buffer for the software secret 1566 * @sw_secret_size: size of the software secret to derive in bytes 1567 * 1568 * Derive a software secret from an ephemerally-wrapped key for software crypto 1569 * operations. This is done by calling into the secure execution environment, 1570 * which then calls into the hardware to unwrap and derive the secret. 1571 * 1572 * For more information on sw_secret, see the "Hardware-wrapped keys" section of 1573 * Documentation/block/inline-encryption.rst. 1574 * 1575 * Return: 0 on success; -errno on failure. 1576 */ 1577 int qcom_scm_derive_sw_secret(const u8 *eph_key, size_t eph_key_size, 1578 u8 *sw_secret, size_t sw_secret_size) 1579 { 1580 struct qcom_scm_desc desc = { 1581 .svc = QCOM_SCM_SVC_ES, 1582 .cmd = QCOM_SCM_ES_DERIVE_SW_SECRET, 1583 .arginfo = QCOM_SCM_ARGS(4, QCOM_SCM_RW, QCOM_SCM_VAL, 1584 QCOM_SCM_RW, QCOM_SCM_VAL), 1585 .owner = ARM_SMCCC_OWNER_SIP, 1586 }; 1587 int ret; 1588 1589 void *eph_key_buf __free(qcom_tzmem) = qcom_tzmem_alloc(__scm->mempool, 1590 eph_key_size, 1591 GFP_KERNEL); 1592 if (!eph_key_buf) 1593 return -ENOMEM; 1594 1595 void *sw_secret_buf __free(qcom_tzmem) = qcom_tzmem_alloc(__scm->mempool, 1596 sw_secret_size, 1597 GFP_KERNEL); 1598 if (!sw_secret_buf) 1599 return -ENOMEM; 1600 1601 memcpy(eph_key_buf, eph_key, eph_key_size); 1602 desc.args[0] = qcom_tzmem_to_phys(eph_key_buf); 1603 desc.args[1] = eph_key_size; 1604 desc.args[2] = qcom_tzmem_to_phys(sw_secret_buf); 1605 desc.args[3] = sw_secret_size; 1606 1607 ret = qcom_scm_call(__scm->dev, &desc, NULL); 1608 if (!ret) 1609 memcpy(sw_secret, sw_secret_buf, sw_secret_size); 1610 1611 memzero_explicit(eph_key_buf, eph_key_size); 1612 memzero_explicit(sw_secret_buf, sw_secret_size); 1613 return ret; 1614 } 1615 EXPORT_SYMBOL_GPL(qcom_scm_derive_sw_secret); 1616 1617 /** 1618 * qcom_scm_generate_ice_key() - Generate a wrapped key for storage encryption 1619 * @lt_key: output buffer for the long-term wrapped key 1620 * @lt_key_size: size of @lt_key in bytes. Must be the exact wrapped key size 1621 * used by the SoC. 1622 * 1623 * Generate a key using the built-in HW module in the SoC. The resulting key is 1624 * returned wrapped with the platform-specific Key Encryption Key. 1625 * 1626 * Return: 0 on success; -errno on failure. 1627 */ 1628 int qcom_scm_generate_ice_key(u8 *lt_key, size_t lt_key_size) 1629 { 1630 struct qcom_scm_desc desc = { 1631 .svc = QCOM_SCM_SVC_ES, 1632 .cmd = QCOM_SCM_ES_GENERATE_ICE_KEY, 1633 .arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_RW, QCOM_SCM_VAL), 1634 .owner = ARM_SMCCC_OWNER_SIP, 1635 }; 1636 int ret; 1637 1638 void *lt_key_buf __free(qcom_tzmem) = qcom_tzmem_alloc(__scm->mempool, 1639 lt_key_size, 1640 GFP_KERNEL); 1641 if (!lt_key_buf) 1642 return -ENOMEM; 1643 1644 desc.args[0] = qcom_tzmem_to_phys(lt_key_buf); 1645 desc.args[1] = lt_key_size; 1646 1647 ret = qcom_scm_call(__scm->dev, &desc, NULL); 1648 if (!ret) 1649 memcpy(lt_key, lt_key_buf, lt_key_size); 1650 1651 memzero_explicit(lt_key_buf, lt_key_size); 1652 return ret; 1653 } 1654 EXPORT_SYMBOL_GPL(qcom_scm_generate_ice_key); 1655 1656 /** 1657 * qcom_scm_prepare_ice_key() - Re-wrap a key with the per-boot ephemeral key 1658 * @lt_key: a long-term wrapped key 1659 * @lt_key_size: size of @lt_key in bytes 1660 * @eph_key: output buffer for the ephemerally-wrapped key 1661 * @eph_key_size: size of @eph_key in bytes. Must be the exact wrapped key size 1662 * used by the SoC. 1663 * 1664 * Given a long-term wrapped key, re-wrap it with the per-boot ephemeral key for 1665 * added protection. The resulting key will only be valid for the current boot. 1666 * 1667 * Return: 0 on success; -errno on failure. 1668 */ 1669 int qcom_scm_prepare_ice_key(const u8 *lt_key, size_t lt_key_size, 1670 u8 *eph_key, size_t eph_key_size) 1671 { 1672 struct qcom_scm_desc desc = { 1673 .svc = QCOM_SCM_SVC_ES, 1674 .cmd = QCOM_SCM_ES_PREPARE_ICE_KEY, 1675 .arginfo = QCOM_SCM_ARGS(4, QCOM_SCM_RO, QCOM_SCM_VAL, 1676 QCOM_SCM_RW, QCOM_SCM_VAL), 1677 .owner = ARM_SMCCC_OWNER_SIP, 1678 }; 1679 int ret; 1680 1681 void *lt_key_buf __free(qcom_tzmem) = qcom_tzmem_alloc(__scm->mempool, 1682 lt_key_size, 1683 GFP_KERNEL); 1684 if (!lt_key_buf) 1685 return -ENOMEM; 1686 1687 void *eph_key_buf __free(qcom_tzmem) = qcom_tzmem_alloc(__scm->mempool, 1688 eph_key_size, 1689 GFP_KERNEL); 1690 if (!eph_key_buf) 1691 return -ENOMEM; 1692 1693 memcpy(lt_key_buf, lt_key, lt_key_size); 1694 desc.args[0] = qcom_tzmem_to_phys(lt_key_buf); 1695 desc.args[1] = lt_key_size; 1696 desc.args[2] = qcom_tzmem_to_phys(eph_key_buf); 1697 desc.args[3] = eph_key_size; 1698 1699 ret = qcom_scm_call(__scm->dev, &desc, NULL); 1700 if (!ret) 1701 memcpy(eph_key, eph_key_buf, eph_key_size); 1702 1703 memzero_explicit(lt_key_buf, lt_key_size); 1704 memzero_explicit(eph_key_buf, eph_key_size); 1705 return ret; 1706 } 1707 EXPORT_SYMBOL_GPL(qcom_scm_prepare_ice_key); 1708 1709 /** 1710 * qcom_scm_import_ice_key() - Import key for storage encryption 1711 * @raw_key: the raw key to import 1712 * @raw_key_size: size of @raw_key in bytes 1713 * @lt_key: output buffer for the long-term wrapped key 1714 * @lt_key_size: size of @lt_key in bytes. Must be the exact wrapped key size 1715 * used by the SoC. 1716 * 1717 * Import a raw key and return a long-term wrapped key. Uses the SoC's HWKM to 1718 * wrap the raw key using the platform-specific Key Encryption Key. 1719 * 1720 * Return: 0 on success; -errno on failure. 1721 */ 1722 int qcom_scm_import_ice_key(const u8 *raw_key, size_t raw_key_size, 1723 u8 *lt_key, size_t lt_key_size) 1724 { 1725 struct qcom_scm_desc desc = { 1726 .svc = QCOM_SCM_SVC_ES, 1727 .cmd = QCOM_SCM_ES_IMPORT_ICE_KEY, 1728 .arginfo = QCOM_SCM_ARGS(4, QCOM_SCM_RO, QCOM_SCM_VAL, 1729 QCOM_SCM_RW, QCOM_SCM_VAL), 1730 .owner = ARM_SMCCC_OWNER_SIP, 1731 }; 1732 int ret; 1733 1734 void *raw_key_buf __free(qcom_tzmem) = qcom_tzmem_alloc(__scm->mempool, 1735 raw_key_size, 1736 GFP_KERNEL); 1737 if (!raw_key_buf) 1738 return -ENOMEM; 1739 1740 void *lt_key_buf __free(qcom_tzmem) = qcom_tzmem_alloc(__scm->mempool, 1741 lt_key_size, 1742 GFP_KERNEL); 1743 if (!lt_key_buf) 1744 return -ENOMEM; 1745 1746 memcpy(raw_key_buf, raw_key, raw_key_size); 1747 desc.args[0] = qcom_tzmem_to_phys(raw_key_buf); 1748 desc.args[1] = raw_key_size; 1749 desc.args[2] = qcom_tzmem_to_phys(lt_key_buf); 1750 desc.args[3] = lt_key_size; 1751 1752 ret = qcom_scm_call(__scm->dev, &desc, NULL); 1753 if (!ret) 1754 memcpy(lt_key, lt_key_buf, lt_key_size); 1755 1756 memzero_explicit(raw_key_buf, raw_key_size); 1757 memzero_explicit(lt_key_buf, lt_key_size); 1758 return ret; 1759 } 1760 EXPORT_SYMBOL_GPL(qcom_scm_import_ice_key); 1761 1762 /** 1763 * qcom_scm_hdcp_available() - Check if secure environment supports HDCP. 1764 * 1765 * Return true if HDCP is supported, false if not. 1766 */ 1767 bool qcom_scm_hdcp_available(void) 1768 { 1769 bool avail; 1770 int ret = qcom_scm_clk_enable(); 1771 1772 if (ret) 1773 return ret; 1774 1775 avail = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP, 1776 QCOM_SCM_HDCP_INVOKE); 1777 1778 qcom_scm_clk_disable(); 1779 1780 return avail; 1781 } 1782 EXPORT_SYMBOL_GPL(qcom_scm_hdcp_available); 1783 1784 /** 1785 * qcom_scm_hdcp_req() - Send HDCP request. 1786 * @req: HDCP request array 1787 * @req_cnt: HDCP request array count 1788 * @resp: response buffer passed to SCM 1789 * 1790 * Write HDCP register(s) through SCM. 1791 */ 1792 int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) 1793 { 1794 int ret; 1795 struct qcom_scm_desc desc = { 1796 .svc = QCOM_SCM_SVC_HDCP, 1797 .cmd = QCOM_SCM_HDCP_INVOKE, 1798 .arginfo = QCOM_SCM_ARGS(10), 1799 .args = { 1800 req[0].addr, 1801 req[0].val, 1802 req[1].addr, 1803 req[1].val, 1804 req[2].addr, 1805 req[2].val, 1806 req[3].addr, 1807 req[3].val, 1808 req[4].addr, 1809 req[4].val 1810 }, 1811 .owner = ARM_SMCCC_OWNER_SIP, 1812 }; 1813 struct qcom_scm_res res; 1814 1815 if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT) 1816 return -ERANGE; 1817 1818 ret = qcom_scm_clk_enable(); 1819 if (ret) 1820 return ret; 1821 1822 ret = qcom_scm_call(__scm->dev, &desc, &res); 1823 *resp = res.result[0]; 1824 1825 qcom_scm_clk_disable(); 1826 1827 return ret; 1828 } 1829 EXPORT_SYMBOL_GPL(qcom_scm_hdcp_req); 1830 1831 int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt) 1832 { 1833 struct qcom_scm_desc desc = { 1834 .svc = QCOM_SCM_SVC_SMMU_PROGRAM, 1835 .cmd = QCOM_SCM_SMMU_PT_FORMAT, 1836 .arginfo = QCOM_SCM_ARGS(3), 1837 .args[0] = sec_id, 1838 .args[1] = ctx_num, 1839 .args[2] = pt_fmt, /* 0: LPAE AArch32 - 1: AArch64 */ 1840 .owner = ARM_SMCCC_OWNER_SIP, 1841 }; 1842 1843 return qcom_scm_call(__scm->dev, &desc, NULL); 1844 } 1845 EXPORT_SYMBOL_GPL(qcom_scm_iommu_set_pt_format); 1846 1847 int qcom_scm_qsmmu500_wait_safe_toggle(bool en) 1848 { 1849 struct qcom_scm_desc desc = { 1850 .svc = QCOM_SCM_SVC_SMMU_PROGRAM, 1851 .cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1, 1852 .arginfo = QCOM_SCM_ARGS(2), 1853 .args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL, 1854 .args[1] = en, 1855 .owner = ARM_SMCCC_OWNER_SIP, 1856 }; 1857 1858 1859 return qcom_scm_call_atomic(__scm->dev, &desc, NULL); 1860 } 1861 EXPORT_SYMBOL_GPL(qcom_scm_qsmmu500_wait_safe_toggle); 1862 1863 bool qcom_scm_lmh_dcvsh_available(void) 1864 { 1865 return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_LMH, QCOM_SCM_LMH_LIMIT_DCVSH); 1866 } 1867 EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh_available); 1868 1869 /* 1870 * This is only supposed to be called once by the TZMem module. It takes the 1871 * SCM struct device as argument and uses it to pass the call as at the time 1872 * the SHM Bridge is enabled, the SCM is not yet fully set up and doesn't 1873 * accept global user calls. Don't try to use the __scm pointer here. 1874 */ 1875 int qcom_scm_shm_bridge_enable(struct device *scm_dev) 1876 { 1877 int ret; 1878 1879 struct qcom_scm_desc desc = { 1880 .svc = QCOM_SCM_SVC_MP, 1881 .cmd = QCOM_SCM_MP_SHM_BRIDGE_ENABLE, 1882 .owner = ARM_SMCCC_OWNER_SIP 1883 }; 1884 1885 struct qcom_scm_res res; 1886 1887 if (!__qcom_scm_is_call_available(scm_dev, QCOM_SCM_SVC_MP, 1888 QCOM_SCM_MP_SHM_BRIDGE_ENABLE)) 1889 return -EOPNOTSUPP; 1890 1891 ret = qcom_scm_call(scm_dev, &desc, &res); 1892 1893 if (ret) 1894 return ret; 1895 1896 if (res.result[0] == SHMBRIDGE_RESULT_NOTSUPP) 1897 return -EOPNOTSUPP; 1898 1899 return res.result[0]; 1900 } 1901 EXPORT_SYMBOL_GPL(qcom_scm_shm_bridge_enable); 1902 1903 int qcom_scm_shm_bridge_create(u64 pfn_and_ns_perm_flags, 1904 u64 ipfn_and_s_perm_flags, u64 size_and_flags, 1905 u64 ns_vmids, u64 *handle) 1906 { 1907 struct qcom_scm_desc desc = { 1908 .svc = QCOM_SCM_SVC_MP, 1909 .cmd = QCOM_SCM_MP_SHM_BRIDGE_CREATE, 1910 .owner = ARM_SMCCC_OWNER_SIP, 1911 .args[0] = pfn_and_ns_perm_flags, 1912 .args[1] = ipfn_and_s_perm_flags, 1913 .args[2] = size_and_flags, 1914 .args[3] = ns_vmids, 1915 .arginfo = QCOM_SCM_ARGS(4, QCOM_SCM_VAL, QCOM_SCM_VAL, 1916 QCOM_SCM_VAL, QCOM_SCM_VAL), 1917 }; 1918 1919 struct qcom_scm_res res; 1920 int ret; 1921 1922 ret = qcom_scm_call(__scm->dev, &desc, &res); 1923 1924 if (handle && !ret) 1925 *handle = res.result[1]; 1926 1927 return ret ?: res.result[0]; 1928 } 1929 EXPORT_SYMBOL_GPL(qcom_scm_shm_bridge_create); 1930 1931 int qcom_scm_shm_bridge_delete(u64 handle) 1932 { 1933 struct qcom_scm_desc desc = { 1934 .svc = QCOM_SCM_SVC_MP, 1935 .cmd = QCOM_SCM_MP_SHM_BRIDGE_DELETE, 1936 .owner = ARM_SMCCC_OWNER_SIP, 1937 .args[0] = handle, 1938 .arginfo = QCOM_SCM_ARGS(1, QCOM_SCM_VAL), 1939 }; 1940 1941 return qcom_scm_call(__scm->dev, &desc, NULL); 1942 } 1943 EXPORT_SYMBOL_GPL(qcom_scm_shm_bridge_delete); 1944 1945 int qcom_scm_lmh_profile_change(u32 profile_id) 1946 { 1947 struct qcom_scm_desc desc = { 1948 .svc = QCOM_SCM_SVC_LMH, 1949 .cmd = QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE, 1950 .arginfo = QCOM_SCM_ARGS(1, QCOM_SCM_VAL), 1951 .args[0] = profile_id, 1952 .owner = ARM_SMCCC_OWNER_SIP, 1953 }; 1954 1955 return qcom_scm_call(__scm->dev, &desc, NULL); 1956 } 1957 EXPORT_SYMBOL_GPL(qcom_scm_lmh_profile_change); 1958 1959 int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, 1960 u64 limit_node, u32 node_id, u64 version) 1961 { 1962 int ret, payload_size = 5 * sizeof(u32); 1963 1964 struct qcom_scm_desc desc = { 1965 .svc = QCOM_SCM_SVC_LMH, 1966 .cmd = QCOM_SCM_LMH_LIMIT_DCVSH, 1967 .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_VAL, 1968 QCOM_SCM_VAL, QCOM_SCM_VAL), 1969 .args[1] = payload_size, 1970 .args[2] = limit_node, 1971 .args[3] = node_id, 1972 .args[4] = version, 1973 .owner = ARM_SMCCC_OWNER_SIP, 1974 }; 1975 1976 u32 *payload_buf __free(qcom_tzmem) = qcom_tzmem_alloc(__scm->mempool, 1977 payload_size, 1978 GFP_KERNEL); 1979 if (!payload_buf) 1980 return -ENOMEM; 1981 1982 payload_buf[0] = payload_fn; 1983 payload_buf[1] = 0; 1984 payload_buf[2] = payload_reg; 1985 payload_buf[3] = 1; 1986 payload_buf[4] = payload_val; 1987 1988 desc.args[0] = qcom_tzmem_to_phys(payload_buf); 1989 1990 ret = qcom_scm_call(__scm->dev, &desc, NULL); 1991 1992 return ret; 1993 } 1994 EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh); 1995 1996 int qcom_scm_gpu_init_regs(u32 gpu_req) 1997 { 1998 struct qcom_scm_desc desc = { 1999 .svc = QCOM_SCM_SVC_GPU, 2000 .cmd = QCOM_SCM_SVC_GPU_INIT_REGS, 2001 .arginfo = QCOM_SCM_ARGS(1), 2002 .args[0] = gpu_req, 2003 .owner = ARM_SMCCC_OWNER_SIP, 2004 }; 2005 2006 return qcom_scm_call(__scm->dev, &desc, NULL); 2007 } 2008 EXPORT_SYMBOL_GPL(qcom_scm_gpu_init_regs); 2009 2010 static int qcom_scm_find_dload_address(struct device *dev, u64 *addr) 2011 { 2012 struct device_node *tcsr; 2013 struct device_node *np = dev->of_node; 2014 struct resource res; 2015 u32 offset; 2016 int ret; 2017 2018 tcsr = of_parse_phandle(np, "qcom,dload-mode", 0); 2019 if (!tcsr) 2020 return 0; 2021 2022 ret = of_address_to_resource(tcsr, 0, &res); 2023 of_node_put(tcsr); 2024 if (ret) 2025 return ret; 2026 2027 ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset); 2028 if (ret < 0) 2029 return ret; 2030 2031 *addr = res.start + offset; 2032 2033 return 0; 2034 } 2035 2036 #ifdef CONFIG_QCOM_QSEECOM 2037 2038 /* Lock for QSEECOM SCM call executions */ 2039 static DEFINE_MUTEX(qcom_scm_qseecom_call_lock); 2040 2041 static int __qcom_scm_qseecom_call(const struct qcom_scm_desc *desc, 2042 struct qcom_scm_qseecom_resp *res) 2043 { 2044 struct qcom_scm_res scm_res = {}; 2045 int status; 2046 2047 /* 2048 * QSEECOM SCM calls should not be executed concurrently. Therefore, we 2049 * require the respective call lock to be held. 2050 */ 2051 lockdep_assert_held(&qcom_scm_qseecom_call_lock); 2052 2053 status = qcom_scm_call(__scm->dev, desc, &scm_res); 2054 2055 res->result = scm_res.result[0]; 2056 res->resp_type = scm_res.result[1]; 2057 res->data = scm_res.result[2]; 2058 2059 if (status) 2060 return status; 2061 2062 return 0; 2063 } 2064 2065 /** 2066 * qcom_scm_qseecom_call() - Perform a QSEECOM SCM call. 2067 * @desc: SCM call descriptor. 2068 * @res: SCM call response (output). 2069 * 2070 * Performs the QSEECOM SCM call described by @desc, returning the response in 2071 * @rsp. 2072 * 2073 * Return: Zero on success, nonzero on failure. 2074 */ 2075 static int qcom_scm_qseecom_call(const struct qcom_scm_desc *desc, 2076 struct qcom_scm_qseecom_resp *res) 2077 { 2078 int status; 2079 2080 /* 2081 * Note: Multiple QSEECOM SCM calls should not be executed same time, 2082 * so lock things here. This needs to be extended to callback/listener 2083 * handling when support for that is implemented. 2084 */ 2085 2086 mutex_lock(&qcom_scm_qseecom_call_lock); 2087 status = __qcom_scm_qseecom_call(desc, res); 2088 mutex_unlock(&qcom_scm_qseecom_call_lock); 2089 2090 dev_dbg(__scm->dev, "%s: owner=%x, svc=%x, cmd=%x, result=%lld, type=%llx, data=%llx\n", 2091 __func__, desc->owner, desc->svc, desc->cmd, res->result, 2092 res->resp_type, res->data); 2093 2094 if (status) { 2095 dev_err(__scm->dev, "qseecom: scm call failed with error %d\n", status); 2096 return status; 2097 } 2098 2099 /* 2100 * TODO: Handle incomplete and blocked calls: 2101 * 2102 * Incomplete and blocked calls are not supported yet. Some devices 2103 * and/or commands require those, some don't. Let's warn about them 2104 * prominently in case someone attempts to try these commands with a 2105 * device/command combination that isn't supported yet. 2106 */ 2107 WARN_ON(res->result == QSEECOM_RESULT_INCOMPLETE); 2108 WARN_ON(res->result == QSEECOM_RESULT_BLOCKED_ON_LISTENER); 2109 2110 return 0; 2111 } 2112 2113 /** 2114 * qcom_scm_qseecom_get_version() - Query the QSEECOM version. 2115 * @version: Pointer where the QSEECOM version will be stored. 2116 * 2117 * Performs the QSEECOM SCM querying the QSEECOM version currently running in 2118 * the TrustZone. 2119 * 2120 * Return: Zero on success, nonzero on failure. 2121 */ 2122 static int qcom_scm_qseecom_get_version(u32 *version) 2123 { 2124 struct qcom_scm_desc desc = {}; 2125 struct qcom_scm_qseecom_resp res = {}; 2126 u32 feature = 10; 2127 int ret; 2128 2129 desc.owner = QSEECOM_TZ_OWNER_SIP; 2130 desc.svc = QSEECOM_TZ_SVC_INFO; 2131 desc.cmd = QSEECOM_TZ_CMD_INFO_VERSION; 2132 desc.arginfo = QCOM_SCM_ARGS(1, QCOM_SCM_VAL); 2133 desc.args[0] = feature; 2134 2135 ret = qcom_scm_qseecom_call(&desc, &res); 2136 if (ret) 2137 return ret; 2138 2139 *version = res.result; 2140 return 0; 2141 } 2142 2143 /** 2144 * qcom_scm_qseecom_app_get_id() - Query the app ID for a given QSEE app name. 2145 * @app_name: The name of the app. 2146 * @app_id: The returned app ID. 2147 * 2148 * Query and return the application ID of the SEE app identified by the given 2149 * name. This returned ID is the unique identifier of the app required for 2150 * subsequent communication. 2151 * 2152 * Return: Zero on success, nonzero on failure, -ENOENT if the app has not been 2153 * loaded or could not be found. 2154 */ 2155 int qcom_scm_qseecom_app_get_id(const char *app_name, u32 *app_id) 2156 { 2157 unsigned long name_buf_size = QSEECOM_MAX_APP_NAME_SIZE; 2158 unsigned long app_name_len = strlen(app_name); 2159 struct qcom_scm_desc desc = {}; 2160 struct qcom_scm_qseecom_resp res = {}; 2161 int status; 2162 2163 if (app_name_len >= name_buf_size) 2164 return -EINVAL; 2165 2166 char *name_buf __free(qcom_tzmem) = qcom_tzmem_alloc(__scm->mempool, 2167 name_buf_size, 2168 GFP_KERNEL); 2169 if (!name_buf) 2170 return -ENOMEM; 2171 2172 memcpy(name_buf, app_name, app_name_len); 2173 2174 desc.owner = QSEECOM_TZ_OWNER_QSEE_OS; 2175 desc.svc = QSEECOM_TZ_SVC_APP_MGR; 2176 desc.cmd = QSEECOM_TZ_CMD_APP_LOOKUP; 2177 desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_RW, QCOM_SCM_VAL); 2178 desc.args[0] = qcom_tzmem_to_phys(name_buf); 2179 desc.args[1] = app_name_len; 2180 2181 status = qcom_scm_qseecom_call(&desc, &res); 2182 2183 if (status) 2184 return status; 2185 2186 if (res.result == QSEECOM_RESULT_FAILURE) 2187 return -ENOENT; 2188 2189 if (res.result != QSEECOM_RESULT_SUCCESS) 2190 return -EINVAL; 2191 2192 if (res.resp_type != QSEECOM_SCM_RES_APP_ID) 2193 return -EINVAL; 2194 2195 *app_id = res.data; 2196 return 0; 2197 } 2198 EXPORT_SYMBOL_GPL(qcom_scm_qseecom_app_get_id); 2199 2200 /** 2201 * qcom_scm_qseecom_app_send() - Send to and receive data from a given QSEE app. 2202 * @app_id: The ID of the target app. 2203 * @req: Request buffer sent to the app (must be TZ memory) 2204 * @req_size: Size of the request buffer. 2205 * @rsp: Response buffer, written to by the app (must be TZ memory) 2206 * @rsp_size: Size of the response buffer. 2207 * 2208 * Sends a request to the QSEE app associated with the given ID and read back 2209 * its response. The caller must provide two DMA memory regions, one for the 2210 * request and one for the response, and fill out the @req region with the 2211 * respective (app-specific) request data. The QSEE app reads this and returns 2212 * its response in the @rsp region. 2213 * 2214 * Return: Zero on success, nonzero on failure. 2215 */ 2216 int qcom_scm_qseecom_app_send(u32 app_id, void *req, size_t req_size, 2217 void *rsp, size_t rsp_size) 2218 { 2219 struct qcom_scm_qseecom_resp res = {}; 2220 struct qcom_scm_desc desc = {}; 2221 phys_addr_t req_phys; 2222 phys_addr_t rsp_phys; 2223 int status; 2224 2225 req_phys = qcom_tzmem_to_phys(req); 2226 rsp_phys = qcom_tzmem_to_phys(rsp); 2227 2228 desc.owner = QSEECOM_TZ_OWNER_TZ_APPS; 2229 desc.svc = QSEECOM_TZ_SVC_APP_ID_PLACEHOLDER; 2230 desc.cmd = QSEECOM_TZ_CMD_APP_SEND; 2231 desc.arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_VAL, 2232 QCOM_SCM_RW, QCOM_SCM_VAL, 2233 QCOM_SCM_RW, QCOM_SCM_VAL); 2234 desc.args[0] = app_id; 2235 desc.args[1] = req_phys; 2236 desc.args[2] = req_size; 2237 desc.args[3] = rsp_phys; 2238 desc.args[4] = rsp_size; 2239 2240 status = qcom_scm_qseecom_call(&desc, &res); 2241 2242 if (status) 2243 return status; 2244 2245 if (res.result != QSEECOM_RESULT_SUCCESS) 2246 return -EIO; 2247 2248 return 0; 2249 } 2250 EXPORT_SYMBOL_GPL(qcom_scm_qseecom_app_send); 2251 2252 /* 2253 * We do not yet support re-entrant calls via the qseecom interface. To prevent 2254 + any potential issues with this, only allow validated machines for now. 2255 */ 2256 static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = { 2257 { .compatible = "asus,vivobook-s15" }, 2258 { .compatible = "asus,vivobook-s15-x1p4" }, 2259 { .compatible = "asus,zenbook-a14-ux3407qa" }, 2260 { .compatible = "asus,zenbook-a14-ux3407ra" }, 2261 { .compatible = "dell,inspiron-14-plus-7441" }, 2262 { .compatible = "dell,latitude-7455" }, 2263 { .compatible = "dell,xps13-9345" }, 2264 { .compatible = "ecs,liva-qc710" }, 2265 { .compatible = "hp,elitebook-ultra-g1q" }, 2266 { .compatible = "hp,omnibook-x14" }, 2267 { .compatible = "huawei,gaokun3" }, 2268 { .compatible = "lenovo,flex-5g" }, 2269 { .compatible = "lenovo,ideacentre-mini-01q8x10" }, 2270 { .compatible = "lenovo,thinkbook-16" }, 2271 { .compatible = "lenovo,thinkpad-t14s" }, 2272 { .compatible = "lenovo,thinkpad-x13s", }, 2273 { .compatible = "lenovo,yoga-slim7x" }, 2274 { .compatible = "medion,sprchrgd14s1" }, 2275 { .compatible = "microsoft,arcata", }, 2276 { .compatible = "microsoft,surface-pro-12in", }, 2277 { .compatible = "microsoft,blackrock" }, 2278 { .compatible = "microsoft,denali", }, 2279 { .compatible = "microsoft,romulus13", }, 2280 { .compatible = "microsoft,romulus15", }, 2281 { .compatible = "qcom,glymur-crd" }, 2282 { .compatible = "qcom,hamoa-iot-evk" }, 2283 { .compatible = "qcom,mahua-crd" }, 2284 { .compatible = "qcom,purwa-iot-evk" }, 2285 { .compatible = "qcom,sc8180x-primus" }, 2286 { .compatible = "qcom,x1e001de-devkit" }, 2287 { .compatible = "qcom,x1e80100-crd" }, 2288 { .compatible = "qcom,x1e80100-qcp" }, 2289 { .compatible = "qcom,x1p42100-crd" }, 2290 { } 2291 }; 2292 2293 static void qcom_scm_qseecom_free(void *data) 2294 { 2295 struct platform_device *qseecom_dev = data; 2296 2297 platform_device_del(qseecom_dev); 2298 platform_device_put(qseecom_dev); 2299 } 2300 2301 static int qcom_scm_qseecom_init(struct qcom_scm *scm) 2302 { 2303 struct platform_device *qseecom_dev; 2304 u32 version; 2305 int ret; 2306 2307 /* 2308 * Note: We do two steps of validation here: First, we try to query the 2309 * QSEECOM version as a check to see if the interface exists on this 2310 * device. Second, we check against known good devices due to current 2311 * driver limitations (see comment in qcom_scm_qseecom_allowlist). 2312 * 2313 * Note that we deliberately do the machine check after the version 2314 * check so that we can log potentially supported devices. This should 2315 * be safe as downstream sources indicate that the version query is 2316 * neither blocking nor reentrant. 2317 */ 2318 ret = qcom_scm_qseecom_get_version(&version); 2319 if (ret) 2320 return 0; 2321 2322 dev_info(scm->dev, "qseecom: found qseecom with version 0x%x\n", version); 2323 2324 if (!of_machine_device_match(qcom_scm_qseecom_allowlist)) { 2325 dev_info(scm->dev, "qseecom: untested machine, skipping\n"); 2326 return 0; 2327 } 2328 2329 /* 2330 * Set up QSEECOM interface device. All application clients will be 2331 * set up and managed by the corresponding driver for it. 2332 */ 2333 qseecom_dev = platform_device_alloc("qcom_qseecom", -1); 2334 if (!qseecom_dev) 2335 return -ENOMEM; 2336 2337 qseecom_dev->dev.parent = scm->dev; 2338 2339 ret = platform_device_add(qseecom_dev); 2340 if (ret) { 2341 platform_device_put(qseecom_dev); 2342 return ret; 2343 } 2344 2345 return devm_add_action_or_reset(scm->dev, qcom_scm_qseecom_free, qseecom_dev); 2346 } 2347 2348 #else /* CONFIG_QCOM_QSEECOM */ 2349 2350 static int qcom_scm_qseecom_init(struct qcom_scm *scm) 2351 { 2352 return 0; 2353 } 2354 2355 #endif /* CONFIG_QCOM_QSEECOM */ 2356 2357 /** 2358 * qcom_scm_qtee_invoke_smc() - Invoke a QTEE object. 2359 * @inbuf: start address of memory area used for inbound buffer. 2360 * @inbuf_size: size of the memory area used for inbound buffer. 2361 * @outbuf: start address of memory area used for outbound buffer. 2362 * @outbuf_size: size of the memory area used for outbound buffer. 2363 * @result: result of QTEE object invocation. 2364 * @response_type: response type returned by QTEE. 2365 * 2366 * @response_type determines how the contents of @inbuf and @outbuf 2367 * should be processed. 2368 * 2369 * Return: On success, return 0 or <0 on failure. 2370 */ 2371 int qcom_scm_qtee_invoke_smc(phys_addr_t inbuf, size_t inbuf_size, 2372 phys_addr_t outbuf, size_t outbuf_size, 2373 u64 *result, u64 *response_type) 2374 { 2375 struct qcom_scm_desc desc = { 2376 .svc = QCOM_SCM_SVC_SMCINVOKE, 2377 .cmd = QCOM_SCM_SMCINVOKE_INVOKE, 2378 .owner = ARM_SMCCC_OWNER_TRUSTED_OS, 2379 .args[0] = inbuf, 2380 .args[1] = inbuf_size, 2381 .args[2] = outbuf, 2382 .args[3] = outbuf_size, 2383 .arginfo = QCOM_SCM_ARGS(4, QCOM_SCM_RW, QCOM_SCM_VAL, 2384 QCOM_SCM_RW, QCOM_SCM_VAL), 2385 }; 2386 struct qcom_scm_res res; 2387 int ret; 2388 2389 ret = qcom_scm_call(__scm->dev, &desc, &res); 2390 if (ret) 2391 return ret; 2392 2393 if (response_type) 2394 *response_type = res.result[0]; 2395 2396 if (result) 2397 *result = res.result[1]; 2398 2399 return 0; 2400 } 2401 EXPORT_SYMBOL(qcom_scm_qtee_invoke_smc); 2402 2403 /** 2404 * qcom_scm_qtee_callback_response() - Submit response for callback request. 2405 * @buf: start address of memory area used for outbound buffer. 2406 * @buf_size: size of the memory area used for outbound buffer. 2407 * @result: Result of QTEE object invocation. 2408 * @response_type: Response type returned by QTEE. 2409 * 2410 * @response_type determines how the contents of @buf should be processed. 2411 * 2412 * Return: On success, return 0 or <0 on failure. 2413 */ 2414 int qcom_scm_qtee_callback_response(phys_addr_t buf, size_t buf_size, 2415 u64 *result, u64 *response_type) 2416 { 2417 struct qcom_scm_desc desc = { 2418 .svc = QCOM_SCM_SVC_SMCINVOKE, 2419 .cmd = QCOM_SCM_SMCINVOKE_CB_RSP, 2420 .owner = ARM_SMCCC_OWNER_TRUSTED_OS, 2421 .args[0] = buf, 2422 .args[1] = buf_size, 2423 .arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_RW, QCOM_SCM_VAL), 2424 }; 2425 struct qcom_scm_res res; 2426 int ret; 2427 2428 ret = qcom_scm_call(__scm->dev, &desc, &res); 2429 if (ret) 2430 return ret; 2431 2432 if (response_type) 2433 *response_type = res.result[0]; 2434 2435 if (result) 2436 *result = res.result[1]; 2437 2438 return 0; 2439 } 2440 EXPORT_SYMBOL(qcom_scm_qtee_callback_response); 2441 2442 static void qcom_scm_gunyah_wdt_free(void *data) 2443 { 2444 struct platform_device *gunyah_wdt_dev = data; 2445 2446 platform_device_unregister(gunyah_wdt_dev); 2447 } 2448 2449 static void qcom_scm_gunyah_wdt_init(struct qcom_scm *scm) 2450 { 2451 struct platform_device *gunyah_wdt_dev; 2452 struct device_node *np; 2453 bool of_wdt_available; 2454 int i; 2455 static const uuid_t gunyah_uuid = UUID_INIT(0xc1d58fcd, 0xa453, 0x5fdb, 2456 0x92, 0x65, 0xce, 0x36, 2457 0x67, 0x3d, 0x5f, 0x14); 2458 static const char * const of_wdt_compatible[] = { 2459 "qcom,kpss-wdt", 2460 "arm,sbsa-gwdt", 2461 }; 2462 2463 /* Bail out if we are not running under Gunyah */ 2464 if (!IS_ENABLED(CONFIG_HAVE_ARM_SMCCC_DISCOVERY) || 2465 !arm_smccc_hypervisor_has_uuid(&gunyah_uuid)) 2466 return; 2467 2468 /* 2469 * Gunyah emulates either of Qualcomm watchdog or ARM SBSA watchdog on 2470 * newer platforms. Bail out if we find them in the devicetree. 2471 */ 2472 for (i = 0; i < ARRAY_SIZE(of_wdt_compatible); i++) { 2473 np = of_find_compatible_node(NULL, NULL, of_wdt_compatible[i]); 2474 of_wdt_available = of_device_is_available(np); 2475 of_node_put(np); 2476 if (of_wdt_available) 2477 return; 2478 } 2479 2480 gunyah_wdt_dev = platform_device_register_simple("gunyah-wdt", -1, 2481 NULL, 0); 2482 if (IS_ERR(gunyah_wdt_dev)) { 2483 dev_err(scm->dev, "Failed to register Gunyah watchdog device: %ld\n", 2484 PTR_ERR(gunyah_wdt_dev)); 2485 return; 2486 } 2487 2488 devm_add_action_or_reset(scm->dev, qcom_scm_gunyah_wdt_free, 2489 gunyah_wdt_dev); 2490 } 2491 2492 static void qcom_scm_qtee_free(void *data) 2493 { 2494 struct platform_device *qtee_dev = data; 2495 2496 platform_device_unregister(qtee_dev); 2497 } 2498 2499 static void qcom_scm_qtee_init(struct qcom_scm *scm) 2500 { 2501 struct platform_device *qtee_dev; 2502 u64 result, response_type; 2503 int ret; 2504 2505 /* 2506 * Probe for smcinvoke support. This will fail due to invalid buffers, 2507 * but first, it checks whether the call is supported in QTEE syscall 2508 * handler. If it is not supported, -EIO is returned. 2509 */ 2510 ret = qcom_scm_qtee_invoke_smc(0, 0, 0, 0, &result, &response_type); 2511 if (ret == -EIO) 2512 return; 2513 2514 /* Setup QTEE interface device. */ 2515 qtee_dev = platform_device_register_data(scm->dev, "qcomtee", 2516 PLATFORM_DEVID_NONE, NULL, 0); 2517 if (IS_ERR(qtee_dev)) 2518 return; 2519 2520 devm_add_action_or_reset(scm->dev, qcom_scm_qtee_free, qtee_dev); 2521 } 2522 2523 /** 2524 * qcom_scm_is_available() - Checks if SCM is available 2525 */ 2526 bool qcom_scm_is_available(void) 2527 { 2528 /* Paired with smp_store_release() in qcom_scm_probe */ 2529 return !!smp_load_acquire(&__scm); 2530 } 2531 EXPORT_SYMBOL_GPL(qcom_scm_is_available); 2532 2533 static int qcom_scm_fill_irq_fwspec_params(struct irq_fwspec *fwspec, u32 hwirq) 2534 { 2535 if (hwirq >= GIC_SPI_BASE && hwirq <= GIC_MAX_SPI) { 2536 fwspec->param[0] = GIC_SPI; 2537 fwspec->param[1] = hwirq - GIC_SPI_BASE; 2538 } else if (hwirq >= GIC_ESPI_BASE && hwirq <= GIC_MAX_ESPI) { 2539 fwspec->param[0] = GIC_ESPI; 2540 fwspec->param[1] = hwirq - GIC_ESPI_BASE; 2541 } else { 2542 WARN(1, "Unexpected hwirq: %d\n", hwirq); 2543 return -ENXIO; 2544 } 2545 2546 fwspec->param[2] = IRQ_TYPE_EDGE_RISING; 2547 fwspec->param_count = 3; 2548 2549 return 0; 2550 } 2551 2552 static int qcom_scm_query_waitq_count(struct qcom_scm *scm) 2553 { 2554 struct qcom_scm_desc desc = { 2555 .svc = QCOM_SCM_SVC_WAITQ, 2556 .cmd = QCOM_SCM_WAITQ_GET_INFO, 2557 .owner = ARM_SMCCC_OWNER_SIP 2558 }; 2559 struct qcom_scm_res res; 2560 int ret; 2561 2562 ret = qcom_scm_call_atomic(scm->dev, &desc, &res); 2563 if (ret) 2564 return ret; 2565 2566 return res.result[0] & GENMASK(7, 0); 2567 } 2568 2569 static int qcom_scm_get_waitq_irq(struct qcom_scm *scm) 2570 { 2571 struct qcom_scm_desc desc = { 2572 .svc = QCOM_SCM_SVC_WAITQ, 2573 .cmd = QCOM_SCM_WAITQ_GET_INFO, 2574 .owner = ARM_SMCCC_OWNER_SIP 2575 }; 2576 struct device_node *parent_irq_node; 2577 struct irq_fwspec fwspec; 2578 struct qcom_scm_res res; 2579 u32 hwirq; 2580 int ret; 2581 2582 ret = qcom_scm_call_atomic(scm->dev, &desc, &res); 2583 if (ret) 2584 return ret; 2585 2586 hwirq = res.result[1] & GENMASK(15, 0); 2587 ret = qcom_scm_fill_irq_fwspec_params(&fwspec, hwirq); 2588 if (ret) 2589 return ret; 2590 2591 parent_irq_node = of_irq_find_parent(scm->dev->of_node); 2592 if (!parent_irq_node) 2593 return -ENODEV; 2594 2595 fwspec.fwnode = of_fwnode_handle(parent_irq_node); 2596 2597 return irq_create_fwspec_mapping(&fwspec); 2598 } 2599 2600 static struct completion *qcom_scm_get_completion(u32 wq_ctx) 2601 { 2602 struct completion *wq; 2603 2604 if (WARN_ON_ONCE(wq_ctx >= __scm->wq_cnt)) 2605 return ERR_PTR(-EINVAL); 2606 2607 wq = &__scm->waitq_comps[wq_ctx]; 2608 2609 return wq; 2610 } 2611 2612 int qcom_scm_wait_for_wq_completion(u32 wq_ctx) 2613 { 2614 struct completion *wq; 2615 2616 wq = qcom_scm_get_completion(wq_ctx); 2617 if (IS_ERR(wq)) 2618 return PTR_ERR(wq); 2619 2620 wait_for_completion_state(wq, TASK_IDLE); 2621 2622 return 0; 2623 } 2624 2625 static int qcom_scm_waitq_wakeup(unsigned int wq_ctx) 2626 { 2627 struct completion *wq; 2628 2629 wq = qcom_scm_get_completion(wq_ctx); 2630 if (IS_ERR(wq)) 2631 return PTR_ERR(wq); 2632 2633 complete(wq); 2634 2635 return 0; 2636 } 2637 2638 static irqreturn_t qcom_scm_irq_handler(int irq, void *data) 2639 { 2640 int ret; 2641 struct qcom_scm *scm = data; 2642 u32 wq_ctx, flags, more_pending = 0; 2643 2644 do { 2645 ret = scm_get_wq_ctx(&wq_ctx, &flags, &more_pending); 2646 if (ret) { 2647 dev_err(scm->dev, "GET_WQ_CTX SMC call failed: %d\n", ret); 2648 goto out; 2649 } 2650 2651 if (flags != QCOM_SMC_WAITQ_FLAG_WAKE_ONE) { 2652 dev_err(scm->dev, "Invalid flags received for wq_ctx: %u\n", flags); 2653 goto out; 2654 } 2655 2656 ret = qcom_scm_waitq_wakeup(wq_ctx); 2657 if (ret) 2658 goto out; 2659 } while (more_pending); 2660 2661 out: 2662 return IRQ_HANDLED; 2663 } 2664 2665 static int get_download_mode(char *buffer, const struct kernel_param *kp) 2666 { 2667 if (download_mode >= ARRAY_SIZE(download_mode_name)) 2668 return sysfs_emit(buffer, "unknown mode\n"); 2669 2670 return sysfs_emit(buffer, "%s\n", download_mode_name[download_mode]); 2671 } 2672 2673 static int set_download_mode(const char *val, const struct kernel_param *kp) 2674 { 2675 bool tmp; 2676 int ret; 2677 2678 ret = sysfs_match_string(download_mode_name, val); 2679 if (ret < 0) { 2680 ret = kstrtobool(val, &tmp); 2681 if (ret < 0) { 2682 pr_err("qcom_scm: err: %d\n", ret); 2683 return ret; 2684 } 2685 2686 ret = tmp ? 1 : 0; 2687 } 2688 2689 download_mode = ret; 2690 if (__scm) 2691 qcom_scm_set_download_mode(download_mode); 2692 2693 return 0; 2694 } 2695 2696 static const struct kernel_param_ops download_mode_param_ops = { 2697 .get = get_download_mode, 2698 .set = set_download_mode, 2699 }; 2700 2701 module_param_cb(download_mode, &download_mode_param_ops, NULL, 0644); 2702 MODULE_PARM_DESC(download_mode, "download mode: off/0/N for no dump mode, full/on/1/Y for full dump mode, mini for minidump mode and full,mini for both full and minidump mode together are acceptable values"); 2703 2704 static int qcom_scm_probe(struct platform_device *pdev) 2705 { 2706 struct qcom_tzmem_pool_config pool_config; 2707 struct qcom_scm *scm; 2708 int irq, ret; 2709 int i; 2710 2711 scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL); 2712 if (!scm) 2713 return -ENOMEM; 2714 2715 scm->dev = &pdev->dev; 2716 ret = qcom_scm_find_dload_address(&pdev->dev, &scm->dload_mode_addr); 2717 if (ret < 0) 2718 return ret; 2719 2720 mutex_init(&scm->scm_bw_lock); 2721 2722 scm->path = devm_of_icc_get(&pdev->dev, NULL); 2723 if (IS_ERR(scm->path)) 2724 return dev_err_probe(&pdev->dev, PTR_ERR(scm->path), 2725 "failed to acquire interconnect path\n"); 2726 2727 scm->core_clk = devm_clk_get_optional(&pdev->dev, "core"); 2728 if (IS_ERR(scm->core_clk)) 2729 return PTR_ERR(scm->core_clk); 2730 2731 scm->iface_clk = devm_clk_get_optional(&pdev->dev, "iface"); 2732 if (IS_ERR(scm->iface_clk)) 2733 return PTR_ERR(scm->iface_clk); 2734 2735 scm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); 2736 if (IS_ERR(scm->bus_clk)) 2737 return PTR_ERR(scm->bus_clk); 2738 2739 scm->reset.ops = &qcom_scm_pas_reset_ops; 2740 scm->reset.nr_resets = 1; 2741 scm->reset.of_node = pdev->dev.of_node; 2742 ret = devm_reset_controller_register(&pdev->dev, &scm->reset); 2743 if (ret) 2744 return ret; 2745 2746 /* vote for max clk rate for highest performance */ 2747 ret = clk_set_rate(scm->core_clk, INT_MAX); 2748 if (ret) 2749 return ret; 2750 2751 ret = of_reserved_mem_device_init(scm->dev); 2752 if (ret && ret != -ENODEV) 2753 return dev_err_probe(scm->dev, ret, 2754 "Failed to setup the reserved memory region for TZ mem\n"); 2755 2756 ret = qcom_tzmem_enable(scm->dev); 2757 if (ret) 2758 return dev_err_probe(scm->dev, ret, 2759 "Failed to enable the TrustZone memory allocator\n"); 2760 2761 memset(&pool_config, 0, sizeof(pool_config)); 2762 pool_config.initial_size = 0; 2763 pool_config.policy = QCOM_TZMEM_POLICY_ON_DEMAND; 2764 pool_config.max_size = SZ_256K; 2765 2766 scm->mempool = devm_qcom_tzmem_pool_new(scm->dev, &pool_config); 2767 if (IS_ERR(scm->mempool)) 2768 return dev_err_probe(scm->dev, PTR_ERR(scm->mempool), 2769 "Failed to create the SCM memory pool\n"); 2770 2771 ret = qcom_scm_query_waitq_count(scm); 2772 scm->wq_cnt = ret < 0 ? QCOM_SCM_DEFAULT_WAITQ_COUNT : ret; 2773 scm->waitq_comps = devm_kcalloc(&pdev->dev, scm->wq_cnt, sizeof(*scm->waitq_comps), 2774 GFP_KERNEL); 2775 if (!scm->waitq_comps) 2776 return -ENOMEM; 2777 2778 for (i = 0; i < scm->wq_cnt; i++) 2779 init_completion(&scm->waitq_comps[i]); 2780 2781 irq = qcom_scm_get_waitq_irq(scm); 2782 if (irq < 0) 2783 irq = platform_get_irq_optional(pdev, 0); 2784 2785 if (irq < 0) { 2786 if (irq != -ENXIO) 2787 return irq; 2788 } else { 2789 ret = devm_request_threaded_irq(scm->dev, irq, NULL, qcom_scm_irq_handler, 2790 IRQF_ONESHOT, "qcom-scm", scm); 2791 if (ret < 0) 2792 return dev_err_probe(scm->dev, ret, 2793 "Failed to request qcom-scm irq\n"); 2794 } 2795 2796 /* 2797 * Paired with smp_load_acquire() in qcom_scm_is_available(). 2798 * 2799 * This marks the SCM API as ready to accept user calls and can only 2800 * be called after the TrustZone memory pool is initialized and the 2801 * waitqueue interrupt requested. 2802 */ 2803 smp_store_release(&__scm, scm); 2804 2805 __get_convention(); 2806 2807 if (qcom_scm_is_pas_available()) { 2808 qcom_pas_ops_scm.dev = scm->dev; 2809 qcom_pas_ops_register(&qcom_pas_ops_scm); 2810 } 2811 2812 /* 2813 * If "download mode" is requested, from this point on warmboot 2814 * will cause the boot stages to enter download mode, unless 2815 * disabled below by a clean shutdown/reboot. 2816 */ 2817 qcom_scm_set_download_mode(download_mode); 2818 2819 /* 2820 * Disable SDI if indicated by DT that it is enabled by default. 2821 */ 2822 if (of_property_read_bool(pdev->dev.of_node, "qcom,sdi-enabled") || !download_mode) 2823 qcom_scm_disable_sdi(); 2824 2825 /* 2826 * Initialize the QSEECOM interface. 2827 * 2828 * Note: QSEECOM is fairly self-contained and this only adds the 2829 * interface device (the driver of which does most of the heavy 2830 * lifting). So any errors returned here should be either -ENOMEM or 2831 * -EINVAL (with the latter only in case there's a bug in our code). 2832 * This means that there is no need to bring down the whole SCM driver. 2833 * Just log the error instead and let SCM live. 2834 */ 2835 ret = qcom_scm_qseecom_init(scm); 2836 WARN(ret < 0, "failed to initialize qseecom: %d\n", ret); 2837 2838 /* Initialize the QTEE object interface. */ 2839 qcom_scm_qtee_init(scm); 2840 2841 /* Initialize the Gunyah watchdog platform device. */ 2842 qcom_scm_gunyah_wdt_init(scm); 2843 2844 return 0; 2845 } 2846 2847 static void qcom_scm_shutdown(struct platform_device *pdev) 2848 { 2849 /* Clean shutdown, disable download mode to allow normal restart */ 2850 qcom_scm_set_download_mode(QCOM_DLOAD_NODUMP); 2851 qcom_pas_ops_unregister(); 2852 } 2853 2854 static const struct of_device_id qcom_scm_dt_match[] = { 2855 { .compatible = "qcom,scm" }, 2856 2857 /* Legacy entries kept for backwards compatibility */ 2858 { .compatible = "qcom,scm-apq8064" }, 2859 { .compatible = "qcom,scm-apq8084" }, 2860 { .compatible = "qcom,scm-ipq4019" }, 2861 { .compatible = "qcom,scm-msm8953" }, 2862 { .compatible = "qcom,scm-msm8974" }, 2863 { .compatible = "qcom,scm-msm8996" }, 2864 {} 2865 }; 2866 MODULE_DEVICE_TABLE(of, qcom_scm_dt_match); 2867 2868 static struct platform_driver qcom_scm_driver = { 2869 .driver = { 2870 .name = "qcom_scm", 2871 .of_match_table = qcom_scm_dt_match, 2872 .suppress_bind_attrs = true, 2873 }, 2874 .probe = qcom_scm_probe, 2875 .shutdown = qcom_scm_shutdown, 2876 }; 2877 2878 static int __init qcom_scm_init(void) 2879 { 2880 return platform_driver_register(&qcom_scm_driver); 2881 } 2882 subsys_initcall(qcom_scm_init); 2883 2884 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SCM driver"); 2885 MODULE_LICENSE("GPL v2"); 2886