1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/efi.h> 3 4 #include <asm/boot.h> 5 #include <asm/cpuid/api.h> 6 #include <asm/desc.h> 7 #include <asm/efi.h> 8 9 #include "efistub.h" 10 #include "x86-stub.h" 11 12 bool efi_no5lvl; 13 14 static void (*la57_toggle)(void *cr3); 15 16 static const struct desc_struct gdt[] = { 17 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff), 18 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE64, 0, 0xfffff), 19 }; 20 21 /* 22 * Enabling (or disabling) 5 level paging is tricky, because it can only be 23 * done from 32-bit mode with paging disabled. This means not only that the 24 * code itself must be running from 32-bit addressable physical memory, but 25 * also that the root page table must be 32-bit addressable, as programming 26 * a 64-bit value into CR3 when running in 32-bit mode is not supported. 27 */ 28 efi_status_t efi_setup_5level_paging(void) 29 { 30 u8 tmpl_size = (u8 *)&trampoline_ljmp_imm_offset - (u8 *)&trampoline_32bit_src; 31 efi_status_t status; 32 u8 *la57_code; 33 34 if (!efi_is_64bit()) 35 return EFI_SUCCESS; 36 37 /* check for 5 level paging support */ 38 if (native_cpuid_eax(0) < 7 || 39 !(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)))) 40 return EFI_SUCCESS; 41 42 /* allocate some 32-bit addressable memory for code and a page table */ 43 status = efi_allocate_pages(2 * PAGE_SIZE, (unsigned long *)&la57_code, 44 U32_MAX); 45 if (status != EFI_SUCCESS) 46 return status; 47 48 la57_toggle = memcpy(la57_code, trampoline_32bit_src, tmpl_size); 49 memset(la57_code + tmpl_size, 0x90, PAGE_SIZE - tmpl_size); 50 51 /* 52 * To avoid the need to allocate a 32-bit addressable stack, the 53 * trampoline uses a LJMP instruction to switch back to long mode. 54 * LJMP takes an absolute destination address, which needs to be 55 * fixed up at runtime. 56 */ 57 *(u32 *)&la57_code[trampoline_ljmp_imm_offset] += (unsigned long)la57_code; 58 59 efi_adjust_memory_range_protection((unsigned long)la57_toggle, PAGE_SIZE); 60 61 return EFI_SUCCESS; 62 } 63 64 void efi_5level_switch(void) 65 { 66 bool want_la57 = !efi_no5lvl; 67 bool have_la57 = native_read_cr4() & X86_CR4_LA57; 68 bool need_toggle = want_la57 ^ have_la57; 69 u64 *pgt = (void *)la57_toggle + PAGE_SIZE; 70 pgd_t *cr3 = (pgd_t *)native_read_cr3_pa(); 71 u64 *new_cr3; 72 73 if (!la57_toggle || !need_toggle) 74 return; 75 76 if (!have_la57) { 77 /* 78 * 5 level paging will be enabled, so a root level page needs 79 * to be allocated from the 32-bit addressable physical region, 80 * with its first entry referring to the existing hierarchy. 81 */ 82 new_cr3 = memset(pgt, 0, PAGE_SIZE); 83 new_cr3[0] = (u64)cr3 | _PAGE_TABLE_NOENC; 84 } else { 85 /* take the new root table pointer from the current entry #0 */ 86 new_cr3 = (u64 *)(native_pgd_val(cr3[0]) & PTE_PFN_MASK); 87 88 /* copy the new root table if it is not 32-bit addressable */ 89 if ((u64)new_cr3 > U32_MAX) 90 new_cr3 = memcpy(pgt, new_cr3, PAGE_SIZE); 91 } 92 93 native_load_gdt(&(struct desc_ptr){ sizeof(gdt) - 1, (u64)gdt }); 94 95 la57_toggle(new_cr3); 96 } 97