1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * sm5502.h 4 * 5 * Copyright (c) 2014 Samsung Electronics Co., Ltd 6 */ 7 8 #ifndef __LINUX_EXTCON_SM5502_H 9 #define __LINUX_EXTCON_SM5502_H 10 11 enum sm5502_types { 12 TYPE_SM5502, 13 }; 14 15 /* SM5502 registers */ 16 enum sm5502_reg { 17 SM5502_REG_DEVICE_ID = 0x01, 18 SM5502_REG_CONTROL, 19 SM5502_REG_INT1, 20 SM5502_REG_INT2, 21 SM5502_REG_INTMASK1, 22 SM5502_REG_INTMASK2, 23 SM5502_REG_ADC, 24 SM5502_REG_TIMING_SET1, 25 SM5502_REG_TIMING_SET2, 26 SM5502_REG_DEV_TYPE1, 27 SM5502_REG_DEV_TYPE2, 28 SM5502_REG_BUTTON1, 29 SM5502_REG_BUTTON2, 30 SM5502_REG_CAR_KIT_STATUS, 31 SM5502_REG_RSVD1, 32 SM5502_REG_RSVD2, 33 SM5502_REG_RSVD3, 34 SM5502_REG_RSVD4, 35 SM5502_REG_MANUAL_SW1, 36 SM5502_REG_MANUAL_SW2, 37 SM5502_REG_DEV_TYPE3, 38 SM5502_REG_RSVD5, 39 SM5502_REG_RSVD6, 40 SM5502_REG_RSVD7, 41 SM5502_REG_RSVD8, 42 SM5502_REG_RSVD9, 43 SM5502_REG_RESET, 44 SM5502_REG_RSVD10, 45 SM5502_REG_RESERVED_ID1, 46 SM5502_REG_RSVD11, 47 SM5502_REG_RSVD12, 48 SM5502_REG_RESERVED_ID2, 49 SM5502_REG_RSVD13, 50 SM5502_REG_OCP, 51 SM5502_REG_RSVD14, 52 SM5502_REG_RSVD15, 53 SM5502_REG_RSVD16, 54 SM5502_REG_RSVD17, 55 SM5502_REG_RSVD18, 56 SM5502_REG_RSVD19, 57 SM5502_REG_RSVD20, 58 SM5502_REG_RSVD21, 59 SM5502_REG_RSVD22, 60 SM5502_REG_RSVD23, 61 SM5502_REG_RSVD24, 62 SM5502_REG_RSVD25, 63 SM5502_REG_RSVD26, 64 SM5502_REG_RSVD27, 65 SM5502_REG_RSVD28, 66 SM5502_REG_RSVD29, 67 SM5502_REG_RSVD30, 68 SM5502_REG_RSVD31, 69 SM5502_REG_RSVD32, 70 SM5502_REG_RSVD33, 71 SM5502_REG_RSVD34, 72 SM5502_REG_RSVD35, 73 SM5502_REG_RSVD36, 74 SM5502_REG_RESERVED_ID3, 75 76 SM5502_REG_END, 77 }; 78 79 /* Define SM5502 MASK/SHIFT constant */ 80 #define SM5502_REG_DEVICE_ID_VENDOR_SHIFT 0 81 #define SM5502_REG_DEVICE_ID_VERSION_SHIFT 3 82 #define SM5502_REG_DEVICE_ID_VENDOR_MASK (0x3 << SM5502_REG_DEVICE_ID_VENDOR_SHIFT) 83 #define SM5502_REG_DEVICE_ID_VERSION_MASK (0x1f << SM5502_REG_DEVICE_ID_VERSION_SHIFT) 84 85 #define SM5502_REG_CONTROL_MASK_INT_SHIFT 0 86 #define SM5502_REG_CONTROL_WAIT_SHIFT 1 87 #define SM5502_REG_CONTROL_MANUAL_SW_SHIFT 2 88 #define SM5502_REG_CONTROL_RAW_DATA_SHIFT 3 89 #define SM5502_REG_CONTROL_SW_OPEN_SHIFT 4 90 #define SM5502_REG_CONTROL_MASK_INT_MASK (0x1 << SM5502_REG_CONTROL_MASK_INT_SHIFT) 91 #define SM5502_REG_CONTROL_WAIT_MASK (0x1 << SM5502_REG_CONTROL_WAIT_SHIFT) 92 #define SM5502_REG_CONTROL_MANUAL_SW_MASK (0x1 << SM5502_REG_CONTROL_MANUAL_SW_SHIFT) 93 #define SM5502_REG_CONTROL_RAW_DATA_MASK (0x1 << SM5502_REG_CONTROL_RAW_DATA_SHIFT) 94 #define SM5502_REG_CONTROL_SW_OPEN_MASK (0x1 << SM5502_REG_CONTROL_SW_OPEN_SHIFT) 95 96 #define SM5502_REG_INTM1_ATTACH_SHIFT 0 97 #define SM5502_REG_INTM1_DETACH_SHIFT 1 98 #define SM5502_REG_INTM1_KP_SHIFT 2 99 #define SM5502_REG_INTM1_LKP_SHIFT 3 100 #define SM5502_REG_INTM1_LKR_SHIFT 4 101 #define SM5502_REG_INTM1_OVP_EVENT_SHIFT 5 102 #define SM5502_REG_INTM1_OCP_EVENT_SHIFT 6 103 #define SM5502_REG_INTM1_OVP_OCP_DIS_SHIFT 7 104 #define SM5502_REG_INTM1_ATTACH_MASK (0x1 << SM5502_REG_INTM1_ATTACH_SHIFT) 105 #define SM5502_REG_INTM1_DETACH_MASK (0x1 << SM5502_REG_INTM1_DETACH_SHIFT) 106 #define SM5502_REG_INTM1_KP_MASK (0x1 << SM5502_REG_INTM1_KP_SHIFT) 107 #define SM5502_REG_INTM1_LKP_MASK (0x1 << SM5502_REG_INTM1_LKP_SHIFT) 108 #define SM5502_REG_INTM1_LKR_MASK (0x1 << SM5502_REG_INTM1_LKR_SHIFT) 109 #define SM5502_REG_INTM1_OVP_EVENT_MASK (0x1 << SM5502_REG_INTM1_OVP_EVENT_SHIFT) 110 #define SM5502_REG_INTM1_OCP_EVENT_MASK (0x1 << SM5502_REG_INTM1_OCP_EVENT_SHIFT) 111 #define SM5502_REG_INTM1_OVP_OCP_DIS_MASK (0x1 << SM5502_REG_INTM1_OVP_OCP_DIS_SHIFT) 112 113 #define SM5502_REG_INTM2_VBUS_DET_SHIFT 0 114 #define SM5502_REG_INTM2_REV_ACCE_SHIFT 1 115 #define SM5502_REG_INTM2_ADC_CHG_SHIFT 2 116 #define SM5502_REG_INTM2_STUCK_KEY_SHIFT 3 117 #define SM5502_REG_INTM2_STUCK_KEY_RCV_SHIFT 4 118 #define SM5502_REG_INTM2_MHL_SHIFT 5 119 #define SM5502_REG_INTM2_VBUS_DET_MASK (0x1 << SM5502_REG_INTM2_VBUS_DET_SHIFT) 120 #define SM5502_REG_INTM2_REV_ACCE_MASK (0x1 << SM5502_REG_INTM2_REV_ACCE_SHIFT) 121 #define SM5502_REG_INTM2_ADC_CHG_MASK (0x1 << SM5502_REG_INTM2_ADC_CHG_SHIFT) 122 #define SM5502_REG_INTM2_STUCK_KEY_MASK (0x1 << SM5502_REG_INTM2_STUCK_KEY_SHIFT) 123 #define SM5502_REG_INTM2_STUCK_KEY_RCV_MASK (0x1 << SM5502_REG_INTM2_STUCK_KEY_RCV_SHIFT) 124 #define SM5502_REG_INTM2_MHL_MASK (0x1 << SM5502_REG_INTM2_MHL_SHIFT) 125 126 #define SM5502_REG_ADC_SHIFT 0 127 #define SM5502_REG_ADC_MASK (0x1f << SM5502_REG_ADC_SHIFT) 128 129 #define SM5502_REG_TIMING_SET1_KEY_PRESS_SHIFT 4 130 #define SM5502_REG_TIMING_SET1_KEY_PRESS_MASK (0xf << SM5502_REG_TIMING_SET1_KEY_PRESS_SHIFT) 131 #define TIMING_KEY_PRESS_100MS 0x0 132 #define TIMING_KEY_PRESS_200MS 0x1 133 #define TIMING_KEY_PRESS_300MS 0x2 134 #define TIMING_KEY_PRESS_400MS 0x3 135 #define TIMING_KEY_PRESS_500MS 0x4 136 #define TIMING_KEY_PRESS_600MS 0x5 137 #define TIMING_KEY_PRESS_700MS 0x6 138 #define TIMING_KEY_PRESS_800MS 0x7 139 #define TIMING_KEY_PRESS_900MS 0x8 140 #define TIMING_KEY_PRESS_1000MS 0x9 141 #define SM5502_REG_TIMING_SET1_ADC_DET_SHIFT 0 142 #define SM5502_REG_TIMING_SET1_ADC_DET_MASK (0xf << SM5502_REG_TIMING_SET1_ADC_DET_SHIFT) 143 #define TIMING_ADC_DET_50MS 0x0 144 #define TIMING_ADC_DET_100MS 0x1 145 #define TIMING_ADC_DET_150MS 0x2 146 #define TIMING_ADC_DET_200MS 0x3 147 #define TIMING_ADC_DET_300MS 0x4 148 #define TIMING_ADC_DET_400MS 0x5 149 #define TIMING_ADC_DET_500MS 0x6 150 #define TIMING_ADC_DET_600MS 0x7 151 #define TIMING_ADC_DET_700MS 0x8 152 #define TIMING_ADC_DET_800MS 0x9 153 #define TIMING_ADC_DET_900MS 0xA 154 #define TIMING_ADC_DET_1000MS 0xB 155 156 #define SM5502_REG_TIMING_SET2_SW_WAIT_SHIFT 4 157 #define SM5502_REG_TIMING_SET2_SW_WAIT_MASK (0xf << SM5502_REG_TIMING_SET2_SW_WAIT_SHIFT) 158 #define TIMING_SW_WAIT_10MS 0x0 159 #define TIMING_SW_WAIT_30MS 0x1 160 #define TIMING_SW_WAIT_50MS 0x2 161 #define TIMING_SW_WAIT_70MS 0x3 162 #define TIMING_SW_WAIT_90MS 0x4 163 #define TIMING_SW_WAIT_110MS 0x5 164 #define TIMING_SW_WAIT_130MS 0x6 165 #define TIMING_SW_WAIT_150MS 0x7 166 #define TIMING_SW_WAIT_170MS 0x8 167 #define TIMING_SW_WAIT_190MS 0x9 168 #define TIMING_SW_WAIT_210MS 0xA 169 #define SM5502_REG_TIMING_SET2_LONG_KEY_SHIFT 0 170 #define SM5502_REG_TIMING_SET2_LONG_KEY_MASK (0xf << SM5502_REG_TIMING_SET2_LONG_KEY_SHIFT) 171 #define TIMING_LONG_KEY_300MS 0x0 172 #define TIMING_LONG_KEY_400MS 0x1 173 #define TIMING_LONG_KEY_500MS 0x2 174 #define TIMING_LONG_KEY_600MS 0x3 175 #define TIMING_LONG_KEY_700MS 0x4 176 #define TIMING_LONG_KEY_800MS 0x5 177 #define TIMING_LONG_KEY_900MS 0x6 178 #define TIMING_LONG_KEY_1000MS 0x7 179 #define TIMING_LONG_KEY_1100MS 0x8 180 #define TIMING_LONG_KEY_1200MS 0x9 181 #define TIMING_LONG_KEY_1300MS 0xA 182 #define TIMING_LONG_KEY_1400MS 0xB 183 #define TIMING_LONG_KEY_1500MS 0xC 184 185 #define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_SHIFT 0 186 #define SM5502_REG_DEV_TYPE1_AUDIO_TYPE2_SHIFT 1 187 #define SM5502_REG_DEV_TYPE1_USB_SDP_SHIFT 2 188 #define SM5502_REG_DEV_TYPE1_UART_SHIFT 3 189 #define SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_SHIFT 4 190 #define SM5502_REG_DEV_TYPE1_USB_CHG_SHIFT 5 191 #define SM5502_REG_DEV_TYPE1_DEDICATED_CHG_SHIFT 6 192 #define SM5502_REG_DEV_TYPE1_USB_OTG_SHIFT 7 193 #define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_MASK (0x1 << SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_SHIFT) 194 #define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1__MASK (0x1 << SM5502_REG_DEV_TYPE1_AUDIO_TYPE2_SHIFT) 195 #define SM5502_REG_DEV_TYPE1_USB_SDP_MASK (0x1 << SM5502_REG_DEV_TYPE1_USB_SDP_SHIFT) 196 #define SM5502_REG_DEV_TYPE1_UART_MASK (0x1 << SM5502_REG_DEV_TYPE1_UART_SHIFT) 197 #define SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_MASK (0x1 << SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_SHIFT) 198 #define SM5502_REG_DEV_TYPE1_USB_CHG_MASK (0x1 << SM5502_REG_DEV_TYPE1_USB_CHG_SHIFT) 199 #define SM5502_REG_DEV_TYPE1_DEDICATED_CHG_MASK (0x1 << SM5502_REG_DEV_TYPE1_DEDICATED_CHG_SHIFT) 200 #define SM5502_REG_DEV_TYPE1_USB_OTG_MASK (0x1 << SM5502_REG_DEV_TYPE1_USB_OTG_SHIFT) 201 202 #define SM5502_REG_DEV_TYPE2_JIG_USB_ON_SHIFT 0 203 #define SM5502_REG_DEV_TYPE2_JIG_USB_OFF_SHIFT 1 204 #define SM5502_REG_DEV_TYPE2_JIG_UART_ON_SHIFT 2 205 #define SM5502_REG_DEV_TYPE2_JIG_UART_OFF_SHIFT 3 206 #define SM5502_REG_DEV_TYPE2_PPD_SHIFT 4 207 #define SM5502_REG_DEV_TYPE2_TTY_SHIFT 5 208 #define SM5502_REG_DEV_TYPE2_AV_CABLE_SHIFT 6 209 #define SM5502_REG_DEV_TYPE2_JIG_USB_ON_MASK (0x1 << SM5502_REG_DEV_TYPE2_JIG_USB_ON_SHIFT) 210 #define SM5502_REG_DEV_TYPE2_JIG_USB_OFF_MASK (0x1 << SM5502_REG_DEV_TYPE2_JIG_USB_OFF_SHIFT) 211 #define SM5502_REG_DEV_TYPE2_JIG_UART_ON_MASK (0x1 << SM5502_REG_DEV_TYPE2_JIG_UART_ON_SHIFT) 212 #define SM5502_REG_DEV_TYPE2_JIG_UART_OFF_MASK (0x1 << SM5502_REG_DEV_TYPE2_JIG_UART_OFF_SHIFT) 213 #define SM5502_REG_DEV_TYPE2_PPD_MASK (0x1 << SM5502_REG_DEV_TYPE2_PPD_SHIFT) 214 #define SM5502_REG_DEV_TYPE2_TTY_MASK (0x1 << SM5502_REG_DEV_TYPE2_TTY_SHIFT) 215 #define SM5502_REG_DEV_TYPE2_AV_CABLE_MASK (0x1 << SM5502_REG_DEV_TYPE2_AV_CABLE_SHIFT) 216 217 #define SM5502_REG_MANUAL_SW1_VBUSIN_SHIFT 0 218 #define SM5502_REG_MANUAL_SW1_DP_SHIFT 2 219 #define SM5502_REG_MANUAL_SW1_DM_SHIFT 5 220 #define SM5502_REG_MANUAL_SW1_VBUSIN_MASK (0x3 << SM5502_REG_MANUAL_SW1_VBUSIN_SHIFT) 221 #define SM5502_REG_MANUAL_SW1_DP_MASK (0x7 << SM5502_REG_MANUAL_SW1_DP_SHIFT) 222 #define SM5502_REG_MANUAL_SW1_DM_MASK (0x7 << SM5502_REG_MANUAL_SW1_DM_SHIFT) 223 #define VBUSIN_SWITCH_OPEN 0x0 224 #define VBUSIN_SWITCH_VBUSOUT 0x1 225 #define VBUSIN_SWITCH_MIC 0x2 226 #define VBUSIN_SWITCH_VBUSOUT_WITH_USB 0x3 227 #define DM_DP_CON_SWITCH_OPEN 0x0 228 #define DM_DP_CON_SWITCH_USB 0x1 229 #define DM_DP_CON_SWITCH_AUDIO 0x2 230 #define DM_DP_CON_SWITCH_UART 0x3 231 #define DM_DP_SWITCH_OPEN ((DM_DP_CON_SWITCH_OPEN <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \ 232 | (DM_DP_CON_SWITCH_OPEN <<SM5502_REG_MANUAL_SW1_DM_SHIFT)) 233 #define DM_DP_SWITCH_USB ((DM_DP_CON_SWITCH_USB <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \ 234 | (DM_DP_CON_SWITCH_USB <<SM5502_REG_MANUAL_SW1_DM_SHIFT)) 235 #define DM_DP_SWITCH_AUDIO ((DM_DP_CON_SWITCH_AUDIO <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \ 236 | (DM_DP_CON_SWITCH_AUDIO <<SM5502_REG_MANUAL_SW1_DM_SHIFT)) 237 #define DM_DP_SWITCH_UART ((DM_DP_CON_SWITCH_UART <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \ 238 | (DM_DP_CON_SWITCH_UART <<SM5502_REG_MANUAL_SW1_DM_SHIFT)) 239 240 #define SM5502_REG_RESET_MASK (0x1) 241 242 /* SM5502 Interrupts */ 243 enum sm5502_irq { 244 /* INT1 */ 245 SM5502_IRQ_INT1_ATTACH, 246 SM5502_IRQ_INT1_DETACH, 247 SM5502_IRQ_INT1_KP, 248 SM5502_IRQ_INT1_LKP, 249 SM5502_IRQ_INT1_LKR, 250 SM5502_IRQ_INT1_OVP_EVENT, 251 SM5502_IRQ_INT1_OCP_EVENT, 252 SM5502_IRQ_INT1_OVP_OCP_DIS, 253 254 /* INT2 */ 255 SM5502_IRQ_INT2_VBUS_DET, 256 SM5502_IRQ_INT2_REV_ACCE, 257 SM5502_IRQ_INT2_ADC_CHG, 258 SM5502_IRQ_INT2_STUCK_KEY, 259 SM5502_IRQ_INT2_STUCK_KEY_RCV, 260 SM5502_IRQ_INT2_MHL, 261 262 SM5502_IRQ_NUM, 263 }; 264 265 #define SM5502_IRQ_INT1_ATTACH_MASK BIT(0) 266 #define SM5502_IRQ_INT1_DETACH_MASK BIT(1) 267 #define SM5502_IRQ_INT1_KP_MASK BIT(2) 268 #define SM5502_IRQ_INT1_LKP_MASK BIT(3) 269 #define SM5502_IRQ_INT1_LKR_MASK BIT(4) 270 #define SM5502_IRQ_INT1_OVP_EVENT_MASK BIT(5) 271 #define SM5502_IRQ_INT1_OCP_EVENT_MASK BIT(6) 272 #define SM5502_IRQ_INT1_OVP_OCP_DIS_MASK BIT(7) 273 #define SM5502_IRQ_INT2_VBUS_DET_MASK BIT(0) 274 #define SM5502_IRQ_INT2_REV_ACCE_MASK BIT(1) 275 #define SM5502_IRQ_INT2_ADC_CHG_MASK BIT(2) 276 #define SM5502_IRQ_INT2_STUCK_KEY_MASK BIT(3) 277 #define SM5502_IRQ_INT2_STUCK_KEY_RCV_MASK BIT(4) 278 #define SM5502_IRQ_INT2_MHL_MASK BIT(5) 279 280 #endif /* __LINUX_EXTCON_SM5502_H */ 281