1*2874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2c03e017cSChanwoo Choi /* 3c03e017cSChanwoo Choi * rt8973a.h 4c03e017cSChanwoo Choi * 5c03e017cSChanwoo Choi * Copyright (c) 2014 Samsung Electronics Co., Ltd 6c03e017cSChanwoo Choi */ 7c03e017cSChanwoo Choi 8c03e017cSChanwoo Choi #ifndef __LINUX_EXTCON_RT8973A_H 9c03e017cSChanwoo Choi #define __LINUX_EXTCON_RT8973A_H 10c03e017cSChanwoo Choi 11c03e017cSChanwoo Choi enum rt8973a_types { 12c03e017cSChanwoo Choi TYPE_RT8973A, 13c03e017cSChanwoo Choi }; 14c03e017cSChanwoo Choi 15c03e017cSChanwoo Choi /* RT8973A registers */ 16c03e017cSChanwoo Choi enum rt8973A_reg { 17c03e017cSChanwoo Choi RT8973A_REG_DEVICE_ID = 0x1, 18c03e017cSChanwoo Choi RT8973A_REG_CONTROL1, 19c03e017cSChanwoo Choi RT8973A_REG_INT1, 20c03e017cSChanwoo Choi RT8973A_REG_INT2, 21c03e017cSChanwoo Choi RT8973A_REG_INTM1, 22c03e017cSChanwoo Choi RT8973A_REG_INTM2, 23c03e017cSChanwoo Choi RT8973A_REG_ADC, 24c03e017cSChanwoo Choi RT8973A_REG_RSVD_1, 25c03e017cSChanwoo Choi RT8973A_REG_RSVD_2, 26c03e017cSChanwoo Choi RT8973A_REG_DEV1, 27c03e017cSChanwoo Choi RT8973A_REG_DEV2, 28c03e017cSChanwoo Choi RT8973A_REG_RSVD_3, 29c03e017cSChanwoo Choi RT8973A_REG_RSVD_4, 30c03e017cSChanwoo Choi RT8973A_REG_RSVD_5, 31c03e017cSChanwoo Choi RT8973A_REG_RSVD_6, 32c03e017cSChanwoo Choi RT8973A_REG_RSVD_7, 33c03e017cSChanwoo Choi RT8973A_REG_RSVD_8, 34c03e017cSChanwoo Choi RT8973A_REG_RSVD_9, 35c03e017cSChanwoo Choi RT8973A_REG_MANUAL_SW1, 36c03e017cSChanwoo Choi RT8973A_REG_MANUAL_SW2, 37c03e017cSChanwoo Choi RT8973A_REG_RSVD_10, 38c03e017cSChanwoo Choi RT8973A_REG_RSVD_11, 39c03e017cSChanwoo Choi RT8973A_REG_RSVD_12, 40c03e017cSChanwoo Choi RT8973A_REG_RSVD_13, 41c03e017cSChanwoo Choi RT8973A_REG_RSVD_14, 42c03e017cSChanwoo Choi RT8973A_REG_RSVD_15, 43c03e017cSChanwoo Choi RT8973A_REG_RESET, 44c03e017cSChanwoo Choi 45c03e017cSChanwoo Choi RT8973A_REG_END, 46c03e017cSChanwoo Choi }; 47c03e017cSChanwoo Choi 48c03e017cSChanwoo Choi /* Define RT8973A MASK/SHIFT constant */ 49c03e017cSChanwoo Choi #define RT8973A_REG_DEVICE_ID_VENDOR_SHIFT 0 50c03e017cSChanwoo Choi #define RT8973A_REG_DEVICE_ID_VERSION_SHIFT 3 51c03e017cSChanwoo Choi #define RT8973A_REG_DEVICE_ID_VENDOR_MASK (0x7 << RT8973A_REG_DEVICE_ID_VENDOR_SHIFT) 52c03e017cSChanwoo Choi #define RT8973A_REG_DEVICE_ID_VERSION_MASK (0x1f << RT8973A_REG_DEVICE_ID_VERSION_SHIFT) 53c03e017cSChanwoo Choi 54c03e017cSChanwoo Choi #define RT8973A_REG_CONTROL1_INTM_SHIFT 0 55c03e017cSChanwoo Choi #define RT8973A_REG_CONTROL1_AUTO_CONFIG_SHIFT 2 56c03e017cSChanwoo Choi #define RT8973A_REG_CONTROL1_I2C_RST_EN_SHIFT 3 57c03e017cSChanwoo Choi #define RT8973A_REG_CONTROL1_SWITCH_OPEN_SHIFT 4 58c03e017cSChanwoo Choi #define RT8973A_REG_CONTROL1_CHGTYP_SHIFT 5 59c03e017cSChanwoo Choi #define RT8973A_REG_CONTROL1_USB_CHD_EN_SHIFT 6 60c03e017cSChanwoo Choi #define RT8973A_REG_CONTROL1_ADC_EN_SHIFT 7 61c03e017cSChanwoo Choi #define RT8973A_REG_CONTROL1_INTM_MASK (0x1 << RT8973A_REG_CONTROL1_INTM_SHIFT) 62c03e017cSChanwoo Choi #define RT8973A_REG_CONTROL1_AUTO_CONFIG_MASK (0x1 << RT8973A_REG_CONTROL1_AUTO_CONFIG_SHIFT) 63c03e017cSChanwoo Choi #define RT8973A_REG_CONTROL1_I2C_RST_EN_MASK (0x1 << RT8973A_REG_CONTROL1_I2C_RST_EN_SHIFT) 64c03e017cSChanwoo Choi #define RT8973A_REG_CONTROL1_SWITCH_OPEN_MASK (0x1 << RT8973A_REG_CONTROL1_SWITCH_OPEN_SHIFT) 65c03e017cSChanwoo Choi #define RT8973A_REG_CONTROL1_CHGTYP_MASK (0x1 << RT8973A_REG_CONTROL1_CHGTYP_SHIFT) 66c03e017cSChanwoo Choi #define RT8973A_REG_CONTROL1_USB_CHD_EN_MASK (0x1 << RT8973A_REG_CONTROL1_USB_CHD_EN_SHIFT) 67c03e017cSChanwoo Choi #define RT8973A_REG_CONTROL1_ADC_EN_MASK (0x1 << RT8973A_REG_CONTROL1_ADC_EN_SHIFT) 68c03e017cSChanwoo Choi 69c03e017cSChanwoo Choi #define RT9873A_REG_INTM1_ATTACH_SHIFT 0 70c03e017cSChanwoo Choi #define RT9873A_REG_INTM1_DETACH_SHIFT 1 71c03e017cSChanwoo Choi #define RT9873A_REG_INTM1_CHGDET_SHIFT 2 72c03e017cSChanwoo Choi #define RT9873A_REG_INTM1_DCD_T_SHIFT 3 73c03e017cSChanwoo Choi #define RT9873A_REG_INTM1_OVP_SHIFT 4 74c03e017cSChanwoo Choi #define RT9873A_REG_INTM1_CONNECT_SHIFT 5 75c03e017cSChanwoo Choi #define RT9873A_REG_INTM1_ADC_CHG_SHIFT 6 76c03e017cSChanwoo Choi #define RT9873A_REG_INTM1_OTP_SHIFT 7 77c03e017cSChanwoo Choi #define RT9873A_REG_INTM1_ATTACH_MASK (0x1 << RT9873A_REG_INTM1_ATTACH_SHIFT) 78c03e017cSChanwoo Choi #define RT9873A_REG_INTM1_DETACH_MASK (0x1 << RT9873A_REG_INTM1_DETACH_SHIFT) 79c03e017cSChanwoo Choi #define RT9873A_REG_INTM1_CHGDET_MASK (0x1 << RT9873A_REG_INTM1_CHGDET_SHIFT) 80c03e017cSChanwoo Choi #define RT9873A_REG_INTM1_DCD_T_MASK (0x1 << RT9873A_REG_INTM1_DCD_T_SHIFT) 81c03e017cSChanwoo Choi #define RT9873A_REG_INTM1_OVP_MASK (0x1 << RT9873A_REG_INTM1_OVP_SHIFT) 82c03e017cSChanwoo Choi #define RT9873A_REG_INTM1_CONNECT_MASK (0x1 << RT9873A_REG_INTM1_CONNECT_SHIFT) 83c03e017cSChanwoo Choi #define RT9873A_REG_INTM1_ADC_CHG_MASK (0x1 << RT9873A_REG_INTM1_ADC_CHG_SHIFT) 84c03e017cSChanwoo Choi #define RT9873A_REG_INTM1_OTP_MASK (0x1 << RT9873A_REG_INTM1_OTP_SHIFT) 85c03e017cSChanwoo Choi 86c03e017cSChanwoo Choi #define RT9873A_REG_INTM2_UVLO_SHIFT 1 87c03e017cSChanwoo Choi #define RT9873A_REG_INTM2_POR_SHIFT 2 88c03e017cSChanwoo Choi #define RT9873A_REG_INTM2_OTP_FET_SHIFT 3 89c03e017cSChanwoo Choi #define RT9873A_REG_INTM2_OVP_FET_SHIFT 4 90c03e017cSChanwoo Choi #define RT9873A_REG_INTM2_OCP_LATCH_SHIFT 5 91c03e017cSChanwoo Choi #define RT9873A_REG_INTM2_OCP_SHIFT 6 92c03e017cSChanwoo Choi #define RT9873A_REG_INTM2_OVP_OCP_SHIFT 7 93c03e017cSChanwoo Choi #define RT9873A_REG_INTM2_UVLO_MASK (0x1 << RT9873A_REG_INTM2_UVLO_SHIFT) 94c03e017cSChanwoo Choi #define RT9873A_REG_INTM2_POR_MASK (0x1 << RT9873A_REG_INTM2_POR_SHIFT) 95c03e017cSChanwoo Choi #define RT9873A_REG_INTM2_OTP_FET_MASK (0x1 << RT9873A_REG_INTM2_OTP_FET_SHIFT) 96c03e017cSChanwoo Choi #define RT9873A_REG_INTM2_OVP_FET_MASK (0x1 << RT9873A_REG_INTM2_OVP_FET_SHIFT) 97c03e017cSChanwoo Choi #define RT9873A_REG_INTM2_OCP_LATCH_MASK (0x1 << RT9873A_REG_INTM2_OCP_LATCH_SHIFT) 98c03e017cSChanwoo Choi #define RT9873A_REG_INTM2_OCP_MASK (0x1 << RT9873A_REG_INTM2_OCP_SHIFT) 99c03e017cSChanwoo Choi #define RT9873A_REG_INTM2_OVP_OCP_MASK (0x1 << RT9873A_REG_INTM2_OVP_OCP_SHIFT) 100c03e017cSChanwoo Choi 101c03e017cSChanwoo Choi #define RT8973A_REG_ADC_SHIFT 0 102c03e017cSChanwoo Choi #define RT8973A_REG_ADC_MASK (0x1f << RT8973A_REG_ADC_SHIFT) 103c03e017cSChanwoo Choi 104c03e017cSChanwoo Choi #define RT8973A_REG_DEV1_OTG_SHIFT 0 105c03e017cSChanwoo Choi #define RT8973A_REG_DEV1_SDP_SHIFT 2 106c03e017cSChanwoo Choi #define RT8973A_REG_DEV1_UART_SHIFT 3 107c03e017cSChanwoo Choi #define RT8973A_REG_DEV1_CAR_KIT_TYPE1_SHIFT 4 108c03e017cSChanwoo Choi #define RT8973A_REG_DEV1_CDPORT_SHIFT 5 109c03e017cSChanwoo Choi #define RT8973A_REG_DEV1_DCPORT_SHIFT 6 110c03e017cSChanwoo Choi #define RT8973A_REG_DEV1_OTG_MASK (0x1 << RT8973A_REG_DEV1_OTG_SHIFT) 111c03e017cSChanwoo Choi #define RT8973A_REG_DEV1_SDP_MASK (0x1 << RT8973A_REG_DEV1_SDP_SHIFT) 112c03e017cSChanwoo Choi #define RT8973A_REG_DEV1_UART_MASK (0x1 << RT8973A_REG_DEV1_UART_SHIFT) 113c03e017cSChanwoo Choi #define RT8973A_REG_DEV1_CAR_KIT_TYPE1_MASK (0x1 << RT8973A_REG_DEV1_CAR_KIT_TYPE1_SHIFT) 114c03e017cSChanwoo Choi #define RT8973A_REG_DEV1_CDPORT_MASK (0x1 << RT8973A_REG_DEV1_CDPORT_SHIFT) 115c03e017cSChanwoo Choi #define RT8973A_REG_DEV1_DCPORT_MASK (0x1 << RT8973A_REG_DEV1_DCPORT_SHIFT) 116c03e017cSChanwoo Choi #define RT8973A_REG_DEV1_USB_MASK (RT8973A_REG_DEV1_SDP_MASK \ 117c03e017cSChanwoo Choi | RT8973A_REG_DEV1_CDPORT_MASK) 118c03e017cSChanwoo Choi 119c03e017cSChanwoo Choi #define RT8973A_REG_DEV2_JIG_USB_ON_SHIFT 0 120c03e017cSChanwoo Choi #define RT8973A_REG_DEV2_JIG_USB_OFF_SHIFT 1 121c03e017cSChanwoo Choi #define RT8973A_REG_DEV2_JIG_UART_ON_SHIFT 2 122c03e017cSChanwoo Choi #define RT8973A_REG_DEV2_JIG_UART_OFF_SHIFT 3 123c03e017cSChanwoo Choi #define RT8973A_REG_DEV2_JIG_USB_ON_MASK (0x1 << RT8973A_REG_DEV2_JIG_USB_ON_SHIFT) 124c03e017cSChanwoo Choi #define RT8973A_REG_DEV2_JIG_USB_OFF_MASK (0x1 << RT8973A_REG_DEV2_JIG_USB_OFF_SHIFT) 125c03e017cSChanwoo Choi #define RT8973A_REG_DEV2_JIG_UART_ON_MASK (0x1 << RT8973A_REG_DEV2_JIG_UART_ON_SHIFT) 126c03e017cSChanwoo Choi #define RT8973A_REG_DEV2_JIG_UART_OFF_MASK (0x1 << RT8973A_REG_DEV2_JIG_UART_OFF_SHIFT) 127c03e017cSChanwoo Choi 128c03e017cSChanwoo Choi #define RT8973A_REG_MANUAL_SW1_DP_SHIFT 2 129c03e017cSChanwoo Choi #define RT8973A_REG_MANUAL_SW1_DM_SHIFT 5 130c03e017cSChanwoo Choi #define RT8973A_REG_MANUAL_SW1_DP_MASK (0x7 << RT8973A_REG_MANUAL_SW1_DP_SHIFT) 131c03e017cSChanwoo Choi #define RT8973A_REG_MANUAL_SW1_DM_MASK (0x7 << RT8973A_REG_MANUAL_SW1_DM_SHIFT) 132c03e017cSChanwoo Choi #define DM_DP_CON_SWITCH_OPEN 0x0 133c03e017cSChanwoo Choi #define DM_DP_CON_SWITCH_USB 0x1 134c03e017cSChanwoo Choi #define DM_DP_CON_SWITCH_UART 0x3 135c03e017cSChanwoo Choi #define DM_DP_SWITCH_OPEN ((DM_DP_CON_SWITCH_OPEN << RT8973A_REG_MANUAL_SW1_DP_SHIFT) \ 136c03e017cSChanwoo Choi | (DM_DP_CON_SWITCH_OPEN << RT8973A_REG_MANUAL_SW1_DM_SHIFT)) 137c03e017cSChanwoo Choi #define DM_DP_SWITCH_USB ((DM_DP_CON_SWITCH_USB << RT8973A_REG_MANUAL_SW1_DP_SHIFT) \ 138c03e017cSChanwoo Choi | (DM_DP_CON_SWITCH_USB << RT8973A_REG_MANUAL_SW1_DM_SHIFT)) 139c03e017cSChanwoo Choi #define DM_DP_SWITCH_UART ((DM_DP_CON_SWITCH_UART << RT8973A_REG_MANUAL_SW1_DP_SHIFT) \ 140c03e017cSChanwoo Choi | (DM_DP_CON_SWITCH_UART << RT8973A_REG_MANUAL_SW1_DM_SHIFT)) 141c03e017cSChanwoo Choi 142c03e017cSChanwoo Choi #define RT8973A_REG_MANUAL_SW2_FET_ON_SHIFT 0 143c03e017cSChanwoo Choi #define RT8973A_REG_MANUAL_SW2_JIG_ON_SHIFT 2 144c03e017cSChanwoo Choi #define RT8973A_REG_MANUAL_SW2_BOOT_SW_SHIFT 3 145c03e017cSChanwoo Choi #define RT8973A_REG_MANUAL_SW2_FET_ON_MASK (0x1 << RT8973A_REG_MANUAL_SW2_FET_ON_SHIFT) 146c03e017cSChanwoo Choi #define RT8973A_REG_MANUAL_SW2_JIG_ON_MASK (0x1 << RT8973A_REG_MANUAL_SW2_JIG_ON_SHIFT) 147c03e017cSChanwoo Choi #define RT8973A_REG_MANUAL_SW2_BOOT_SW_MASK (0x1 << RT8973A_REG_MANUAL_SW2_BOOT_SW_SHIFT) 148c03e017cSChanwoo Choi #define RT8973A_REG_MANUAL_SW2_FET_ON 0 149c03e017cSChanwoo Choi #define RT8973A_REG_MANUAL_SW2_FET_OFF 0x1 150c03e017cSChanwoo Choi #define RT8973A_REG_MANUAL_SW2_JIG_OFF 0 151c03e017cSChanwoo Choi #define RT8973A_REG_MANUAL_SW2_JIG_ON 0x1 152c03e017cSChanwoo Choi #define RT8973A_REG_MANUAL_SW2_BOOT_SW_ON 0 153c03e017cSChanwoo Choi #define RT8973A_REG_MANUAL_SW2_BOOT_SW_OFF 0x1 154c03e017cSChanwoo Choi 155c03e017cSChanwoo Choi #define RT8973A_REG_RESET_SHIFT 0 156c03e017cSChanwoo Choi #define RT8973A_REG_RESET_MASK (0x1 << RT8973A_REG_RESET_SHIFT) 157c03e017cSChanwoo Choi #define RT8973A_REG_RESET 0x1 158c03e017cSChanwoo Choi 159c03e017cSChanwoo Choi /* RT8973A Interrupts */ 160c03e017cSChanwoo Choi enum rt8973a_irq { 161c03e017cSChanwoo Choi /* Interrupt1*/ 162c03e017cSChanwoo Choi RT8973A_INT1_ATTACH, 163c03e017cSChanwoo Choi RT8973A_INT1_DETACH, 164c03e017cSChanwoo Choi RT8973A_INT1_CHGDET, 165c03e017cSChanwoo Choi RT8973A_INT1_DCD_T, 166c03e017cSChanwoo Choi RT8973A_INT1_OVP, 167c03e017cSChanwoo Choi RT8973A_INT1_CONNECT, 168c03e017cSChanwoo Choi RT8973A_INT1_ADC_CHG, 169c03e017cSChanwoo Choi RT8973A_INT1_OTP, 170c03e017cSChanwoo Choi 171c03e017cSChanwoo Choi /* Interrupt2*/ 172c03e017cSChanwoo Choi RT8973A_INT2_UVLO, 173c03e017cSChanwoo Choi RT8973A_INT2_POR, 174c03e017cSChanwoo Choi RT8973A_INT2_OTP_FET, 175c03e017cSChanwoo Choi RT8973A_INT2_OVP_FET, 176c03e017cSChanwoo Choi RT8973A_INT2_OCP_LATCH, 177c03e017cSChanwoo Choi RT8973A_INT2_OCP, 178c03e017cSChanwoo Choi RT8973A_INT2_OVP_OCP, 179c03e017cSChanwoo Choi 180c03e017cSChanwoo Choi RT8973A_NUM, 181c03e017cSChanwoo Choi }; 182c03e017cSChanwoo Choi 183c03e017cSChanwoo Choi #define RT8973A_INT1_ATTACH_MASK BIT(0) 184c03e017cSChanwoo Choi #define RT8973A_INT1_DETACH_MASK BIT(1) 185c03e017cSChanwoo Choi #define RT8973A_INT1_CHGDET_MASK BIT(2) 186c03e017cSChanwoo Choi #define RT8973A_INT1_DCD_T_MASK BIT(3) 187c03e017cSChanwoo Choi #define RT8973A_INT1_OVP_MASK BIT(4) 188c03e017cSChanwoo Choi #define RT8973A_INT1_CONNECT_MASK BIT(5) 189c03e017cSChanwoo Choi #define RT8973A_INT1_ADC_CHG_MASK BIT(6) 190c03e017cSChanwoo Choi #define RT8973A_INT1_OTP_MASK BIT(7) 191c03e017cSChanwoo Choi #define RT8973A_INT2_UVLOT_MASK BIT(0) 192c03e017cSChanwoo Choi #define RT8973A_INT2_POR_MASK BIT(1) 193c03e017cSChanwoo Choi #define RT8973A_INT2_OTP_FET_MASK BIT(2) 194c03e017cSChanwoo Choi #define RT8973A_INT2_OVP_FET_MASK BIT(3) 195c03e017cSChanwoo Choi #define RT8973A_INT2_OCP_LATCH_MASK BIT(4) 196c03e017cSChanwoo Choi #define RT8973A_INT2_OCP_MASK BIT(5) 197c03e017cSChanwoo Choi #define RT8973A_INT2_OVP_OCP_MASK BIT(6) 198c03e017cSChanwoo Choi 199c03e017cSChanwoo Choi #endif /* __LINUX_EXTCON_RT8973A_H */ 200