xref: /linux/drivers/edac/synopsys_edac.c (revision 1f20a5769446a1acae67ac9e63d07a594829a789)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Synopsys DDR ECC Driver
4  * This driver is based on ppc4xx_edac.c drivers
5  *
6  * Copyright (C) 2012 - 2014 Xilinx, Inc.
7  */
8 
9 #include <linux/edac.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/interrupt.h>
13 #include <linux/of.h>
14 
15 #include "edac_module.h"
16 
17 /* Number of cs_rows needed per memory controller */
18 #define SYNPS_EDAC_NR_CSROWS		1
19 
20 /* Number of channels per memory controller */
21 #define SYNPS_EDAC_NR_CHANS		1
22 
23 /* Granularity of reported error in bytes */
24 #define SYNPS_EDAC_ERR_GRAIN		1
25 
26 #define SYNPS_EDAC_MSG_SIZE		256
27 
28 #define SYNPS_EDAC_MOD_STRING		"synps_edac"
29 #define SYNPS_EDAC_MOD_VER		"1"
30 
31 /* Synopsys DDR memory controller registers that are relevant to ECC */
32 #define CTRL_OFST			0x0
33 #define T_ZQ_OFST			0xA4
34 
35 /* ECC control register */
36 #define ECC_CTRL_OFST			0xC4
37 /* ECC log register */
38 #define CE_LOG_OFST			0xC8
39 /* ECC address register */
40 #define CE_ADDR_OFST			0xCC
41 /* ECC data[31:0] register */
42 #define CE_DATA_31_0_OFST		0xD0
43 
44 /* Uncorrectable error info registers */
45 #define UE_LOG_OFST			0xDC
46 #define UE_ADDR_OFST			0xE0
47 #define UE_DATA_31_0_OFST		0xE4
48 
49 #define STAT_OFST			0xF0
50 #define SCRUB_OFST			0xF4
51 
52 /* Control register bit field definitions */
53 #define CTRL_BW_MASK			0xC
54 #define CTRL_BW_SHIFT			2
55 
56 #define DDRCTL_WDTH_16			1
57 #define DDRCTL_WDTH_32			0
58 
59 /* ZQ register bit field definitions */
60 #define T_ZQ_DDRMODE_MASK		0x2
61 
62 /* ECC control register bit field definitions */
63 #define ECC_CTRL_CLR_CE_ERR		0x2
64 #define ECC_CTRL_CLR_UE_ERR		0x1
65 
66 /* ECC correctable/uncorrectable error log register definitions */
67 #define LOG_VALID			0x1
68 #define CE_LOG_BITPOS_MASK		0xFE
69 #define CE_LOG_BITPOS_SHIFT		1
70 
71 /* ECC correctable/uncorrectable error address register definitions */
72 #define ADDR_COL_MASK			0xFFF
73 #define ADDR_ROW_MASK			0xFFFF000
74 #define ADDR_ROW_SHIFT			12
75 #define ADDR_BANK_MASK			0x70000000
76 #define ADDR_BANK_SHIFT			28
77 
78 /* ECC statistic register definitions */
79 #define STAT_UECNT_MASK			0xFF
80 #define STAT_CECNT_MASK			0xFF00
81 #define STAT_CECNT_SHIFT		8
82 
83 /* ECC scrub register definitions */
84 #define SCRUB_MODE_MASK			0x7
85 #define SCRUB_MODE_SECDED		0x4
86 
87 /* DDR ECC Quirks */
88 #define DDR_ECC_INTR_SUPPORT		BIT(0)
89 #define DDR_ECC_DATA_POISON_SUPPORT	BIT(1)
90 #define DDR_ECC_INTR_SELF_CLEAR		BIT(2)
91 
92 /* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */
93 /* ECC Configuration Registers */
94 #define ECC_CFG0_OFST			0x70
95 #define ECC_CFG1_OFST			0x74
96 
97 /* ECC Status Register */
98 #define ECC_STAT_OFST			0x78
99 
100 /* ECC Clear Register */
101 #define ECC_CLR_OFST			0x7C
102 
103 /* ECC Error count Register */
104 #define ECC_ERRCNT_OFST			0x80
105 
106 /* ECC Corrected Error Address Register */
107 #define ECC_CEADDR0_OFST		0x84
108 #define ECC_CEADDR1_OFST		0x88
109 
110 /* ECC Syndrome Registers */
111 #define ECC_CSYND0_OFST			0x8C
112 #define ECC_CSYND1_OFST			0x90
113 #define ECC_CSYND2_OFST			0x94
114 
115 /* ECC Bit Mask0 Address Register */
116 #define ECC_BITMASK0_OFST		0x98
117 #define ECC_BITMASK1_OFST		0x9C
118 #define ECC_BITMASK2_OFST		0xA0
119 
120 /* ECC UnCorrected Error Address Register */
121 #define ECC_UEADDR0_OFST		0xA4
122 #define ECC_UEADDR1_OFST		0xA8
123 
124 /* ECC Syndrome Registers */
125 #define ECC_UESYND0_OFST		0xAC
126 #define ECC_UESYND1_OFST		0xB0
127 #define ECC_UESYND2_OFST		0xB4
128 
129 /* ECC Poison Address Reg */
130 #define ECC_POISON0_OFST		0xB8
131 #define ECC_POISON1_OFST		0xBC
132 
133 #define ECC_ADDRMAP0_OFFSET		0x200
134 
135 /* Control register bitfield definitions */
136 #define ECC_CTRL_BUSWIDTH_MASK		0x3000
137 #define ECC_CTRL_BUSWIDTH_SHIFT		12
138 #define ECC_CTRL_CLR_CE_ERRCNT		BIT(2)
139 #define ECC_CTRL_CLR_UE_ERRCNT		BIT(3)
140 
141 /* DDR Control Register width definitions  */
142 #define DDRCTL_EWDTH_16			2
143 #define DDRCTL_EWDTH_32			1
144 #define DDRCTL_EWDTH_64			0
145 
146 /* ECC status register definitions */
147 #define ECC_STAT_UECNT_MASK		0xF0000
148 #define ECC_STAT_UECNT_SHIFT		16
149 #define ECC_STAT_CECNT_MASK		0xF00
150 #define ECC_STAT_CECNT_SHIFT		8
151 #define ECC_STAT_BITNUM_MASK		0x7F
152 
153 /* ECC error count register definitions */
154 #define ECC_ERRCNT_UECNT_MASK		0xFFFF0000
155 #define ECC_ERRCNT_UECNT_SHIFT		16
156 #define ECC_ERRCNT_CECNT_MASK		0xFFFF
157 
158 /* DDR QOS Interrupt register definitions */
159 #define DDR_QOS_IRQ_STAT_OFST		0x20200
160 #define DDR_QOSUE_MASK			0x4
161 #define	DDR_QOSCE_MASK			0x2
162 #define	ECC_CE_UE_INTR_MASK		0x6
163 #define DDR_QOS_IRQ_EN_OFST		0x20208
164 #define DDR_QOS_IRQ_DB_OFST		0x2020C
165 
166 /* DDR QOS Interrupt register definitions */
167 #define DDR_UE_MASK			BIT(9)
168 #define DDR_CE_MASK			BIT(8)
169 
170 /* ECC Corrected Error Register Mask and Shifts*/
171 #define ECC_CEADDR0_RW_MASK		0x3FFFF
172 #define ECC_CEADDR0_RNK_MASK		BIT(24)
173 #define ECC_CEADDR1_BNKGRP_MASK		0x3000000
174 #define ECC_CEADDR1_BNKNR_MASK		0x70000
175 #define ECC_CEADDR1_BLKNR_MASK		0xFFF
176 #define ECC_CEADDR1_BNKGRP_SHIFT	24
177 #define ECC_CEADDR1_BNKNR_SHIFT		16
178 
179 /* ECC Poison register shifts */
180 #define ECC_POISON0_RANK_SHIFT		24
181 #define ECC_POISON0_RANK_MASK		BIT(24)
182 #define ECC_POISON0_COLUMN_SHIFT	0
183 #define ECC_POISON0_COLUMN_MASK		0xFFF
184 #define ECC_POISON1_BG_SHIFT		28
185 #define ECC_POISON1_BG_MASK		0x30000000
186 #define ECC_POISON1_BANKNR_SHIFT	24
187 #define ECC_POISON1_BANKNR_MASK		0x7000000
188 #define ECC_POISON1_ROW_SHIFT		0
189 #define ECC_POISON1_ROW_MASK		0x3FFFF
190 
191 /* DDR Memory type defines */
192 #define MEM_TYPE_DDR3			0x1
193 #define MEM_TYPE_LPDDR3			0x8
194 #define MEM_TYPE_DDR2			0x4
195 #define MEM_TYPE_DDR4			0x10
196 #define MEM_TYPE_LPDDR4			0x20
197 
198 /* DDRC Software control register */
199 #define DDRC_SWCTL			0x320
200 
201 /* DDRC ECC CE & UE poison mask */
202 #define ECC_CEPOISON_MASK		0x3
203 #define ECC_UEPOISON_MASK		0x1
204 
205 /* DDRC Device config masks */
206 #define DDRC_MSTR_CFG_MASK		0xC0000000
207 #define DDRC_MSTR_CFG_SHIFT		30
208 #define DDRC_MSTR_CFG_X4_MASK		0x0
209 #define DDRC_MSTR_CFG_X8_MASK		0x1
210 #define DDRC_MSTR_CFG_X16_MASK		0x2
211 #define DDRC_MSTR_CFG_X32_MASK		0x3
212 
213 #define DDR_MAX_ROW_SHIFT		18
214 #define DDR_MAX_COL_SHIFT		14
215 #define DDR_MAX_BANK_SHIFT		3
216 #define DDR_MAX_BANKGRP_SHIFT		2
217 
218 #define ROW_MAX_VAL_MASK		0xF
219 #define COL_MAX_VAL_MASK		0xF
220 #define BANK_MAX_VAL_MASK		0x1F
221 #define BANKGRP_MAX_VAL_MASK		0x1F
222 #define RANK_MAX_VAL_MASK		0x1F
223 
224 #define ROW_B0_BASE			6
225 #define ROW_B1_BASE			7
226 #define ROW_B2_BASE			8
227 #define ROW_B3_BASE			9
228 #define ROW_B4_BASE			10
229 #define ROW_B5_BASE			11
230 #define ROW_B6_BASE			12
231 #define ROW_B7_BASE			13
232 #define ROW_B8_BASE			14
233 #define ROW_B9_BASE			15
234 #define ROW_B10_BASE			16
235 #define ROW_B11_BASE			17
236 #define ROW_B12_BASE			18
237 #define ROW_B13_BASE			19
238 #define ROW_B14_BASE			20
239 #define ROW_B15_BASE			21
240 #define ROW_B16_BASE			22
241 #define ROW_B17_BASE			23
242 
243 #define COL_B2_BASE			2
244 #define COL_B3_BASE			3
245 #define COL_B4_BASE			4
246 #define COL_B5_BASE			5
247 #define COL_B6_BASE			6
248 #define COL_B7_BASE			7
249 #define COL_B8_BASE			8
250 #define COL_B9_BASE			9
251 #define COL_B10_BASE			10
252 #define COL_B11_BASE			11
253 #define COL_B12_BASE			12
254 #define COL_B13_BASE			13
255 
256 #define BANK_B0_BASE			2
257 #define BANK_B1_BASE			3
258 #define BANK_B2_BASE			4
259 
260 #define BANKGRP_B0_BASE			2
261 #define BANKGRP_B1_BASE			3
262 
263 #define RANK_B0_BASE			6
264 
265 /**
266  * struct ecc_error_info - ECC error log information.
267  * @row:	Row number.
268  * @col:	Column number.
269  * @bank:	Bank number.
270  * @bitpos:	Bit position.
271  * @data:	Data causing the error.
272  * @bankgrpnr:	Bank group number.
273  * @blknr:	Block number.
274  */
275 struct ecc_error_info {
276 	u32 row;
277 	u32 col;
278 	u32 bank;
279 	u32 bitpos;
280 	u32 data;
281 	u32 bankgrpnr;
282 	u32 blknr;
283 };
284 
285 /**
286  * struct synps_ecc_status - ECC status information to report.
287  * @ce_cnt:	Correctable error count.
288  * @ue_cnt:	Uncorrectable error count.
289  * @ceinfo:	Correctable error log information.
290  * @ueinfo:	Uncorrectable error log information.
291  */
292 struct synps_ecc_status {
293 	u32 ce_cnt;
294 	u32 ue_cnt;
295 	struct ecc_error_info ceinfo;
296 	struct ecc_error_info ueinfo;
297 };
298 
299 /**
300  * struct synps_edac_priv - DDR memory controller private instance data.
301  * @baseaddr:		Base address of the DDR controller.
302  * @message:		Buffer for framing the event specific info.
303  * @stat:		ECC status information.
304  * @p_data:		Platform data.
305  * @ce_cnt:		Correctable Error count.
306  * @ue_cnt:		Uncorrectable Error count.
307  * @poison_addr:	Data poison address.
308  * @row_shift:		Bit shifts for row bit.
309  * @col_shift:		Bit shifts for column bit.
310  * @bank_shift:		Bit shifts for bank bit.
311  * @bankgrp_shift:	Bit shifts for bank group bit.
312  * @rank_shift:		Bit shifts for rank bit.
313  */
314 struct synps_edac_priv {
315 	void __iomem *baseaddr;
316 	char message[SYNPS_EDAC_MSG_SIZE];
317 	struct synps_ecc_status stat;
318 	const struct synps_platform_data *p_data;
319 	u32 ce_cnt;
320 	u32 ue_cnt;
321 #ifdef CONFIG_EDAC_DEBUG
322 	ulong poison_addr;
323 	u32 row_shift[18];
324 	u32 col_shift[14];
325 	u32 bank_shift[3];
326 	u32 bankgrp_shift[2];
327 	u32 rank_shift[1];
328 #endif
329 };
330 
331 /**
332  * struct synps_platform_data -  synps platform data structure.
333  * @get_error_info:	Get EDAC error info.
334  * @get_mtype:		Get mtype.
335  * @get_dtype:		Get dtype.
336  * @get_ecc_state:	Get ECC state.
337  * @quirks:		To differentiate IPs.
338  */
339 struct synps_platform_data {
340 	int (*get_error_info)(struct synps_edac_priv *priv);
341 	enum mem_type (*get_mtype)(const void __iomem *base);
342 	enum dev_type (*get_dtype)(const void __iomem *base);
343 	bool (*get_ecc_state)(void __iomem *base);
344 	int quirks;
345 };
346 
347 /**
348  * zynq_get_error_info - Get the current ECC error info.
349  * @priv:	DDR memory controller private instance data.
350  *
351  * Return: one if there is no error, otherwise zero.
352  */
353 static int zynq_get_error_info(struct synps_edac_priv *priv)
354 {
355 	struct synps_ecc_status *p;
356 	u32 regval, clearval = 0;
357 	void __iomem *base;
358 
359 	base = priv->baseaddr;
360 	p = &priv->stat;
361 
362 	regval = readl(base + STAT_OFST);
363 	if (!regval)
364 		return 1;
365 
366 	p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT;
367 	p->ue_cnt = regval & STAT_UECNT_MASK;
368 
369 	regval = readl(base + CE_LOG_OFST);
370 	if (!(p->ce_cnt && (regval & LOG_VALID)))
371 		goto ue_err;
372 
373 	p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT;
374 	regval = readl(base + CE_ADDR_OFST);
375 	p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT;
376 	p->ceinfo.col = regval & ADDR_COL_MASK;
377 	p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT;
378 	p->ceinfo.data = readl(base + CE_DATA_31_0_OFST);
379 	edac_dbg(3, "CE bit position: %d data: %d\n", p->ceinfo.bitpos,
380 		 p->ceinfo.data);
381 	clearval = ECC_CTRL_CLR_CE_ERR;
382 
383 ue_err:
384 	regval = readl(base + UE_LOG_OFST);
385 	if (!(p->ue_cnt && (regval & LOG_VALID)))
386 		goto out;
387 
388 	regval = readl(base + UE_ADDR_OFST);
389 	p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT;
390 	p->ueinfo.col = regval & ADDR_COL_MASK;
391 	p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT;
392 	p->ueinfo.data = readl(base + UE_DATA_31_0_OFST);
393 	clearval |= ECC_CTRL_CLR_UE_ERR;
394 
395 out:
396 	writel(clearval, base + ECC_CTRL_OFST);
397 	writel(0x0, base + ECC_CTRL_OFST);
398 
399 	return 0;
400 }
401 
402 /**
403  * zynqmp_get_error_info - Get the current ECC error info.
404  * @priv:	DDR memory controller private instance data.
405  *
406  * Return: one if there is no error otherwise returns zero.
407  */
408 static int zynqmp_get_error_info(struct synps_edac_priv *priv)
409 {
410 	struct synps_ecc_status *p;
411 	u32 regval, clearval = 0;
412 	void __iomem *base;
413 
414 	base = priv->baseaddr;
415 	p = &priv->stat;
416 
417 	regval = readl(base + ECC_ERRCNT_OFST);
418 	p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK;
419 	p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT;
420 	if (!p->ce_cnt)
421 		goto ue_err;
422 
423 	regval = readl(base + ECC_STAT_OFST);
424 	if (!regval)
425 		return 1;
426 
427 	p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK);
428 
429 	regval = readl(base + ECC_CEADDR0_OFST);
430 	p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK);
431 	regval = readl(base + ECC_CEADDR1_OFST);
432 	p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>
433 					ECC_CEADDR1_BNKNR_SHIFT;
434 	p->ceinfo.bankgrpnr = (regval &	ECC_CEADDR1_BNKGRP_MASK) >>
435 					ECC_CEADDR1_BNKGRP_SHIFT;
436 	p->ceinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);
437 	p->ceinfo.data = readl(base + ECC_CSYND0_OFST);
438 	edac_dbg(2, "ECCCSYN0: 0x%08X ECCCSYN1: 0x%08X ECCCSYN2: 0x%08X\n",
439 		 readl(base + ECC_CSYND0_OFST), readl(base + ECC_CSYND1_OFST),
440 		 readl(base + ECC_CSYND2_OFST));
441 ue_err:
442 	if (!p->ue_cnt)
443 		goto out;
444 
445 	regval = readl(base + ECC_UEADDR0_OFST);
446 	p->ueinfo.row = (regval & ECC_CEADDR0_RW_MASK);
447 	regval = readl(base + ECC_UEADDR1_OFST);
448 	p->ueinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >>
449 					ECC_CEADDR1_BNKGRP_SHIFT;
450 	p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>
451 					ECC_CEADDR1_BNKNR_SHIFT;
452 	p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);
453 	p->ueinfo.data = readl(base + ECC_UESYND0_OFST);
454 out:
455 	clearval = ECC_CTRL_CLR_CE_ERR | ECC_CTRL_CLR_CE_ERRCNT;
456 	clearval |= ECC_CTRL_CLR_UE_ERR | ECC_CTRL_CLR_UE_ERRCNT;
457 	writel(clearval, base + ECC_CLR_OFST);
458 	writel(0x0, base + ECC_CLR_OFST);
459 
460 	return 0;
461 }
462 
463 /**
464  * handle_error - Handle Correctable and Uncorrectable errors.
465  * @mci:	EDAC memory controller instance.
466  * @p:		Synopsys ECC status structure.
467  *
468  * Handles ECC correctable and uncorrectable errors.
469  */
470 static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p)
471 {
472 	struct synps_edac_priv *priv = mci->pvt_info;
473 	struct ecc_error_info *pinf;
474 
475 	if (p->ce_cnt) {
476 		pinf = &p->ceinfo;
477 		if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
478 			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
479 				 "DDR ECC error type:%s Row %d Bank %d BankGroup Number %d Block Number %d Bit Position: %d Data: 0x%08x",
480 				 "CE", pinf->row, pinf->bank,
481 				 pinf->bankgrpnr, pinf->blknr,
482 				 pinf->bitpos, pinf->data);
483 		} else {
484 			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
485 				 "DDR ECC error type:%s Row %d Bank %d Col %d Bit Position: %d Data: 0x%08x",
486 				 "CE", pinf->row, pinf->bank, pinf->col,
487 				 pinf->bitpos, pinf->data);
488 		}
489 
490 		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
491 				     p->ce_cnt, 0, 0, 0, 0, 0, -1,
492 				     priv->message, "");
493 	}
494 
495 	if (p->ue_cnt) {
496 		pinf = &p->ueinfo;
497 		if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
498 			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
499 				 "DDR ECC error type :%s Row %d Bank %d BankGroup Number %d Block Number %d",
500 				 "UE", pinf->row, pinf->bank,
501 				 pinf->bankgrpnr, pinf->blknr);
502 		} else {
503 			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
504 				 "DDR ECC error type :%s Row %d Bank %d Col %d ",
505 				 "UE", pinf->row, pinf->bank, pinf->col);
506 		}
507 
508 		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
509 				     p->ue_cnt, 0, 0, 0, 0, 0, -1,
510 				     priv->message, "");
511 	}
512 
513 	memset(p, 0, sizeof(*p));
514 }
515 
516 static void enable_intr(struct synps_edac_priv *priv)
517 {
518 	/* Enable UE/CE Interrupts */
519 	if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
520 		writel(DDR_UE_MASK | DDR_CE_MASK,
521 		       priv->baseaddr + ECC_CLR_OFST);
522 	else
523 		writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
524 		       priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
525 
526 }
527 
528 static void disable_intr(struct synps_edac_priv *priv)
529 {
530 	/* Disable UE/CE Interrupts */
531 	if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
532 		writel(0x0, priv->baseaddr + ECC_CLR_OFST);
533 	else
534 		writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
535 		       priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
536 }
537 
538 /**
539  * intr_handler - Interrupt Handler for ECC interrupts.
540  * @irq:        IRQ number.
541  * @dev_id:     Device ID.
542  *
543  * Return: IRQ_NONE, if interrupt not set or IRQ_HANDLED otherwise.
544  */
545 static irqreturn_t intr_handler(int irq, void *dev_id)
546 {
547 	const struct synps_platform_data *p_data;
548 	struct mem_ctl_info *mci = dev_id;
549 	struct synps_edac_priv *priv;
550 	int status, regval;
551 
552 	priv = mci->pvt_info;
553 	p_data = priv->p_data;
554 
555 	/*
556 	 * v3.0 of the controller has the ce/ue bits cleared automatically,
557 	 * so this condition does not apply.
558 	 */
559 	if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) {
560 		regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
561 		regval &= (DDR_QOSCE_MASK | DDR_QOSUE_MASK);
562 		if (!(regval & ECC_CE_UE_INTR_MASK))
563 			return IRQ_NONE;
564 	}
565 
566 	status = p_data->get_error_info(priv);
567 	if (status)
568 		return IRQ_NONE;
569 
570 	priv->ce_cnt += priv->stat.ce_cnt;
571 	priv->ue_cnt += priv->stat.ue_cnt;
572 	handle_error(mci, &priv->stat);
573 
574 	edac_dbg(3, "Total error count CE %d UE %d\n",
575 		 priv->ce_cnt, priv->ue_cnt);
576 	/* v3.0 of the controller does not have this register */
577 	if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR))
578 		writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
579 	else
580 		enable_intr(priv);
581 
582 	return IRQ_HANDLED;
583 }
584 
585 /**
586  * check_errors - Check controller for ECC errors.
587  * @mci:	EDAC memory controller instance.
588  *
589  * Check and post ECC errors. Called by the polling thread.
590  */
591 static void check_errors(struct mem_ctl_info *mci)
592 {
593 	const struct synps_platform_data *p_data;
594 	struct synps_edac_priv *priv;
595 	int status;
596 
597 	priv = mci->pvt_info;
598 	p_data = priv->p_data;
599 
600 	status = p_data->get_error_info(priv);
601 	if (status)
602 		return;
603 
604 	priv->ce_cnt += priv->stat.ce_cnt;
605 	priv->ue_cnt += priv->stat.ue_cnt;
606 	handle_error(mci, &priv->stat);
607 
608 	edac_dbg(3, "Total error count CE %d UE %d\n",
609 		 priv->ce_cnt, priv->ue_cnt);
610 }
611 
612 /**
613  * zynq_get_dtype - Return the controller memory width.
614  * @base:	DDR memory controller base address.
615  *
616  * Get the EDAC device type width appropriate for the current controller
617  * configuration.
618  *
619  * Return: a device type width enumeration.
620  */
621 static enum dev_type zynq_get_dtype(const void __iomem *base)
622 {
623 	enum dev_type dt;
624 	u32 width;
625 
626 	width = readl(base + CTRL_OFST);
627 	width = (width & CTRL_BW_MASK) >> CTRL_BW_SHIFT;
628 
629 	switch (width) {
630 	case DDRCTL_WDTH_16:
631 		dt = DEV_X2;
632 		break;
633 	case DDRCTL_WDTH_32:
634 		dt = DEV_X4;
635 		break;
636 	default:
637 		dt = DEV_UNKNOWN;
638 	}
639 
640 	return dt;
641 }
642 
643 /**
644  * zynqmp_get_dtype - Return the controller memory width.
645  * @base:	DDR memory controller base address.
646  *
647  * Get the EDAC device type width appropriate for the current controller
648  * configuration.
649  *
650  * Return: a device type width enumeration.
651  */
652 static enum dev_type zynqmp_get_dtype(const void __iomem *base)
653 {
654 	enum dev_type dt;
655 	u32 width;
656 
657 	width = readl(base + CTRL_OFST);
658 	width = (width & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT;
659 	switch (width) {
660 	case DDRCTL_EWDTH_16:
661 		dt = DEV_X2;
662 		break;
663 	case DDRCTL_EWDTH_32:
664 		dt = DEV_X4;
665 		break;
666 	case DDRCTL_EWDTH_64:
667 		dt = DEV_X8;
668 		break;
669 	default:
670 		dt = DEV_UNKNOWN;
671 	}
672 
673 	return dt;
674 }
675 
676 /**
677  * zynq_get_ecc_state - Return the controller ECC enable/disable status.
678  * @base:	DDR memory controller base address.
679  *
680  * Get the ECC enable/disable status of the controller.
681  *
682  * Return: true if enabled, otherwise false.
683  */
684 static bool zynq_get_ecc_state(void __iomem *base)
685 {
686 	enum dev_type dt;
687 	u32 ecctype;
688 
689 	dt = zynq_get_dtype(base);
690 	if (dt == DEV_UNKNOWN)
691 		return false;
692 
693 	ecctype = readl(base + SCRUB_OFST) & SCRUB_MODE_MASK;
694 	if ((ecctype == SCRUB_MODE_SECDED) && (dt == DEV_X2))
695 		return true;
696 
697 	return false;
698 }
699 
700 /**
701  * zynqmp_get_ecc_state - Return the controller ECC enable/disable status.
702  * @base:	DDR memory controller base address.
703  *
704  * Get the ECC enable/disable status for the controller.
705  *
706  * Return: a ECC status boolean i.e true/false - enabled/disabled.
707  */
708 static bool zynqmp_get_ecc_state(void __iomem *base)
709 {
710 	enum dev_type dt;
711 	u32 ecctype;
712 
713 	dt = zynqmp_get_dtype(base);
714 	if (dt == DEV_UNKNOWN)
715 		return false;
716 
717 	ecctype = readl(base + ECC_CFG0_OFST) & SCRUB_MODE_MASK;
718 	if ((ecctype == SCRUB_MODE_SECDED) &&
719 	    ((dt == DEV_X2) || (dt == DEV_X4) || (dt == DEV_X8)))
720 		return true;
721 
722 	return false;
723 }
724 
725 /**
726  * get_memsize - Read the size of the attached memory device.
727  *
728  * Return: the memory size in bytes.
729  */
730 static u32 get_memsize(void)
731 {
732 	struct sysinfo inf;
733 
734 	si_meminfo(&inf);
735 
736 	return inf.totalram * inf.mem_unit;
737 }
738 
739 /**
740  * zynq_get_mtype - Return the controller memory type.
741  * @base:	Synopsys ECC status structure.
742  *
743  * Get the EDAC memory type appropriate for the current controller
744  * configuration.
745  *
746  * Return: a memory type enumeration.
747  */
748 static enum mem_type zynq_get_mtype(const void __iomem *base)
749 {
750 	enum mem_type mt;
751 	u32 memtype;
752 
753 	memtype = readl(base + T_ZQ_OFST);
754 
755 	if (memtype & T_ZQ_DDRMODE_MASK)
756 		mt = MEM_DDR3;
757 	else
758 		mt = MEM_DDR2;
759 
760 	return mt;
761 }
762 
763 /**
764  * zynqmp_get_mtype - Returns controller memory type.
765  * @base:	Synopsys ECC status structure.
766  *
767  * Get the EDAC memory type appropriate for the current controller
768  * configuration.
769  *
770  * Return: a memory type enumeration.
771  */
772 static enum mem_type zynqmp_get_mtype(const void __iomem *base)
773 {
774 	enum mem_type mt;
775 	u32 memtype;
776 
777 	memtype = readl(base + CTRL_OFST);
778 
779 	if ((memtype & MEM_TYPE_DDR3) || (memtype & MEM_TYPE_LPDDR3))
780 		mt = MEM_DDR3;
781 	else if (memtype & MEM_TYPE_DDR2)
782 		mt = MEM_RDDR2;
783 	else if ((memtype & MEM_TYPE_LPDDR4) || (memtype & MEM_TYPE_DDR4))
784 		mt = MEM_DDR4;
785 	else
786 		mt = MEM_EMPTY;
787 
788 	return mt;
789 }
790 
791 /**
792  * init_csrows - Initialize the csrow data.
793  * @mci:	EDAC memory controller instance.
794  *
795  * Initialize the chip select rows associated with the EDAC memory
796  * controller instance.
797  */
798 static void init_csrows(struct mem_ctl_info *mci)
799 {
800 	struct synps_edac_priv *priv = mci->pvt_info;
801 	const struct synps_platform_data *p_data;
802 	struct csrow_info *csi;
803 	struct dimm_info *dimm;
804 	u32 size, row;
805 	int j;
806 
807 	p_data = priv->p_data;
808 
809 	for (row = 0; row < mci->nr_csrows; row++) {
810 		csi = mci->csrows[row];
811 		size = get_memsize();
812 
813 		for (j = 0; j < csi->nr_channels; j++) {
814 			dimm		= csi->channels[j]->dimm;
815 			dimm->edac_mode	= EDAC_SECDED;
816 			dimm->mtype	= p_data->get_mtype(priv->baseaddr);
817 			dimm->nr_pages	= (size >> PAGE_SHIFT) / csi->nr_channels;
818 			dimm->grain	= SYNPS_EDAC_ERR_GRAIN;
819 			dimm->dtype	= p_data->get_dtype(priv->baseaddr);
820 		}
821 	}
822 }
823 
824 /**
825  * mc_init - Initialize one driver instance.
826  * @mci:	EDAC memory controller instance.
827  * @pdev:	platform device.
828  *
829  * Perform initialization of the EDAC memory controller instance and
830  * related driver-private data associated with the memory controller the
831  * instance is bound to.
832  */
833 static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev)
834 {
835 	struct synps_edac_priv *priv;
836 
837 	mci->pdev = &pdev->dev;
838 	priv = mci->pvt_info;
839 	platform_set_drvdata(pdev, mci);
840 
841 	/* Initialize controller capabilities and configuration */
842 	mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2;
843 	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
844 	mci->scrub_cap = SCRUB_HW_SRC;
845 	mci->scrub_mode = SCRUB_NONE;
846 
847 	mci->edac_cap = EDAC_FLAG_SECDED;
848 	mci->ctl_name = "synps_ddr_controller";
849 	mci->dev_name = SYNPS_EDAC_MOD_STRING;
850 	mci->mod_name = SYNPS_EDAC_MOD_VER;
851 
852 	if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
853 		edac_op_state = EDAC_OPSTATE_INT;
854 	} else {
855 		edac_op_state = EDAC_OPSTATE_POLL;
856 		mci->edac_check = check_errors;
857 	}
858 
859 	mci->ctl_page_to_phys = NULL;
860 
861 	init_csrows(mci);
862 }
863 
864 static int setup_irq(struct mem_ctl_info *mci,
865 		     struct platform_device *pdev)
866 {
867 	struct synps_edac_priv *priv = mci->pvt_info;
868 	int ret, irq;
869 
870 	irq = platform_get_irq(pdev, 0);
871 	if (irq < 0) {
872 		edac_printk(KERN_ERR, EDAC_MC,
873 			    "No IRQ %d in DT\n", irq);
874 		return irq;
875 	}
876 
877 	ret = devm_request_irq(&pdev->dev, irq, intr_handler,
878 			       0, dev_name(&pdev->dev), mci);
879 	if (ret < 0) {
880 		edac_printk(KERN_ERR, EDAC_MC, "Failed to request IRQ\n");
881 		return ret;
882 	}
883 
884 	enable_intr(priv);
885 
886 	return 0;
887 }
888 
889 static const struct synps_platform_data zynq_edac_def = {
890 	.get_error_info	= zynq_get_error_info,
891 	.get_mtype	= zynq_get_mtype,
892 	.get_dtype	= zynq_get_dtype,
893 	.get_ecc_state	= zynq_get_ecc_state,
894 	.quirks		= 0,
895 };
896 
897 static const struct synps_platform_data zynqmp_edac_def = {
898 	.get_error_info	= zynqmp_get_error_info,
899 	.get_mtype	= zynqmp_get_mtype,
900 	.get_dtype	= zynqmp_get_dtype,
901 	.get_ecc_state	= zynqmp_get_ecc_state,
902 	.quirks         = (DDR_ECC_INTR_SUPPORT
903 #ifdef CONFIG_EDAC_DEBUG
904 			  | DDR_ECC_DATA_POISON_SUPPORT
905 #endif
906 			  ),
907 };
908 
909 static const struct synps_platform_data synopsys_edac_def = {
910 	.get_error_info	= zynqmp_get_error_info,
911 	.get_mtype	= zynqmp_get_mtype,
912 	.get_dtype	= zynqmp_get_dtype,
913 	.get_ecc_state	= zynqmp_get_ecc_state,
914 	.quirks         = (DDR_ECC_INTR_SUPPORT | DDR_ECC_INTR_SELF_CLEAR
915 #ifdef CONFIG_EDAC_DEBUG
916 			  | DDR_ECC_DATA_POISON_SUPPORT
917 #endif
918 			  ),
919 };
920 
921 
922 static const struct of_device_id synps_edac_match[] = {
923 	{
924 		.compatible = "xlnx,zynq-ddrc-a05",
925 		.data = (void *)&zynq_edac_def
926 	},
927 	{
928 		.compatible = "xlnx,zynqmp-ddrc-2.40a",
929 		.data = (void *)&zynqmp_edac_def
930 	},
931 	{
932 		.compatible = "snps,ddrc-3.80a",
933 		.data = (void *)&synopsys_edac_def
934 	},
935 	{
936 		/* end of table */
937 	}
938 };
939 
940 MODULE_DEVICE_TABLE(of, synps_edac_match);
941 
942 #ifdef CONFIG_EDAC_DEBUG
943 #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
944 
945 /**
946  * ddr_poison_setup -	Update poison registers.
947  * @priv:		DDR memory controller private instance data.
948  *
949  * Update poison registers as per DDR mapping.
950  * Return: none.
951  */
952 static void ddr_poison_setup(struct synps_edac_priv *priv)
953 {
954 	int col = 0, row = 0, bank = 0, bankgrp = 0, rank = 0, regval;
955 	int index;
956 	ulong hif_addr = 0;
957 
958 	hif_addr = priv->poison_addr >> 3;
959 
960 	for (index = 0; index < DDR_MAX_ROW_SHIFT; index++) {
961 		if (priv->row_shift[index])
962 			row |= (((hif_addr >> priv->row_shift[index]) &
963 						BIT(0)) << index);
964 		else
965 			break;
966 	}
967 
968 	for (index = 0; index < DDR_MAX_COL_SHIFT; index++) {
969 		if (priv->col_shift[index] || index < 3)
970 			col |= (((hif_addr >> priv->col_shift[index]) &
971 						BIT(0)) << index);
972 		else
973 			break;
974 	}
975 
976 	for (index = 0; index < DDR_MAX_BANK_SHIFT; index++) {
977 		if (priv->bank_shift[index])
978 			bank |= (((hif_addr >> priv->bank_shift[index]) &
979 						BIT(0)) << index);
980 		else
981 			break;
982 	}
983 
984 	for (index = 0; index < DDR_MAX_BANKGRP_SHIFT; index++) {
985 		if (priv->bankgrp_shift[index])
986 			bankgrp |= (((hif_addr >> priv->bankgrp_shift[index])
987 						& BIT(0)) << index);
988 		else
989 			break;
990 	}
991 
992 	if (priv->rank_shift[0])
993 		rank = (hif_addr >> priv->rank_shift[0]) & BIT(0);
994 
995 	regval = (rank << ECC_POISON0_RANK_SHIFT) & ECC_POISON0_RANK_MASK;
996 	regval |= (col << ECC_POISON0_COLUMN_SHIFT) & ECC_POISON0_COLUMN_MASK;
997 	writel(regval, priv->baseaddr + ECC_POISON0_OFST);
998 
999 	regval = (bankgrp << ECC_POISON1_BG_SHIFT) & ECC_POISON1_BG_MASK;
1000 	regval |= (bank << ECC_POISON1_BANKNR_SHIFT) & ECC_POISON1_BANKNR_MASK;
1001 	regval |= (row << ECC_POISON1_ROW_SHIFT) & ECC_POISON1_ROW_MASK;
1002 	writel(regval, priv->baseaddr + ECC_POISON1_OFST);
1003 }
1004 
1005 static ssize_t inject_data_error_show(struct device *dev,
1006 				      struct device_attribute *mattr,
1007 				      char *data)
1008 {
1009 	struct mem_ctl_info *mci = to_mci(dev);
1010 	struct synps_edac_priv *priv = mci->pvt_info;
1011 
1012 	return sprintf(data, "Poison0 Addr: 0x%08x\n\rPoison1 Addr: 0x%08x\n\r"
1013 			"Error injection Address: 0x%lx\n\r",
1014 			readl(priv->baseaddr + ECC_POISON0_OFST),
1015 			readl(priv->baseaddr + ECC_POISON1_OFST),
1016 			priv->poison_addr);
1017 }
1018 
1019 static ssize_t inject_data_error_store(struct device *dev,
1020 				       struct device_attribute *mattr,
1021 				       const char *data, size_t count)
1022 {
1023 	struct mem_ctl_info *mci = to_mci(dev);
1024 	struct synps_edac_priv *priv = mci->pvt_info;
1025 
1026 	if (kstrtoul(data, 0, &priv->poison_addr))
1027 		return -EINVAL;
1028 
1029 	ddr_poison_setup(priv);
1030 
1031 	return count;
1032 }
1033 
1034 static ssize_t inject_data_poison_show(struct device *dev,
1035 				       struct device_attribute *mattr,
1036 				       char *data)
1037 {
1038 	struct mem_ctl_info *mci = to_mci(dev);
1039 	struct synps_edac_priv *priv = mci->pvt_info;
1040 
1041 	return sprintf(data, "Data Poisoning: %s\n\r",
1042 			(((readl(priv->baseaddr + ECC_CFG1_OFST)) & 0x3) == 0x3)
1043 			? ("Correctable Error") : ("UnCorrectable Error"));
1044 }
1045 
1046 static ssize_t inject_data_poison_store(struct device *dev,
1047 					struct device_attribute *mattr,
1048 					const char *data, size_t count)
1049 {
1050 	struct mem_ctl_info *mci = to_mci(dev);
1051 	struct synps_edac_priv *priv = mci->pvt_info;
1052 
1053 	writel(0, priv->baseaddr + DDRC_SWCTL);
1054 	if (strncmp(data, "CE", 2) == 0)
1055 		writel(ECC_CEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST);
1056 	else
1057 		writel(ECC_UEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST);
1058 	writel(1, priv->baseaddr + DDRC_SWCTL);
1059 
1060 	return count;
1061 }
1062 
1063 static DEVICE_ATTR_RW(inject_data_error);
1064 static DEVICE_ATTR_RW(inject_data_poison);
1065 
1066 static int edac_create_sysfs_attributes(struct mem_ctl_info *mci)
1067 {
1068 	int rc;
1069 
1070 	rc = device_create_file(&mci->dev, &dev_attr_inject_data_error);
1071 	if (rc < 0)
1072 		return rc;
1073 	rc = device_create_file(&mci->dev, &dev_attr_inject_data_poison);
1074 	if (rc < 0)
1075 		return rc;
1076 	return 0;
1077 }
1078 
1079 static void edac_remove_sysfs_attributes(struct mem_ctl_info *mci)
1080 {
1081 	device_remove_file(&mci->dev, &dev_attr_inject_data_error);
1082 	device_remove_file(&mci->dev, &dev_attr_inject_data_poison);
1083 }
1084 
1085 static void setup_row_address_map(struct synps_edac_priv *priv, u32 *addrmap)
1086 {
1087 	u32 addrmap_row_b2_10;
1088 	int index;
1089 
1090 	priv->row_shift[0] = (addrmap[5] & ROW_MAX_VAL_MASK) + ROW_B0_BASE;
1091 	priv->row_shift[1] = ((addrmap[5] >> 8) &
1092 			ROW_MAX_VAL_MASK) + ROW_B1_BASE;
1093 
1094 	addrmap_row_b2_10 = (addrmap[5] >> 16) & ROW_MAX_VAL_MASK;
1095 	if (addrmap_row_b2_10 != ROW_MAX_VAL_MASK) {
1096 		for (index = 2; index < 11; index++)
1097 			priv->row_shift[index] = addrmap_row_b2_10 +
1098 				index + ROW_B0_BASE;
1099 
1100 	} else {
1101 		priv->row_shift[2] = (addrmap[9] &
1102 				ROW_MAX_VAL_MASK) + ROW_B2_BASE;
1103 		priv->row_shift[3] = ((addrmap[9] >> 8) &
1104 				ROW_MAX_VAL_MASK) + ROW_B3_BASE;
1105 		priv->row_shift[4] = ((addrmap[9] >> 16) &
1106 				ROW_MAX_VAL_MASK) + ROW_B4_BASE;
1107 		priv->row_shift[5] = ((addrmap[9] >> 24) &
1108 				ROW_MAX_VAL_MASK) + ROW_B5_BASE;
1109 		priv->row_shift[6] = (addrmap[10] &
1110 				ROW_MAX_VAL_MASK) + ROW_B6_BASE;
1111 		priv->row_shift[7] = ((addrmap[10] >> 8) &
1112 				ROW_MAX_VAL_MASK) + ROW_B7_BASE;
1113 		priv->row_shift[8] = ((addrmap[10] >> 16) &
1114 				ROW_MAX_VAL_MASK) + ROW_B8_BASE;
1115 		priv->row_shift[9] = ((addrmap[10] >> 24) &
1116 				ROW_MAX_VAL_MASK) + ROW_B9_BASE;
1117 		priv->row_shift[10] = (addrmap[11] &
1118 				ROW_MAX_VAL_MASK) + ROW_B10_BASE;
1119 	}
1120 
1121 	priv->row_shift[11] = (((addrmap[5] >> 24) & ROW_MAX_VAL_MASK) ==
1122 				ROW_MAX_VAL_MASK) ? 0 : (((addrmap[5] >> 24) &
1123 				ROW_MAX_VAL_MASK) + ROW_B11_BASE);
1124 	priv->row_shift[12] = ((addrmap[6] & ROW_MAX_VAL_MASK) ==
1125 				ROW_MAX_VAL_MASK) ? 0 : ((addrmap[6] &
1126 				ROW_MAX_VAL_MASK) + ROW_B12_BASE);
1127 	priv->row_shift[13] = (((addrmap[6] >> 8) & ROW_MAX_VAL_MASK) ==
1128 				ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 8) &
1129 				ROW_MAX_VAL_MASK) + ROW_B13_BASE);
1130 	priv->row_shift[14] = (((addrmap[6] >> 16) & ROW_MAX_VAL_MASK) ==
1131 				ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 16) &
1132 				ROW_MAX_VAL_MASK) + ROW_B14_BASE);
1133 	priv->row_shift[15] = (((addrmap[6] >> 24) & ROW_MAX_VAL_MASK) ==
1134 				ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 24) &
1135 				ROW_MAX_VAL_MASK) + ROW_B15_BASE);
1136 	priv->row_shift[16] = ((addrmap[7] & ROW_MAX_VAL_MASK) ==
1137 				ROW_MAX_VAL_MASK) ? 0 : ((addrmap[7] &
1138 				ROW_MAX_VAL_MASK) + ROW_B16_BASE);
1139 	priv->row_shift[17] = (((addrmap[7] >> 8) & ROW_MAX_VAL_MASK) ==
1140 				ROW_MAX_VAL_MASK) ? 0 : (((addrmap[7] >> 8) &
1141 				ROW_MAX_VAL_MASK) + ROW_B17_BASE);
1142 }
1143 
1144 static void setup_column_address_map(struct synps_edac_priv *priv, u32 *addrmap)
1145 {
1146 	u32 width, memtype;
1147 	int index;
1148 
1149 	memtype = readl(priv->baseaddr + CTRL_OFST);
1150 	width = (memtype & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT;
1151 
1152 	priv->col_shift[0] = 0;
1153 	priv->col_shift[1] = 1;
1154 	priv->col_shift[2] = (addrmap[2] & COL_MAX_VAL_MASK) + COL_B2_BASE;
1155 	priv->col_shift[3] = ((addrmap[2] >> 8) &
1156 			COL_MAX_VAL_MASK) + COL_B3_BASE;
1157 	priv->col_shift[4] = (((addrmap[2] >> 16) & COL_MAX_VAL_MASK) ==
1158 			COL_MAX_VAL_MASK) ? 0 : (((addrmap[2] >> 16) &
1159 					COL_MAX_VAL_MASK) + COL_B4_BASE);
1160 	priv->col_shift[5] = (((addrmap[2] >> 24) & COL_MAX_VAL_MASK) ==
1161 			COL_MAX_VAL_MASK) ? 0 : (((addrmap[2] >> 24) &
1162 					COL_MAX_VAL_MASK) + COL_B5_BASE);
1163 	priv->col_shift[6] = ((addrmap[3] & COL_MAX_VAL_MASK) ==
1164 			COL_MAX_VAL_MASK) ? 0 : ((addrmap[3] &
1165 					COL_MAX_VAL_MASK) + COL_B6_BASE);
1166 	priv->col_shift[7] = (((addrmap[3] >> 8) & COL_MAX_VAL_MASK) ==
1167 			COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 8) &
1168 					COL_MAX_VAL_MASK) + COL_B7_BASE);
1169 	priv->col_shift[8] = (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) ==
1170 			COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 16) &
1171 					COL_MAX_VAL_MASK) + COL_B8_BASE);
1172 	priv->col_shift[9] = (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) ==
1173 			COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 24) &
1174 					COL_MAX_VAL_MASK) + COL_B9_BASE);
1175 	if (width == DDRCTL_EWDTH_64) {
1176 		if (memtype & MEM_TYPE_LPDDR3) {
1177 			priv->col_shift[10] = ((addrmap[4] &
1178 				COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1179 				((addrmap[4] & COL_MAX_VAL_MASK) +
1180 				 COL_B10_BASE);
1181 			priv->col_shift[11] = (((addrmap[4] >> 8) &
1182 				COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1183 				(((addrmap[4] >> 8) & COL_MAX_VAL_MASK) +
1184 				 COL_B11_BASE);
1185 		} else {
1186 			priv->col_shift[11] = ((addrmap[4] &
1187 				COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1188 				((addrmap[4] & COL_MAX_VAL_MASK) +
1189 				 COL_B10_BASE);
1190 			priv->col_shift[13] = (((addrmap[4] >> 8) &
1191 				COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1192 				(((addrmap[4] >> 8) & COL_MAX_VAL_MASK) +
1193 				 COL_B11_BASE);
1194 		}
1195 	} else if (width == DDRCTL_EWDTH_32) {
1196 		if (memtype & MEM_TYPE_LPDDR3) {
1197 			priv->col_shift[10] = (((addrmap[3] >> 24) &
1198 				COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1199 				(((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
1200 				 COL_B9_BASE);
1201 			priv->col_shift[11] = ((addrmap[4] &
1202 				COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1203 				((addrmap[4] & COL_MAX_VAL_MASK) +
1204 				 COL_B10_BASE);
1205 		} else {
1206 			priv->col_shift[11] = (((addrmap[3] >> 24) &
1207 				COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1208 				(((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
1209 				 COL_B9_BASE);
1210 			priv->col_shift[13] = ((addrmap[4] &
1211 				COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1212 				((addrmap[4] & COL_MAX_VAL_MASK) +
1213 				 COL_B10_BASE);
1214 		}
1215 	} else {
1216 		if (memtype & MEM_TYPE_LPDDR3) {
1217 			priv->col_shift[10] = (((addrmap[3] >> 16) &
1218 				COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1219 				(((addrmap[3] >> 16) & COL_MAX_VAL_MASK) +
1220 				 COL_B8_BASE);
1221 			priv->col_shift[11] = (((addrmap[3] >> 24) &
1222 				COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1223 				(((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
1224 				 COL_B9_BASE);
1225 			priv->col_shift[13] = ((addrmap[4] &
1226 				COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1227 				((addrmap[4] & COL_MAX_VAL_MASK) +
1228 				 COL_B10_BASE);
1229 		} else {
1230 			priv->col_shift[11] = (((addrmap[3] >> 16) &
1231 				COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1232 				(((addrmap[3] >> 16) & COL_MAX_VAL_MASK) +
1233 				 COL_B8_BASE);
1234 			priv->col_shift[13] = (((addrmap[3] >> 24) &
1235 				COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1236 				(((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
1237 				 COL_B9_BASE);
1238 		}
1239 	}
1240 
1241 	if (width) {
1242 		for (index = 9; index > width; index--) {
1243 			priv->col_shift[index] = priv->col_shift[index - width];
1244 			priv->col_shift[index - width] = 0;
1245 		}
1246 	}
1247 
1248 }
1249 
1250 static void setup_bank_address_map(struct synps_edac_priv *priv, u32 *addrmap)
1251 {
1252 	priv->bank_shift[0] = (addrmap[1] & BANK_MAX_VAL_MASK) + BANK_B0_BASE;
1253 	priv->bank_shift[1] = ((addrmap[1] >> 8) &
1254 				BANK_MAX_VAL_MASK) + BANK_B1_BASE;
1255 	priv->bank_shift[2] = (((addrmap[1] >> 16) &
1256 				BANK_MAX_VAL_MASK) == BANK_MAX_VAL_MASK) ? 0 :
1257 				(((addrmap[1] >> 16) & BANK_MAX_VAL_MASK) +
1258 				 BANK_B2_BASE);
1259 
1260 }
1261 
1262 static void setup_bg_address_map(struct synps_edac_priv *priv, u32 *addrmap)
1263 {
1264 	priv->bankgrp_shift[0] = (addrmap[8] &
1265 				BANKGRP_MAX_VAL_MASK) + BANKGRP_B0_BASE;
1266 	priv->bankgrp_shift[1] = (((addrmap[8] >> 8) & BANKGRP_MAX_VAL_MASK) ==
1267 				BANKGRP_MAX_VAL_MASK) ? 0 : (((addrmap[8] >> 8)
1268 				& BANKGRP_MAX_VAL_MASK) + BANKGRP_B1_BASE);
1269 
1270 }
1271 
1272 static void setup_rank_address_map(struct synps_edac_priv *priv, u32 *addrmap)
1273 {
1274 	priv->rank_shift[0] = ((addrmap[0] & RANK_MAX_VAL_MASK) ==
1275 				RANK_MAX_VAL_MASK) ? 0 : ((addrmap[0] &
1276 				RANK_MAX_VAL_MASK) + RANK_B0_BASE);
1277 }
1278 
1279 /**
1280  * setup_address_map -	Set Address Map by querying ADDRMAP registers.
1281  * @priv:		DDR memory controller private instance data.
1282  *
1283  * Set Address Map by querying ADDRMAP registers.
1284  *
1285  * Return: none.
1286  */
1287 static void setup_address_map(struct synps_edac_priv *priv)
1288 {
1289 	u32 addrmap[12];
1290 	int index;
1291 
1292 	for (index = 0; index < 12; index++) {
1293 		u32 addrmap_offset;
1294 
1295 		addrmap_offset = ECC_ADDRMAP0_OFFSET + (index * 4);
1296 		addrmap[index] = readl(priv->baseaddr + addrmap_offset);
1297 	}
1298 
1299 	setup_row_address_map(priv, addrmap);
1300 
1301 	setup_column_address_map(priv, addrmap);
1302 
1303 	setup_bank_address_map(priv, addrmap);
1304 
1305 	setup_bg_address_map(priv, addrmap);
1306 
1307 	setup_rank_address_map(priv, addrmap);
1308 }
1309 #endif /* CONFIG_EDAC_DEBUG */
1310 
1311 /**
1312  * mc_probe - Check controller and bind driver.
1313  * @pdev:	platform device.
1314  *
1315  * Probe a specific controller instance for binding with the driver.
1316  *
1317  * Return: 0 if the controller instance was successfully bound to the
1318  * driver; otherwise, < 0 on error.
1319  */
1320 static int mc_probe(struct platform_device *pdev)
1321 {
1322 	const struct synps_platform_data *p_data;
1323 	struct edac_mc_layer layers[2];
1324 	struct synps_edac_priv *priv;
1325 	struct mem_ctl_info *mci;
1326 	void __iomem *baseaddr;
1327 	int rc;
1328 
1329 	baseaddr = devm_platform_ioremap_resource(pdev, 0);
1330 	if (IS_ERR(baseaddr))
1331 		return PTR_ERR(baseaddr);
1332 
1333 	p_data = of_device_get_match_data(&pdev->dev);
1334 	if (!p_data)
1335 		return -ENODEV;
1336 
1337 	if (!p_data->get_ecc_state(baseaddr)) {
1338 		edac_printk(KERN_INFO, EDAC_MC, "ECC not enabled\n");
1339 		return -ENXIO;
1340 	}
1341 
1342 	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
1343 	layers[0].size = SYNPS_EDAC_NR_CSROWS;
1344 	layers[0].is_virt_csrow = true;
1345 	layers[1].type = EDAC_MC_LAYER_CHANNEL;
1346 	layers[1].size = SYNPS_EDAC_NR_CHANS;
1347 	layers[1].is_virt_csrow = false;
1348 
1349 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
1350 			    sizeof(struct synps_edac_priv));
1351 	if (!mci) {
1352 		edac_printk(KERN_ERR, EDAC_MC,
1353 			    "Failed memory allocation for mc instance\n");
1354 		return -ENOMEM;
1355 	}
1356 
1357 	priv = mci->pvt_info;
1358 	priv->baseaddr = baseaddr;
1359 	priv->p_data = p_data;
1360 
1361 	mc_init(mci, pdev);
1362 
1363 	if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
1364 		rc = setup_irq(mci, pdev);
1365 		if (rc)
1366 			goto free_edac_mc;
1367 	}
1368 
1369 	rc = edac_mc_add_mc(mci);
1370 	if (rc) {
1371 		edac_printk(KERN_ERR, EDAC_MC,
1372 			    "Failed to register with EDAC core\n");
1373 		goto free_edac_mc;
1374 	}
1375 
1376 #ifdef CONFIG_EDAC_DEBUG
1377 	if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) {
1378 		rc = edac_create_sysfs_attributes(mci);
1379 		if (rc) {
1380 			edac_printk(KERN_ERR, EDAC_MC,
1381 					"Failed to create sysfs entries\n");
1382 			goto free_edac_mc;
1383 		}
1384 	}
1385 
1386 	if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)
1387 		setup_address_map(priv);
1388 #endif
1389 
1390 	/*
1391 	 * Start capturing the correctable and uncorrectable errors. A write of
1392 	 * 0 starts the counters.
1393 	 */
1394 	if (!(priv->p_data->quirks & DDR_ECC_INTR_SUPPORT))
1395 		writel(0x0, baseaddr + ECC_CTRL_OFST);
1396 
1397 	return rc;
1398 
1399 free_edac_mc:
1400 	edac_mc_free(mci);
1401 
1402 	return rc;
1403 }
1404 
1405 /**
1406  * mc_remove - Unbind driver from controller.
1407  * @pdev:	Platform device.
1408  *
1409  * Return: Unconditionally 0
1410  */
1411 static void mc_remove(struct platform_device *pdev)
1412 {
1413 	struct mem_ctl_info *mci = platform_get_drvdata(pdev);
1414 	struct synps_edac_priv *priv = mci->pvt_info;
1415 
1416 	if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)
1417 		disable_intr(priv);
1418 
1419 #ifdef CONFIG_EDAC_DEBUG
1420 	if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT)
1421 		edac_remove_sysfs_attributes(mci);
1422 #endif
1423 
1424 	edac_mc_del_mc(&pdev->dev);
1425 	edac_mc_free(mci);
1426 }
1427 
1428 static struct platform_driver synps_edac_mc_driver = {
1429 	.driver = {
1430 		   .name = "synopsys-edac",
1431 		   .of_match_table = synps_edac_match,
1432 		   },
1433 	.probe = mc_probe,
1434 	.remove_new = mc_remove,
1435 };
1436 
1437 module_platform_driver(synps_edac_mc_driver);
1438 
1439 MODULE_AUTHOR("Xilinx Inc");
1440 MODULE_DESCRIPTION("Synopsys DDR ECC driver");
1441 MODULE_LICENSE("GPL v2");
1442