1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Common codes for both the skx_edac driver and Intel 10nm server EDAC driver. 4 * Originally split out from the skx_edac driver. 5 * 6 * Copyright (c) 2018, Intel Corporation. 7 */ 8 9 #ifndef _SKX_COMM_EDAC_H 10 #define _SKX_COMM_EDAC_H 11 12 #include <linux/bits.h> 13 #include <asm/mce.h> 14 15 #define MSG_SIZE 1024 16 17 /* 18 * Debug macros 19 */ 20 #define skx_printk(level, fmt, arg...) \ 21 edac_printk(level, "skx", fmt, ##arg) 22 23 #define skx_mc_printk(mci, level, fmt, arg...) \ 24 edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg) 25 26 /* 27 * Get a bit field at register value <v>, from bit <lo> to bit <hi> 28 */ 29 #define GET_BITFIELD(v, lo, hi) \ 30 (((v) & GENMASK_ULL((hi), (lo))) >> (lo)) 31 32 #define SKX_NUM_CHANNELS 3 /* Channels per memory controller */ 33 #define SKX_NUM_DIMMS 2 /* Max DIMMS per channel */ 34 35 #define I10NM_NUM_DDR_CHANNELS 2 36 #define I10NM_NUM_DDR_DIMMS 2 37 38 #define I10NM_NUM_HBM_CHANNELS 2 39 #define I10NM_NUM_HBM_DIMMS 1 40 41 #define I10NM_NUM_CHANNELS MAX(I10NM_NUM_DDR_CHANNELS, I10NM_NUM_HBM_CHANNELS) 42 #define I10NM_NUM_DIMMS MAX(I10NM_NUM_DDR_DIMMS, I10NM_NUM_HBM_DIMMS) 43 44 #define NUM_CHANNELS MAX(SKX_NUM_CHANNELS, I10NM_NUM_CHANNELS) 45 #define NUM_DIMMS MAX(SKX_NUM_DIMMS, I10NM_NUM_DIMMS) 46 47 #define IS_DIMM_PRESENT(r) GET_BITFIELD(r, 15, 15) 48 #define IS_NVDIMM_PRESENT(r, i) GET_BITFIELD(r, i, i) 49 50 #define MCI_MISC_ECC_MODE(m) (((m) >> 59) & 15) 51 #define MCI_MISC_ECC_DDRT 8 /* read from DDRT */ 52 53 /* 54 * According to Intel Architecture spec vol 3B, 55 * Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding" 56 * memory errors should fit one of these masks: 57 * 000f 0000 1mmm cccc (binary) 58 * 000f 0010 1mmm cccc (binary) [RAM used as cache] 59 * where: 60 * f = Correction Report Filtering Bit. If 1, subsequent errors 61 * won't be shown 62 * mmm = error type 63 * cccc = channel 64 */ 65 #define MCACOD_MEM_ERR_MASK 0xef80 66 /* 67 * Errors from either the memory of the 1-level memory system or the 68 * 2nd level memory (the slow "far" memory) of the 2-level memory system. 69 */ 70 #define MCACOD_MEM_CTL_ERR 0x80 71 /* 72 * Errors from the 1st level memory (the fast "near" memory as cache) 73 * of the 2-level memory system. 74 */ 75 #define MCACOD_EXT_MEM_ERR 0x280 76 77 /* Max RRL register sets per {,sub-,pseudo-}channel. */ 78 #define NUM_RRL_SET 4 79 /* Max RRL registers per set. */ 80 #define NUM_RRL_REG 6 81 /* Max correctable error count registers. */ 82 #define NUM_CECNT_REG 8 83 84 /* Modes of RRL register set. */ 85 enum rrl_mode { 86 /* Last read error from patrol scrub. */ 87 LRE_SCRUB, 88 /* Last read error from demand. */ 89 LRE_DEMAND, 90 /* First read error from patrol scrub. */ 91 FRE_SCRUB, 92 /* First read error from demand. */ 93 FRE_DEMAND, 94 }; 95 96 /* RRL registers per {,sub-,pseudo-}channel. */ 97 struct reg_rrl { 98 /* RRL register parts. */ 99 int set_num, reg_num; 100 enum rrl_mode modes[NUM_RRL_SET]; 101 u32 offsets[NUM_RRL_SET][NUM_RRL_REG]; 102 /* RRL register widths in byte per set. */ 103 u8 widths[NUM_RRL_REG]; 104 /* RRL control bits of the first register per set. */ 105 u32 v_mask; 106 u32 uc_mask; 107 u32 over_mask; 108 u32 en_patspr_mask; 109 u32 noover_mask; 110 u32 en_mask; 111 112 /* CORRERRCNT register parts. */ 113 int cecnt_num; 114 u32 cecnt_offsets[NUM_CECNT_REG]; 115 u8 cecnt_widths[NUM_CECNT_REG]; 116 }; 117 118 /* 119 * Each cpu socket contains some pci devices that provide global 120 * information, and also some that are local to each of the two 121 * memory controllers on the die. 122 */ 123 struct skx_dev { 124 struct list_head list; 125 u8 bus[4]; 126 int seg; 127 struct pci_dev *sad_all; 128 struct pci_dev *util_all; 129 struct pci_dev *uracu; /* for i10nm CPU */ 130 struct pci_dev *pcu_cr3; /* for HBM memory detection */ 131 u32 mcroute; 132 int num_imc; 133 struct skx_imc { 134 struct mem_ctl_info *mci; 135 struct pci_dev *mdev; /* for i10nm CPU */ 136 void __iomem *mbase; /* for i10nm CPU */ 137 int chan_mmio_sz; /* for i10nm CPU */ 138 int num_channels; /* channels per memory controller */ 139 int num_dimms; /* dimms per channel */ 140 bool hbm_mc; 141 u8 mc; /* system wide mc# */ 142 u8 lmc; /* socket relative mc# */ 143 u8 src_id; 144 /* 145 * Some server BIOS may hide certain memory controllers, and the 146 * EDAC driver skips those hidden memory controllers. However, the 147 * ADXL still decodes memory error address using physical memory 148 * controller indices. The mapping table is used to convert the 149 * physical indices (reported by ADXL) to the logical indices 150 * (used the EDAC driver) of present memory controllers during the 151 * error handling process. 152 */ 153 u8 mc_mapping; 154 struct skx_channel { 155 struct pci_dev *cdev; 156 struct pci_dev *edev; 157 /* 158 * Two groups of RRL control registers per channel to save default RRL 159 * settings of two {sub-,pseudo-}channels in Linux RRL control mode. 160 */ 161 u32 rrl_ctl[2][NUM_RRL_SET]; 162 struct skx_dimm { 163 u8 close_pg; 164 u8 bank_xor_enable; 165 u8 fine_grain_bank; 166 u8 rowbits; 167 u8 colbits; 168 } dimms[NUM_DIMMS]; 169 } chan[NUM_CHANNELS]; 170 } imc[]; 171 }; 172 173 struct skx_pvt { 174 struct skx_imc *imc; 175 }; 176 177 enum type { 178 SKX, 179 I10NM, 180 SPR, 181 GNR 182 }; 183 184 enum { 185 INDEX_SOCKET, 186 INDEX_MEMCTRL, 187 INDEX_CHANNEL, 188 INDEX_DIMM, 189 INDEX_CS, 190 INDEX_NM_FIRST, 191 INDEX_NM_MEMCTRL = INDEX_NM_FIRST, 192 INDEX_NM_CHANNEL, 193 INDEX_NM_DIMM, 194 INDEX_NM_CS, 195 INDEX_MAX 196 }; 197 198 enum error_source { 199 ERR_SRC_1LM, 200 ERR_SRC_2LM_NM, 201 ERR_SRC_2LM_FM, 202 ERR_SRC_NOT_MEMORY, 203 }; 204 205 #define BIT_NM_MEMCTRL BIT_ULL(INDEX_NM_MEMCTRL) 206 #define BIT_NM_CHANNEL BIT_ULL(INDEX_NM_CHANNEL) 207 #define BIT_NM_DIMM BIT_ULL(INDEX_NM_DIMM) 208 #define BIT_NM_CS BIT_ULL(INDEX_NM_CS) 209 210 struct decoded_addr { 211 struct mce *mce; 212 struct skx_dev *dev; 213 u64 addr; 214 int socket; 215 int imc; 216 int channel; 217 u64 chan_addr; 218 int sktways; 219 int chanways; 220 int dimm; 221 int cs; 222 int rank; 223 int channel_rank; 224 u64 rank_address; 225 int row; 226 int column; 227 int bank_address; 228 int bank_group; 229 bool decoded_by_adxl; 230 }; 231 232 struct pci_bdf { 233 u32 bus : 8; 234 u32 dev : 5; 235 u32 fun : 3; 236 }; 237 238 struct res_config { 239 enum type type; 240 /* Configuration agent device ID */ 241 unsigned int decs_did; 242 /* Default bus number configuration register offset */ 243 int busno_cfg_offset; 244 /* DDR memory controllers per socket */ 245 int ddr_imc_num; 246 /* DDR channels per DDR memory controller */ 247 int ddr_chan_num; 248 /* DDR DIMMs per DDR memory channel */ 249 int ddr_dimm_num; 250 /* Per DDR channel memory-mapped I/O size */ 251 int ddr_chan_mmio_sz; 252 /* HBM memory controllers per socket */ 253 int hbm_imc_num; 254 /* HBM channels per HBM memory controller */ 255 int hbm_chan_num; 256 /* HBM DIMMs per HBM memory channel */ 257 int hbm_dimm_num; 258 /* Per HBM channel memory-mapped I/O size */ 259 int hbm_chan_mmio_sz; 260 bool support_ddr5; 261 /* SAD device BDF */ 262 struct pci_bdf sad_all_bdf; 263 /* PCU device BDF */ 264 struct pci_bdf pcu_cr3_bdf; 265 /* UTIL device BDF */ 266 struct pci_bdf util_all_bdf; 267 /* URACU device BDF */ 268 struct pci_bdf uracu_bdf; 269 /* DDR mdev device BDF */ 270 struct pci_bdf ddr_mdev_bdf; 271 /* HBM mdev device BDF */ 272 struct pci_bdf hbm_mdev_bdf; 273 int sad_all_offset; 274 /* RRL register sets per DDR channel */ 275 struct reg_rrl *reg_rrl_ddr; 276 /* RRL register sets per HBM channel */ 277 struct reg_rrl *reg_rrl_hbm[2]; 278 }; 279 280 typedef int (*get_dimm_config_f)(struct mem_ctl_info *mci, 281 struct res_config *cfg); 282 typedef bool (*skx_decode_f)(struct decoded_addr *res); 283 typedef void (*skx_show_retry_log_f)(struct decoded_addr *res, char *msg, int len, bool scrub_err); 284 285 int skx_adxl_get(void); 286 void skx_adxl_put(void); 287 void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log); 288 void skx_set_mem_cfg(bool mem_cfg_2lm); 289 void skx_set_res_cfg(struct res_config *cfg); 290 void skx_set_mc_mapping(struct skx_dev *d, u8 pmc, u8 lmc); 291 292 int skx_get_src_id(struct skx_dev *d, int off, u8 *id); 293 294 int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list); 295 296 int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm); 297 298 int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm, 299 struct skx_imc *imc, int chan, int dimmno, 300 struct res_config *cfg); 301 302 int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc, 303 int chan, int dimmno, const char *mod_str); 304 305 int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev, 306 const char *ctl_name, const char *mod_str, 307 get_dimm_config_f get_dimm_config, 308 struct res_config *cfg); 309 310 int skx_mce_check_error(struct notifier_block *nb, unsigned long val, 311 void *data); 312 313 void skx_remove(void); 314 315 #ifdef CONFIG_EDAC_DEBUG 316 void skx_setup_debug(const char *name); 317 void skx_teardown_debug(void); 318 #else 319 static inline void skx_setup_debug(const char *name) {} 320 static inline void skx_teardown_debug(void) {} 321 #endif 322 323 #endif /* _SKX_COMM_EDAC_H */ 324