1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 4 * Shared code by both skx_edac and i10nm_edac. Originally split out 5 * from the skx_edac driver. 6 * 7 * This file is linked into both skx_edac and i10nm_edac drivers. In 8 * order to avoid link errors, this file must be like a pure library 9 * without including symbols and defines which would otherwise conflict, 10 * when linked once into a module and into a built-in object, at the 11 * same time. For example, __this_module symbol references when that 12 * file is being linked into a built-in object. 13 * 14 * Copyright (c) 2018, Intel Corporation. 15 */ 16 17 #include <linux/topology.h> 18 #include <linux/acpi.h> 19 #include <linux/dmi.h> 20 #include <linux/adxl.h> 21 #include <linux/overflow.h> 22 #include <acpi/nfit.h> 23 #include <asm/mce.h> 24 #include <asm/uv/uv.h> 25 #include "edac_module.h" 26 #include "skx_common.h" 27 28 static const char * const component_names[] = { 29 [INDEX_SOCKET] = "ProcessorSocketId", 30 [INDEX_MEMCTRL] = "MemoryControllerId", 31 [INDEX_CHANNEL] = "ChannelId", 32 [INDEX_DIMM] = "DimmSlotId", 33 [INDEX_CS] = "ChipSelect", 34 [INDEX_NM_MEMCTRL] = "NmMemoryControllerId", 35 [INDEX_NM_CHANNEL] = "NmChannelId", 36 [INDEX_NM_DIMM] = "NmDimmSlotId", 37 [INDEX_NM_CS] = "NmChipSelect", 38 }; 39 40 static int component_indices[ARRAY_SIZE(component_names)]; 41 static int adxl_component_count; 42 static const char * const *adxl_component_names; 43 static u64 *adxl_values; 44 static char *adxl_msg; 45 static unsigned long adxl_nm_bitmap; 46 47 static char skx_msg[MSG_SIZE]; 48 static skx_decode_f driver_decode; 49 static skx_show_retry_log_f skx_show_retry_rd_err_log; 50 static u64 skx_tolm, skx_tohm; 51 static LIST_HEAD(dev_edac_list); 52 static bool skx_mem_cfg_2lm; 53 static struct res_config *skx_res_cfg; 54 55 int skx_adxl_get(void) 56 { 57 const char * const *names; 58 int i, j; 59 60 names = adxl_get_component_names(); 61 if (!names) { 62 skx_printk(KERN_NOTICE, "No firmware support for address translation.\n"); 63 return -ENODEV; 64 } 65 66 for (i = 0; i < INDEX_MAX; i++) { 67 for (j = 0; names[j]; j++) { 68 if (!strcmp(component_names[i], names[j])) { 69 component_indices[i] = j; 70 71 if (i >= INDEX_NM_FIRST) 72 adxl_nm_bitmap |= 1 << i; 73 74 break; 75 } 76 } 77 78 if (!names[j] && i < INDEX_NM_FIRST) 79 goto err; 80 } 81 82 if (skx_mem_cfg_2lm) { 83 if (!adxl_nm_bitmap) 84 skx_printk(KERN_NOTICE, "Not enough ADXL components for 2-level memory.\n"); 85 else 86 edac_dbg(2, "adxl_nm_bitmap: 0x%lx\n", adxl_nm_bitmap); 87 } 88 89 adxl_component_names = names; 90 while (*names++) 91 adxl_component_count++; 92 93 adxl_values = kcalloc(adxl_component_count, sizeof(*adxl_values), 94 GFP_KERNEL); 95 if (!adxl_values) { 96 adxl_component_count = 0; 97 return -ENOMEM; 98 } 99 100 adxl_msg = kzalloc(MSG_SIZE, GFP_KERNEL); 101 if (!adxl_msg) { 102 adxl_component_count = 0; 103 kfree(adxl_values); 104 return -ENOMEM; 105 } 106 107 return 0; 108 err: 109 skx_printk(KERN_ERR, "'%s' is not matched from DSM parameters: ", 110 component_names[i]); 111 for (j = 0; names[j]; j++) 112 skx_printk(KERN_CONT, "%s ", names[j]); 113 skx_printk(KERN_CONT, "\n"); 114 115 return -ENODEV; 116 } 117 EXPORT_SYMBOL_GPL(skx_adxl_get); 118 119 void skx_adxl_put(void) 120 { 121 adxl_component_count = 0; 122 kfree(adxl_values); 123 kfree(adxl_msg); 124 } 125 EXPORT_SYMBOL_GPL(skx_adxl_put); 126 127 static void skx_init_mc_mapping(struct skx_dev *d) 128 { 129 /* 130 * By default, the BIOS presents all memory controllers within each 131 * socket to the EDAC driver. The physical indices are the same as 132 * the logical indices of the memory controllers enumerated by the 133 * EDAC driver. 134 */ 135 for (int i = 0; i < d->num_imc; i++) 136 d->imc[i].mc_mapping = i; 137 } 138 139 void skx_set_mc_mapping(struct skx_dev *d, u8 pmc, u8 lmc) 140 { 141 edac_dbg(0, "Set the mapping of mc phy idx to logical idx: %02d -> %02d\n", 142 pmc, lmc); 143 144 d->imc[lmc].mc_mapping = pmc; 145 } 146 EXPORT_SYMBOL_GPL(skx_set_mc_mapping); 147 148 static int skx_get_mc_mapping(struct skx_dev *d, u8 pmc) 149 { 150 for (int lmc = 0; lmc < d->num_imc; lmc++) { 151 if (d->imc[lmc].mc_mapping == pmc) { 152 edac_dbg(0, "Get the mapping of mc phy idx to logical idx: %02d -> %02d\n", 153 pmc, lmc); 154 155 return lmc; 156 } 157 } 158 159 return -1; 160 } 161 162 static bool skx_adxl_decode(struct decoded_addr *res, enum error_source err_src) 163 { 164 int i, lmc, len = 0; 165 struct skx_dev *d; 166 167 if (res->addr >= skx_tohm || (res->addr >= skx_tolm && 168 res->addr < BIT_ULL(32))) { 169 edac_dbg(0, "Address 0x%llx out of range\n", res->addr); 170 return false; 171 } 172 173 if (adxl_decode(res->addr, adxl_values)) { 174 edac_dbg(0, "Failed to decode 0x%llx\n", res->addr); 175 return false; 176 } 177 178 /* 179 * GNR with a Flat2LM memory configuration may mistakenly classify 180 * a near-memory error(DDR5) as a far-memory error(CXL), resulting 181 * in the incorrect selection of decoded ADXL components. 182 * To address this, prefetch the decoded far-memory controller ID 183 * and adjust the error source to near-memory if the far-memory 184 * controller ID is invalid. 185 */ 186 if (skx_res_cfg && skx_res_cfg->type == GNR && err_src == ERR_SRC_2LM_FM) { 187 res->imc = (int)adxl_values[component_indices[INDEX_MEMCTRL]]; 188 if (res->imc == -1) { 189 err_src = ERR_SRC_2LM_NM; 190 edac_dbg(0, "Adjust the error source to near-memory.\n"); 191 } 192 } 193 194 res->socket = (int)adxl_values[component_indices[INDEX_SOCKET]]; 195 if (err_src == ERR_SRC_2LM_NM) { 196 res->imc = (adxl_nm_bitmap & BIT_NM_MEMCTRL) ? 197 (int)adxl_values[component_indices[INDEX_NM_MEMCTRL]] : -1; 198 res->channel = (adxl_nm_bitmap & BIT_NM_CHANNEL) ? 199 (int)adxl_values[component_indices[INDEX_NM_CHANNEL]] : -1; 200 res->dimm = (adxl_nm_bitmap & BIT_NM_DIMM) ? 201 (int)adxl_values[component_indices[INDEX_NM_DIMM]] : -1; 202 res->cs = (adxl_nm_bitmap & BIT_NM_CS) ? 203 (int)adxl_values[component_indices[INDEX_NM_CS]] : -1; 204 } else { 205 res->imc = (int)adxl_values[component_indices[INDEX_MEMCTRL]]; 206 res->channel = (int)adxl_values[component_indices[INDEX_CHANNEL]]; 207 res->dimm = (int)adxl_values[component_indices[INDEX_DIMM]]; 208 res->cs = (int)adxl_values[component_indices[INDEX_CS]]; 209 } 210 211 if (res->imc < 0) { 212 skx_printk(KERN_ERR, "Bad imc %d\n", res->imc); 213 return false; 214 } 215 216 list_for_each_entry(d, &dev_edac_list, list) { 217 if (d->imc[0].src_id == res->socket) { 218 res->dev = d; 219 break; 220 } 221 } 222 223 if (!res->dev) { 224 skx_printk(KERN_ERR, "No device for src_id %d imc %d\n", 225 res->socket, res->imc); 226 return false; 227 } 228 229 lmc = skx_get_mc_mapping(d, res->imc); 230 if (lmc < 0) { 231 skx_printk(KERN_ERR, "No lmc for imc %d\n", res->imc); 232 return false; 233 } 234 235 res->imc = lmc; 236 237 for (i = 0; i < adxl_component_count; i++) { 238 if (adxl_values[i] == ~0x0ull) 239 continue; 240 241 len += snprintf(adxl_msg + len, MSG_SIZE - len, " %s:0x%llx", 242 adxl_component_names[i], adxl_values[i]); 243 if (MSG_SIZE - len <= 0) 244 break; 245 } 246 247 res->decoded_by_adxl = true; 248 249 return true; 250 } 251 252 void skx_set_mem_cfg(bool mem_cfg_2lm) 253 { 254 skx_mem_cfg_2lm = mem_cfg_2lm; 255 } 256 EXPORT_SYMBOL_GPL(skx_set_mem_cfg); 257 258 void skx_set_res_cfg(struct res_config *cfg) 259 { 260 skx_res_cfg = cfg; 261 } 262 EXPORT_SYMBOL_GPL(skx_set_res_cfg); 263 264 void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log) 265 { 266 driver_decode = decode; 267 skx_show_retry_rd_err_log = show_retry_log; 268 } 269 EXPORT_SYMBOL_GPL(skx_set_decode); 270 271 static int skx_get_pkg_id(struct skx_dev *d, u8 *id) 272 { 273 int node; 274 int cpu; 275 276 node = pcibus_to_node(d->util_all->bus); 277 if (numa_valid_node(node)) { 278 for_each_cpu(cpu, cpumask_of_pcibus(d->util_all->bus)) { 279 struct cpuinfo_x86 *c = &cpu_data(cpu); 280 281 if (c->initialized && cpu_to_node(cpu) == node) { 282 *id = topology_physical_package_id(cpu); 283 return 0; 284 } 285 } 286 } 287 288 skx_printk(KERN_ERR, "Failed to get package ID from NUMA information\n"); 289 return -ENODEV; 290 } 291 292 int skx_get_src_id(struct skx_dev *d, int off, u8 *id) 293 { 294 u32 reg; 295 296 /* 297 * The 3-bit source IDs in PCI configuration space registers are limited 298 * to 8 unique IDs, and each ID is local to a UPI/QPI domain. 299 * 300 * Source IDs cannot be used to map devices to sockets on UV systems 301 * because they can exceed 8 sockets and have multiple UPI/QPI domains 302 * with identical, repeating source IDs. 303 */ 304 if (is_uv_system()) 305 return skx_get_pkg_id(d, id); 306 307 if (pci_read_config_dword(d->util_all, off, ®)) { 308 skx_printk(KERN_ERR, "Failed to read src id\n"); 309 return -ENODEV; 310 } 311 312 *id = GET_BITFIELD(reg, 12, 14); 313 return 0; 314 } 315 EXPORT_SYMBOL_GPL(skx_get_src_id); 316 317 static int get_width(u32 mtr) 318 { 319 switch (GET_BITFIELD(mtr, 8, 9)) { 320 case 0: 321 return DEV_X4; 322 case 1: 323 return DEV_X8; 324 case 2: 325 return DEV_X16; 326 } 327 return DEV_UNKNOWN; 328 } 329 330 /* 331 * We use the per-socket device @cfg->did to count how many sockets are present, 332 * and to detemine which PCI buses are associated with each socket. Allocate 333 * and build the full list of all the skx_dev structures that we need here. 334 */ 335 int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list) 336 { 337 int ndev = 0, imc_num = cfg->ddr_imc_num + cfg->hbm_imc_num; 338 struct pci_dev *pdev, *prev; 339 struct skx_dev *d; 340 u32 reg; 341 342 prev = NULL; 343 for (;;) { 344 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, cfg->decs_did, prev); 345 if (!pdev) 346 break; 347 ndev++; 348 d = kzalloc(struct_size(d, imc, imc_num), GFP_KERNEL); 349 if (!d) { 350 pci_dev_put(pdev); 351 return -ENOMEM; 352 } 353 354 if (pci_read_config_dword(pdev, cfg->busno_cfg_offset, ®)) { 355 kfree(d); 356 pci_dev_put(pdev); 357 skx_printk(KERN_ERR, "Failed to read bus idx\n"); 358 return -ENODEV; 359 } 360 361 d->bus[0] = GET_BITFIELD(reg, 0, 7); 362 d->bus[1] = GET_BITFIELD(reg, 8, 15); 363 if (cfg->type == SKX) { 364 d->seg = pci_domain_nr(pdev->bus); 365 d->bus[2] = GET_BITFIELD(reg, 16, 23); 366 d->bus[3] = GET_BITFIELD(reg, 24, 31); 367 } else { 368 d->seg = GET_BITFIELD(reg, 16, 23); 369 } 370 371 d->num_imc = imc_num; 372 373 edac_dbg(2, "busses: 0x%x, 0x%x, 0x%x, 0x%x, imcs %d\n", 374 d->bus[0], d->bus[1], d->bus[2], d->bus[3], imc_num); 375 list_add_tail(&d->list, &dev_edac_list); 376 prev = pdev; 377 378 skx_init_mc_mapping(d); 379 } 380 381 if (list) 382 *list = &dev_edac_list; 383 return ndev; 384 } 385 EXPORT_SYMBOL_GPL(skx_get_all_bus_mappings); 386 387 int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm) 388 { 389 struct pci_dev *pdev; 390 u32 reg; 391 392 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, did, NULL); 393 if (!pdev) { 394 edac_dbg(2, "Can't get tolm/tohm\n"); 395 return -ENODEV; 396 } 397 398 if (pci_read_config_dword(pdev, off[0], ®)) { 399 skx_printk(KERN_ERR, "Failed to read tolm\n"); 400 goto fail; 401 } 402 skx_tolm = reg; 403 404 if (pci_read_config_dword(pdev, off[1], ®)) { 405 skx_printk(KERN_ERR, "Failed to read lower tohm\n"); 406 goto fail; 407 } 408 skx_tohm = reg; 409 410 if (pci_read_config_dword(pdev, off[2], ®)) { 411 skx_printk(KERN_ERR, "Failed to read upper tohm\n"); 412 goto fail; 413 } 414 skx_tohm |= (u64)reg << 32; 415 416 pci_dev_put(pdev); 417 *tolm = skx_tolm; 418 *tohm = skx_tohm; 419 edac_dbg(2, "tolm = 0x%llx tohm = 0x%llx\n", skx_tolm, skx_tohm); 420 return 0; 421 fail: 422 pci_dev_put(pdev); 423 return -ENODEV; 424 } 425 EXPORT_SYMBOL_GPL(skx_get_hi_lo); 426 427 static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add, 428 int minval, int maxval, const char *name) 429 { 430 u32 val = GET_BITFIELD(reg, lobit, hibit); 431 432 if (val < minval || val > maxval) { 433 edac_dbg(2, "bad %s = %d (raw=0x%x)\n", name, val, reg); 434 return -EINVAL; 435 } 436 return val + add; 437 } 438 439 #define numrank(reg) skx_get_dimm_attr(reg, 12, 13, 0, 0, 2, "ranks") 440 #define numrow(reg) skx_get_dimm_attr(reg, 2, 4, 12, 1, 6, "rows") 441 #define numcol(reg) skx_get_dimm_attr(reg, 0, 1, 10, 0, 2, "cols") 442 443 int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm, 444 struct skx_imc *imc, int chan, int dimmno, 445 struct res_config *cfg) 446 { 447 int banks, ranks, rows, cols, npages; 448 enum mem_type mtype; 449 u64 size; 450 451 ranks = numrank(mtr); 452 rows = numrow(mtr); 453 cols = imc->hbm_mc ? 6 : numcol(mtr); 454 455 if (imc->hbm_mc) { 456 banks = 32; 457 mtype = MEM_HBM2; 458 } else if (cfg->support_ddr5) { 459 banks = 32; 460 mtype = MEM_DDR5; 461 } else { 462 banks = 16; 463 mtype = MEM_DDR4; 464 } 465 466 /* 467 * Compute size in 8-byte (2^3) words, then shift to MiB (2^20) 468 */ 469 size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3); 470 npages = MiB_TO_PAGES(size); 471 472 edac_dbg(0, "mc#%d: channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: 0x%x, col: 0x%x\n", 473 imc->mc, chan, dimmno, size, npages, 474 banks, 1 << ranks, rows, cols); 475 476 imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mcmtr, 0, 0); 477 imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mcmtr, 9, 9); 478 imc->chan[chan].dimms[dimmno].fine_grain_bank = GET_BITFIELD(amap, 0, 0); 479 imc->chan[chan].dimms[dimmno].rowbits = rows; 480 imc->chan[chan].dimms[dimmno].colbits = cols; 481 482 dimm->nr_pages = npages; 483 dimm->grain = 32; 484 dimm->dtype = get_width(mtr); 485 dimm->mtype = mtype; 486 dimm->edac_mode = EDAC_SECDED; /* likely better than this */ 487 488 if (imc->hbm_mc) 489 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_HBMC#%u_Chan#%u", 490 imc->src_id, imc->lmc, chan); 491 else 492 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u", 493 imc->src_id, imc->lmc, chan, dimmno); 494 495 return 1; 496 } 497 EXPORT_SYMBOL_GPL(skx_get_dimm_info); 498 499 int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc, 500 int chan, int dimmno, const char *mod_str) 501 { 502 int smbios_handle; 503 u32 dev_handle; 504 u16 flags; 505 u64 size = 0; 506 507 dev_handle = ACPI_NFIT_BUILD_DEVICE_HANDLE(dimmno, chan, imc->lmc, 508 imc->src_id, 0); 509 510 smbios_handle = nfit_get_smbios_id(dev_handle, &flags); 511 if (smbios_handle == -EOPNOTSUPP) { 512 pr_warn_once("%s: Can't find size of NVDIMM. Try enabling CONFIG_ACPI_NFIT\n", mod_str); 513 goto unknown_size; 514 } 515 516 if (smbios_handle < 0) { 517 skx_printk(KERN_ERR, "Can't find handle for NVDIMM ADR=0x%x\n", dev_handle); 518 goto unknown_size; 519 } 520 521 if (flags & ACPI_NFIT_MEM_MAP_FAILED) { 522 skx_printk(KERN_ERR, "NVDIMM ADR=0x%x is not mapped\n", dev_handle); 523 goto unknown_size; 524 } 525 526 size = dmi_memdev_size(smbios_handle); 527 if (size == ~0ull) 528 skx_printk(KERN_ERR, "Can't find size for NVDIMM ADR=0x%x/SMBIOS=0x%x\n", 529 dev_handle, smbios_handle); 530 531 unknown_size: 532 dimm->nr_pages = size >> PAGE_SHIFT; 533 dimm->grain = 32; 534 dimm->dtype = DEV_UNKNOWN; 535 dimm->mtype = MEM_NVDIMM; 536 dimm->edac_mode = EDAC_SECDED; /* likely better than this */ 537 538 edac_dbg(0, "mc#%d: channel %d, dimm %d, %llu MiB (%u pages)\n", 539 imc->mc, chan, dimmno, size >> 20, dimm->nr_pages); 540 541 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u", 542 imc->src_id, imc->lmc, chan, dimmno); 543 544 return (size == 0 || size == ~0ull) ? 0 : 1; 545 } 546 EXPORT_SYMBOL_GPL(skx_get_nvdimm_info); 547 548 int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev, 549 const char *ctl_name, const char *mod_str, 550 get_dimm_config_f get_dimm_config, 551 struct res_config *cfg) 552 { 553 struct mem_ctl_info *mci; 554 struct edac_mc_layer layers[2]; 555 struct skx_pvt *pvt; 556 int rc; 557 558 /* Allocate a new MC control structure */ 559 layers[0].type = EDAC_MC_LAYER_CHANNEL; 560 layers[0].size = imc->num_channels; 561 layers[0].is_virt_csrow = false; 562 layers[1].type = EDAC_MC_LAYER_SLOT; 563 layers[1].size = imc->num_dimms; 564 layers[1].is_virt_csrow = true; 565 mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers, 566 sizeof(struct skx_pvt)); 567 568 if (unlikely(!mci)) 569 return -ENOMEM; 570 571 edac_dbg(0, "MC#%d: mci = %p\n", imc->mc, mci); 572 573 /* Associate skx_dev and mci for future usage */ 574 imc->mci = mci; 575 pvt = mci->pvt_info; 576 pvt->imc = imc; 577 578 mci->ctl_name = kasprintf(GFP_KERNEL, "%s#%d IMC#%d", ctl_name, 579 imc->src_id, imc->lmc); 580 if (!mci->ctl_name) { 581 rc = -ENOMEM; 582 goto fail0; 583 } 584 585 mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_NVDIMM; 586 if (cfg->support_ddr5) 587 mci->mtype_cap |= MEM_FLAG_DDR5; 588 mci->edac_ctl_cap = EDAC_FLAG_NONE; 589 mci->edac_cap = EDAC_FLAG_NONE; 590 mci->mod_name = mod_str; 591 mci->dev_name = pci_name(pdev); 592 mci->ctl_page_to_phys = NULL; 593 594 rc = get_dimm_config(mci, cfg); 595 if (rc < 0) 596 goto fail; 597 598 /* Record ptr to the generic device */ 599 mci->pdev = &pdev->dev; 600 601 /* Add this new MC control structure to EDAC's list of MCs */ 602 if (unlikely(edac_mc_add_mc(mci))) { 603 edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); 604 rc = -EINVAL; 605 goto fail; 606 } 607 608 return 0; 609 610 fail: 611 kfree(mci->ctl_name); 612 fail0: 613 edac_mc_free(mci); 614 imc->mci = NULL; 615 return rc; 616 } 617 EXPORT_SYMBOL_GPL(skx_register_mci); 618 619 static void skx_unregister_mci(struct skx_imc *imc) 620 { 621 struct mem_ctl_info *mci = imc->mci; 622 623 if (!mci) 624 return; 625 626 edac_dbg(0, "MC%d: mci = %p\n", imc->mc, mci); 627 628 /* Remove MC sysfs nodes */ 629 edac_mc_del_mc(mci->pdev); 630 631 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); 632 kfree(mci->ctl_name); 633 edac_mc_free(mci); 634 } 635 636 static void skx_mce_output_error(struct mem_ctl_info *mci, 637 const struct mce *m, 638 struct decoded_addr *res) 639 { 640 enum hw_event_mc_err_type tp_event; 641 char *optype; 642 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); 643 bool overflow = GET_BITFIELD(m->status, 62, 62); 644 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); 645 bool scrub_err = false; 646 bool recoverable; 647 int len; 648 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); 649 u32 mscod = GET_BITFIELD(m->status, 16, 31); 650 u32 errcode = GET_BITFIELD(m->status, 0, 15); 651 u32 optypenum = GET_BITFIELD(m->status, 4, 6); 652 653 recoverable = GET_BITFIELD(m->status, 56, 56); 654 655 if (uncorrected_error) { 656 core_err_cnt = 1; 657 if (ripv) { 658 tp_event = HW_EVENT_ERR_UNCORRECTED; 659 } else { 660 tp_event = HW_EVENT_ERR_FATAL; 661 } 662 } else { 663 tp_event = HW_EVENT_ERR_CORRECTED; 664 } 665 666 switch (optypenum) { 667 case 0: 668 optype = "generic undef request error"; 669 break; 670 case 1: 671 optype = "memory read error"; 672 break; 673 case 2: 674 optype = "memory write error"; 675 break; 676 case 3: 677 optype = "addr/cmd error"; 678 break; 679 case 4: 680 optype = "memory scrubbing error"; 681 scrub_err = true; 682 break; 683 default: 684 optype = "reserved"; 685 break; 686 } 687 688 if (res->decoded_by_adxl) { 689 len = scnprintf(skx_msg, MSG_SIZE, "%s%s err_code:0x%04x:0x%04x %s", 690 overflow ? " OVERFLOW" : "", 691 (uncorrected_error && recoverable) ? " recoverable" : "", 692 mscod, errcode, adxl_msg); 693 } else { 694 len = scnprintf(skx_msg, MSG_SIZE, 695 "%s%s err_code:0x%04x:0x%04x ProcessorSocketId:0x%x MemoryControllerId:0x%x PhysicalRankId:0x%x Row:0x%x Column:0x%x Bank:0x%x BankGroup:0x%x", 696 overflow ? " OVERFLOW" : "", 697 (uncorrected_error && recoverable) ? " recoverable" : "", 698 mscod, errcode, 699 res->socket, res->imc, res->rank, 700 res->row, res->column, res->bank_address, res->bank_group); 701 } 702 703 if (skx_show_retry_rd_err_log) 704 skx_show_retry_rd_err_log(res, skx_msg + len, MSG_SIZE - len, scrub_err); 705 706 edac_dbg(0, "%s\n", skx_msg); 707 708 /* Call the helper to output message */ 709 edac_mc_handle_error(tp_event, mci, core_err_cnt, 710 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, 711 res->channel, res->dimm, -1, 712 optype, skx_msg); 713 } 714 715 static enum error_source skx_error_source(const struct mce *m) 716 { 717 u32 errcode = GET_BITFIELD(m->status, 0, 15) & MCACOD_MEM_ERR_MASK; 718 719 if (errcode != MCACOD_MEM_CTL_ERR && errcode != MCACOD_EXT_MEM_ERR) 720 return ERR_SRC_NOT_MEMORY; 721 722 if (!skx_mem_cfg_2lm) 723 return ERR_SRC_1LM; 724 725 if (errcode == MCACOD_EXT_MEM_ERR) 726 return ERR_SRC_2LM_NM; 727 728 return ERR_SRC_2LM_FM; 729 } 730 731 int skx_mce_check_error(struct notifier_block *nb, unsigned long val, 732 void *data) 733 { 734 struct mce *mce = (struct mce *)data; 735 enum error_source err_src; 736 struct decoded_addr res; 737 struct mem_ctl_info *mci; 738 char *type; 739 740 if (mce->kflags & MCE_HANDLED_CEC) 741 return NOTIFY_DONE; 742 743 err_src = skx_error_source(mce); 744 745 /* Ignore unless this is memory related with an address */ 746 if (err_src == ERR_SRC_NOT_MEMORY || !(mce->status & MCI_STATUS_ADDRV)) 747 return NOTIFY_DONE; 748 749 memset(&res, 0, sizeof(res)); 750 res.mce = mce; 751 res.addr = mce->addr & MCI_ADDR_PHYSADDR; 752 if (!pfn_to_online_page(res.addr >> PAGE_SHIFT) && !arch_is_platform_page(res.addr)) { 753 pr_err("Invalid address 0x%llx in IA32_MC%d_ADDR\n", mce->addr, mce->bank); 754 return NOTIFY_DONE; 755 } 756 757 /* Try driver decoder first */ 758 if (!(driver_decode && driver_decode(&res))) { 759 /* Then try firmware decoder (ACPI DSM methods) */ 760 if (!(adxl_component_count && skx_adxl_decode(&res, err_src))) 761 return NOTIFY_DONE; 762 } 763 764 mci = res.dev->imc[res.imc].mci; 765 766 if (!mci) 767 return NOTIFY_DONE; 768 769 if (mce->mcgstatus & MCG_STATUS_MCIP) 770 type = "Exception"; 771 else 772 type = "Event"; 773 774 skx_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n"); 775 776 skx_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: 0x%llx " 777 "Bank %d: 0x%llx\n", mce->extcpu, type, 778 mce->mcgstatus, mce->bank, mce->status); 779 skx_mc_printk(mci, KERN_DEBUG, "TSC 0x%llx ", mce->tsc); 780 skx_mc_printk(mci, KERN_DEBUG, "ADDR 0x%llx ", mce->addr); 781 skx_mc_printk(mci, KERN_DEBUG, "MISC 0x%llx ", mce->misc); 782 783 skx_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:0x%x TIME %llu SOCKET " 784 "%u APIC 0x%x\n", mce->cpuvendor, mce->cpuid, 785 mce->time, mce->socketid, mce->apicid); 786 787 skx_mce_output_error(mci, mce, &res); 788 789 mce->kflags |= MCE_HANDLED_EDAC; 790 return NOTIFY_DONE; 791 } 792 EXPORT_SYMBOL_GPL(skx_mce_check_error); 793 794 void skx_remove(void) 795 { 796 int i, j; 797 struct skx_dev *d, *tmp; 798 799 edac_dbg(0, "\n"); 800 801 list_for_each_entry_safe(d, tmp, &dev_edac_list, list) { 802 list_del(&d->list); 803 for (i = 0; i < d->num_imc; i++) { 804 if (d->imc[i].mci) 805 skx_unregister_mci(&d->imc[i]); 806 807 if (d->imc[i].mdev) 808 pci_dev_put(d->imc[i].mdev); 809 810 if (d->imc[i].mbase) 811 iounmap(d->imc[i].mbase); 812 813 for (j = 0; j < d->imc[i].num_channels; j++) { 814 if (d->imc[i].chan[j].cdev) 815 pci_dev_put(d->imc[i].chan[j].cdev); 816 } 817 } 818 if (d->util_all) 819 pci_dev_put(d->util_all); 820 if (d->pcu_cr3) 821 pci_dev_put(d->pcu_cr3); 822 if (d->sad_all) 823 pci_dev_put(d->sad_all); 824 if (d->uracu) 825 pci_dev_put(d->uracu); 826 827 kfree(d); 828 } 829 } 830 EXPORT_SYMBOL_GPL(skx_remove); 831 832 #ifdef CONFIG_EDAC_DEBUG 833 /* 834 * Debug feature. 835 * Exercise the address decode logic by writing an address to 836 * /sys/kernel/debug/edac/{skx,i10nm}_test/addr. 837 */ 838 static struct dentry *skx_test; 839 840 static int debugfs_u64_set(void *data, u64 val) 841 { 842 struct mce m; 843 844 pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val); 845 846 memset(&m, 0, sizeof(m)); 847 /* ADDRV + MemRd + Unknown channel */ 848 m.status = MCI_STATUS_ADDRV + 0x90; 849 /* One corrected error */ 850 m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT); 851 m.addr = val; 852 skx_mce_check_error(NULL, 0, &m); 853 854 return 0; 855 } 856 DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n"); 857 858 void skx_setup_debug(const char *name) 859 { 860 skx_test = edac_debugfs_create_dir(name); 861 if (!skx_test) 862 return; 863 864 if (!edac_debugfs_create_file("addr", 0200, skx_test, 865 NULL, &fops_u64_wo)) { 866 debugfs_remove(skx_test); 867 skx_test = NULL; 868 } 869 } 870 EXPORT_SYMBOL_GPL(skx_setup_debug); 871 872 void skx_teardown_debug(void) 873 { 874 debugfs_remove_recursive(skx_test); 875 } 876 EXPORT_SYMBOL_GPL(skx_teardown_debug); 877 #endif /*CONFIG_EDAC_DEBUG*/ 878 879 MODULE_LICENSE("GPL v2"); 880 MODULE_AUTHOR("Tony Luck"); 881 MODULE_DESCRIPTION("MC Driver for Intel server processors"); 882