1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * EDAC driver for Intel(R) Xeon(R) Skylake processors 4 * Copyright (c) 2016, Intel Corporation. 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/processor.h> 9 #include <asm/cpu_device_id.h> 10 #include <asm/intel-family.h> 11 #include <asm/mce.h> 12 13 #include "edac_module.h" 14 #include "skx_common.h" 15 16 #define EDAC_MOD_STR "skx_edac" 17 18 /* 19 * Debug macros 20 */ 21 #define skx_printk(level, fmt, arg...) \ 22 edac_printk(level, "skx", fmt, ##arg) 23 24 #define skx_mc_printk(mci, level, fmt, arg...) \ 25 edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg) 26 27 static struct list_head *skx_edac_list; 28 29 static u64 skx_tolm, skx_tohm; 30 static int skx_num_sockets; 31 static unsigned int nvdimm_count; 32 33 #define MASK26 0x3FFFFFF /* Mask for 2^26 */ 34 #define MASK29 0x1FFFFFFF /* Mask for 2^29 */ 35 36 static struct res_config skx_cfg = { 37 .type = SKX, 38 .decs_did = 0x2016, 39 .busno_cfg_offset = 0xcc, 40 .ddr_imc_num = 2, 41 .ddr_chan_num = 3, 42 .ddr_dimm_num = 2, 43 }; 44 45 static struct skx_dev *get_skx_dev(struct pci_bus *bus, u8 idx) 46 { 47 struct skx_dev *d; 48 49 list_for_each_entry(d, skx_edac_list, list) { 50 if (d->seg == pci_domain_nr(bus) && d->bus[idx] == bus->number) 51 return d; 52 } 53 54 return NULL; 55 } 56 57 enum munittype { 58 CHAN0, CHAN1, CHAN2, SAD_ALL, UTIL_ALL, SAD, 59 ERRCHAN0, ERRCHAN1, ERRCHAN2, 60 }; 61 62 struct munit { 63 u16 did; 64 u16 devfn[2]; 65 u8 busidx; 66 u8 per_socket; 67 enum munittype mtype; 68 }; 69 70 /* 71 * List of PCI device ids that we need together with some device 72 * number and function numbers to tell which memory controller the 73 * device belongs to. 74 */ 75 static const struct munit skx_all_munits[] = { 76 { 0x2054, { }, 1, 1, SAD_ALL }, 77 { 0x2055, { }, 1, 1, UTIL_ALL }, 78 { 0x2040, { PCI_DEVFN(10, 0), PCI_DEVFN(12, 0) }, 2, 2, CHAN0 }, 79 { 0x2044, { PCI_DEVFN(10, 4), PCI_DEVFN(12, 4) }, 2, 2, CHAN1 }, 80 { 0x2048, { PCI_DEVFN(11, 0), PCI_DEVFN(13, 0) }, 2, 2, CHAN2 }, 81 { 0x2043, { PCI_DEVFN(10, 3), PCI_DEVFN(12, 3) }, 2, 2, ERRCHAN0 }, 82 { 0x2047, { PCI_DEVFN(10, 7), PCI_DEVFN(12, 7) }, 2, 2, ERRCHAN1 }, 83 { 0x204b, { PCI_DEVFN(11, 3), PCI_DEVFN(13, 3) }, 2, 2, ERRCHAN2 }, 84 { 0x208e, { }, 1, 0, SAD }, 85 { } 86 }; 87 88 static int get_all_munits(const struct munit *m) 89 { 90 struct pci_dev *pdev, *prev; 91 struct skx_dev *d; 92 u32 reg; 93 int i = 0, ndev = 0; 94 95 prev = NULL; 96 for (;;) { 97 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, m->did, prev); 98 if (!pdev) 99 break; 100 ndev++; 101 if (m->per_socket == skx_cfg.ddr_imc_num) { 102 for (i = 0; i < skx_cfg.ddr_imc_num; i++) 103 if (m->devfn[i] == pdev->devfn) 104 break; 105 if (i == skx_cfg.ddr_imc_num) 106 goto fail; 107 } 108 d = get_skx_dev(pdev->bus, m->busidx); 109 if (!d) 110 goto fail; 111 112 /* Be sure that the device is enabled */ 113 if (unlikely(pci_enable_device(pdev) < 0)) { 114 skx_printk(KERN_ERR, "Couldn't enable device %04x:%04x\n", 115 PCI_VENDOR_ID_INTEL, m->did); 116 goto fail; 117 } 118 119 switch (m->mtype) { 120 case CHAN0: 121 case CHAN1: 122 case CHAN2: 123 pci_dev_get(pdev); 124 d->imc[i].chan[m->mtype].cdev = pdev; 125 break; 126 case ERRCHAN0: 127 case ERRCHAN1: 128 case ERRCHAN2: 129 pci_dev_get(pdev); 130 d->imc[i].chan[m->mtype - ERRCHAN0].edev = pdev; 131 break; 132 case SAD_ALL: 133 pci_dev_get(pdev); 134 d->sad_all = pdev; 135 break; 136 case UTIL_ALL: 137 pci_dev_get(pdev); 138 d->util_all = pdev; 139 break; 140 case SAD: 141 /* 142 * one of these devices per core, including cores 143 * that don't exist on this SKU. Ignore any that 144 * read a route table of zero, make sure all the 145 * non-zero values match. 146 */ 147 pci_read_config_dword(pdev, 0xB4, ®); 148 if (reg != 0) { 149 if (d->mcroute == 0) { 150 d->mcroute = reg; 151 } else if (d->mcroute != reg) { 152 skx_printk(KERN_ERR, "mcroute mismatch\n"); 153 goto fail; 154 } 155 } 156 ndev--; 157 break; 158 } 159 160 prev = pdev; 161 } 162 163 return ndev; 164 fail: 165 pci_dev_put(pdev); 166 return -ENODEV; 167 } 168 169 static const struct x86_cpu_id skx_cpuids[] = { 170 X86_MATCH_VFM(INTEL_SKYLAKE_X, &skx_cfg), 171 { } 172 }; 173 MODULE_DEVICE_TABLE(x86cpu, skx_cpuids); 174 175 static bool skx_check_ecc(u32 mcmtr) 176 { 177 return !!GET_BITFIELD(mcmtr, 2, 2); 178 } 179 180 static int skx_get_dimm_config(struct mem_ctl_info *mci, struct res_config *cfg) 181 { 182 struct skx_pvt *pvt = mci->pvt_info; 183 u32 mtr, mcmtr, amap, mcddrtcfg; 184 struct skx_imc *imc = pvt->imc; 185 struct dimm_info *dimm; 186 int i, j; 187 int ndimms; 188 189 /* Only the mcmtr on the first channel is effective */ 190 pci_read_config_dword(imc->chan[0].cdev, 0x87c, &mcmtr); 191 192 for (i = 0; i < cfg->ddr_chan_num; i++) { 193 ndimms = 0; 194 pci_read_config_dword(imc->chan[i].cdev, 0x8C, &amap); 195 pci_read_config_dword(imc->chan[i].cdev, 0x400, &mcddrtcfg); 196 for (j = 0; j < cfg->ddr_dimm_num; j++) { 197 dimm = edac_get_dimm(mci, i, j, 0); 198 pci_read_config_dword(imc->chan[i].cdev, 199 0x80 + 4 * j, &mtr); 200 if (IS_DIMM_PRESENT(mtr)) { 201 ndimms += skx_get_dimm_info(mtr, mcmtr, amap, dimm, imc, i, j, cfg); 202 } else if (IS_NVDIMM_PRESENT(mcddrtcfg, j)) { 203 ndimms += skx_get_nvdimm_info(dimm, imc, i, j, 204 EDAC_MOD_STR); 205 nvdimm_count++; 206 } 207 } 208 if (ndimms && !skx_check_ecc(mcmtr)) { 209 skx_printk(KERN_ERR, "ECC is disabled on imc %d\n", imc->mc); 210 return -ENODEV; 211 } 212 } 213 214 return 0; 215 } 216 217 #define SKX_MAX_SAD 24 218 219 #define SKX_GET_SAD(d, i, reg) \ 220 pci_read_config_dword((d)->sad_all, 0x60 + 8 * (i), &(reg)) 221 #define SKX_GET_ILV(d, i, reg) \ 222 pci_read_config_dword((d)->sad_all, 0x64 + 8 * (i), &(reg)) 223 224 #define SKX_SAD_MOD3MODE(sad) GET_BITFIELD((sad), 30, 31) 225 #define SKX_SAD_MOD3(sad) GET_BITFIELD((sad), 27, 27) 226 #define SKX_SAD_LIMIT(sad) (((u64)GET_BITFIELD((sad), 7, 26) << 26) | MASK26) 227 #define SKX_SAD_MOD3ASMOD2(sad) GET_BITFIELD((sad), 5, 6) 228 #define SKX_SAD_ATTR(sad) GET_BITFIELD((sad), 3, 4) 229 #define SKX_SAD_INTERLEAVE(sad) GET_BITFIELD((sad), 1, 2) 230 #define SKX_SAD_ENABLE(sad) GET_BITFIELD((sad), 0, 0) 231 232 #define SKX_ILV_REMOTE(tgt) (((tgt) & 8) == 0) 233 #define SKX_ILV_TARGET(tgt) ((tgt) & 7) 234 235 static void skx_show_retry_rd_err_log(struct decoded_addr *res, 236 char *msg, int len, 237 bool scrub_err) 238 { 239 u32 log0, log1, log2, log3, log4; 240 u32 corr0, corr1, corr2, corr3; 241 struct pci_dev *edev; 242 int n; 243 244 edev = res->dev->imc[res->imc].chan[res->channel].edev; 245 246 pci_read_config_dword(edev, 0x154, &log0); 247 pci_read_config_dword(edev, 0x148, &log1); 248 pci_read_config_dword(edev, 0x150, &log2); 249 pci_read_config_dword(edev, 0x15c, &log3); 250 pci_read_config_dword(edev, 0x114, &log4); 251 252 n = snprintf(msg, len, " retry_rd_err_log[%.8x %.8x %.8x %.8x %.8x]", 253 log0, log1, log2, log3, log4); 254 255 pci_read_config_dword(edev, 0x104, &corr0); 256 pci_read_config_dword(edev, 0x108, &corr1); 257 pci_read_config_dword(edev, 0x10c, &corr2); 258 pci_read_config_dword(edev, 0x110, &corr3); 259 260 if (len - n > 0) 261 snprintf(msg + n, len - n, 262 " correrrcnt[%.4x %.4x %.4x %.4x %.4x %.4x %.4x %.4x]", 263 corr0 & 0xffff, corr0 >> 16, 264 corr1 & 0xffff, corr1 >> 16, 265 corr2 & 0xffff, corr2 >> 16, 266 corr3 & 0xffff, corr3 >> 16); 267 } 268 269 static bool skx_sad_decode(struct decoded_addr *res) 270 { 271 struct skx_dev *d = list_first_entry(skx_edac_list, typeof(*d), list); 272 u64 addr = res->addr; 273 int i, idx, tgt, lchan, shift; 274 u32 sad, ilv; 275 u64 limit, prev_limit; 276 int remote = 0; 277 278 /* Simple sanity check for I/O space or out of range */ 279 if (addr >= skx_tohm || (addr >= skx_tolm && addr < BIT_ULL(32))) { 280 edac_dbg(0, "Address 0x%llx out of range\n", addr); 281 return false; 282 } 283 284 restart: 285 prev_limit = 0; 286 for (i = 0; i < SKX_MAX_SAD; i++) { 287 SKX_GET_SAD(d, i, sad); 288 limit = SKX_SAD_LIMIT(sad); 289 if (SKX_SAD_ENABLE(sad)) { 290 if (addr >= prev_limit && addr <= limit) 291 goto sad_found; 292 } 293 prev_limit = limit + 1; 294 } 295 edac_dbg(0, "No SAD entry for 0x%llx\n", addr); 296 return false; 297 298 sad_found: 299 SKX_GET_ILV(d, i, ilv); 300 301 switch (SKX_SAD_INTERLEAVE(sad)) { 302 case 0: 303 idx = GET_BITFIELD(addr, 6, 8); 304 break; 305 case 1: 306 idx = GET_BITFIELD(addr, 8, 10); 307 break; 308 case 2: 309 idx = GET_BITFIELD(addr, 12, 14); 310 break; 311 case 3: 312 idx = GET_BITFIELD(addr, 30, 32); 313 break; 314 } 315 316 tgt = GET_BITFIELD(ilv, 4 * idx, 4 * idx + 3); 317 318 /* If point to another node, find it and start over */ 319 if (SKX_ILV_REMOTE(tgt)) { 320 if (remote) { 321 edac_dbg(0, "Double remote!\n"); 322 return false; 323 } 324 remote = 1; 325 list_for_each_entry(d, skx_edac_list, list) { 326 if (d->imc[0].src_id == SKX_ILV_TARGET(tgt)) 327 goto restart; 328 } 329 edac_dbg(0, "Can't find node %d\n", SKX_ILV_TARGET(tgt)); 330 return false; 331 } 332 333 if (SKX_SAD_MOD3(sad) == 0) { 334 lchan = SKX_ILV_TARGET(tgt); 335 } else { 336 switch (SKX_SAD_MOD3MODE(sad)) { 337 case 0: 338 shift = 6; 339 break; 340 case 1: 341 shift = 8; 342 break; 343 case 2: 344 shift = 12; 345 break; 346 default: 347 edac_dbg(0, "illegal mod3mode\n"); 348 return false; 349 } 350 switch (SKX_SAD_MOD3ASMOD2(sad)) { 351 case 0: 352 lchan = (addr >> shift) % 3; 353 break; 354 case 1: 355 lchan = (addr >> shift) % 2; 356 break; 357 case 2: 358 lchan = (addr >> shift) % 2; 359 lchan = (lchan << 1) | !lchan; 360 break; 361 case 3: 362 lchan = ((addr >> shift) % 2) << 1; 363 break; 364 } 365 lchan = (lchan << 1) | (SKX_ILV_TARGET(tgt) & 1); 366 } 367 368 res->dev = d; 369 res->socket = d->imc[0].src_id; 370 res->imc = GET_BITFIELD(d->mcroute, lchan * 3, lchan * 3 + 2); 371 res->channel = GET_BITFIELD(d->mcroute, lchan * 2 + 18, lchan * 2 + 19); 372 373 edac_dbg(2, "0x%llx: socket=%d imc=%d channel=%d\n", 374 res->addr, res->socket, res->imc, res->channel); 375 return true; 376 } 377 378 #define SKX_MAX_TAD 8 379 380 #define SKX_GET_TADBASE(d, mc, i, reg) \ 381 pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x850 + 4 * (i), &(reg)) 382 #define SKX_GET_TADWAYNESS(d, mc, i, reg) \ 383 pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x880 + 4 * (i), &(reg)) 384 #define SKX_GET_TADCHNILVOFFSET(d, mc, ch, i, reg) \ 385 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, 0x90 + 4 * (i), &(reg)) 386 387 #define SKX_TAD_BASE(b) ((u64)GET_BITFIELD((b), 12, 31) << 26) 388 #define SKX_TAD_SKT_GRAN(b) GET_BITFIELD((b), 4, 5) 389 #define SKX_TAD_CHN_GRAN(b) GET_BITFIELD((b), 6, 7) 390 #define SKX_TAD_LIMIT(b) (((u64)GET_BITFIELD((b), 12, 31) << 26) | MASK26) 391 #define SKX_TAD_OFFSET(b) ((u64)GET_BITFIELD((b), 4, 23) << 26) 392 #define SKX_TAD_SKTWAYS(b) (1 << GET_BITFIELD((b), 10, 11)) 393 #define SKX_TAD_CHNWAYS(b) (GET_BITFIELD((b), 8, 9) + 1) 394 395 /* which bit used for both socket and channel interleave */ 396 static int skx_granularity[] = { 6, 8, 12, 30 }; 397 398 static u64 skx_do_interleave(u64 addr, int shift, int ways, u64 lowbits) 399 { 400 addr >>= shift; 401 addr /= ways; 402 addr <<= shift; 403 404 return addr | (lowbits & ((1ull << shift) - 1)); 405 } 406 407 static bool skx_tad_decode(struct decoded_addr *res) 408 { 409 int i; 410 u32 base, wayness, chnilvoffset; 411 int skt_interleave_bit, chn_interleave_bit; 412 u64 channel_addr; 413 414 for (i = 0; i < SKX_MAX_TAD; i++) { 415 SKX_GET_TADBASE(res->dev, res->imc, i, base); 416 SKX_GET_TADWAYNESS(res->dev, res->imc, i, wayness); 417 if (SKX_TAD_BASE(base) <= res->addr && res->addr <= SKX_TAD_LIMIT(wayness)) 418 goto tad_found; 419 } 420 edac_dbg(0, "No TAD entry for 0x%llx\n", res->addr); 421 return false; 422 423 tad_found: 424 res->sktways = SKX_TAD_SKTWAYS(wayness); 425 res->chanways = SKX_TAD_CHNWAYS(wayness); 426 skt_interleave_bit = skx_granularity[SKX_TAD_SKT_GRAN(base)]; 427 chn_interleave_bit = skx_granularity[SKX_TAD_CHN_GRAN(base)]; 428 429 SKX_GET_TADCHNILVOFFSET(res->dev, res->imc, res->channel, i, chnilvoffset); 430 channel_addr = res->addr - SKX_TAD_OFFSET(chnilvoffset); 431 432 if (res->chanways == 3 && skt_interleave_bit > chn_interleave_bit) { 433 /* Must handle channel first, then socket */ 434 channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit, 435 res->chanways, channel_addr); 436 channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit, 437 res->sktways, channel_addr); 438 } else { 439 /* Handle socket then channel. Preserve low bits from original address */ 440 channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit, 441 res->sktways, res->addr); 442 channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit, 443 res->chanways, res->addr); 444 } 445 446 res->chan_addr = channel_addr; 447 448 edac_dbg(2, "0x%llx: chan_addr=0x%llx sktways=%d chanways=%d\n", 449 res->addr, res->chan_addr, res->sktways, res->chanways); 450 return true; 451 } 452 453 #define SKX_MAX_RIR 4 454 455 #define SKX_GET_RIRWAYNESS(d, mc, ch, i, reg) \ 456 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \ 457 0x108 + 4 * (i), &(reg)) 458 #define SKX_GET_RIRILV(d, mc, ch, idx, i, reg) \ 459 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \ 460 0x120 + 16 * (idx) + 4 * (i), &(reg)) 461 462 #define SKX_RIR_VALID(b) GET_BITFIELD((b), 31, 31) 463 #define SKX_RIR_LIMIT(b) (((u64)GET_BITFIELD((b), 1, 11) << 29) | MASK29) 464 #define SKX_RIR_WAYS(b) (1 << GET_BITFIELD((b), 28, 29)) 465 #define SKX_RIR_CHAN_RANK(b) GET_BITFIELD((b), 16, 19) 466 #define SKX_RIR_OFFSET(b) ((u64)(GET_BITFIELD((b), 2, 15) << 26)) 467 468 static bool skx_rir_decode(struct decoded_addr *res) 469 { 470 int i, idx, chan_rank; 471 int shift; 472 u32 rirway, rirlv; 473 u64 rank_addr, prev_limit = 0, limit; 474 475 if (res->dev->imc[res->imc].chan[res->channel].dimms[0].close_pg) 476 shift = 6; 477 else 478 shift = 13; 479 480 for (i = 0; i < SKX_MAX_RIR; i++) { 481 SKX_GET_RIRWAYNESS(res->dev, res->imc, res->channel, i, rirway); 482 limit = SKX_RIR_LIMIT(rirway); 483 if (SKX_RIR_VALID(rirway)) { 484 if (prev_limit <= res->chan_addr && 485 res->chan_addr <= limit) 486 goto rir_found; 487 } 488 prev_limit = limit; 489 } 490 edac_dbg(0, "No RIR entry for 0x%llx\n", res->addr); 491 return false; 492 493 rir_found: 494 rank_addr = res->chan_addr >> shift; 495 rank_addr /= SKX_RIR_WAYS(rirway); 496 rank_addr <<= shift; 497 rank_addr |= res->chan_addr & GENMASK_ULL(shift - 1, 0); 498 499 res->rank_address = rank_addr; 500 idx = (res->chan_addr >> shift) % SKX_RIR_WAYS(rirway); 501 502 SKX_GET_RIRILV(res->dev, res->imc, res->channel, idx, i, rirlv); 503 res->rank_address = rank_addr - SKX_RIR_OFFSET(rirlv); 504 chan_rank = SKX_RIR_CHAN_RANK(rirlv); 505 res->channel_rank = chan_rank; 506 res->dimm = chan_rank / 4; 507 res->rank = chan_rank % 4; 508 509 edac_dbg(2, "0x%llx: dimm=%d rank=%d chan_rank=%d rank_addr=0x%llx\n", 510 res->addr, res->dimm, res->rank, 511 res->channel_rank, res->rank_address); 512 return true; 513 } 514 515 static u8 skx_close_row[] = { 516 15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33, 34 517 }; 518 519 static u8 skx_close_column[] = { 520 3, 4, 5, 14, 19, 23, 24, 25, 26, 27 521 }; 522 523 static u8 skx_open_row[] = { 524 14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33, 34 525 }; 526 527 static u8 skx_open_column[] = { 528 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 529 }; 530 531 static u8 skx_open_fine_column[] = { 532 3, 4, 5, 7, 8, 9, 10, 11, 12, 13 533 }; 534 535 static int skx_bits(u64 addr, int nbits, u8 *bits) 536 { 537 int i, res = 0; 538 539 for (i = 0; i < nbits; i++) 540 res |= ((addr >> bits[i]) & 1) << i; 541 return res; 542 } 543 544 static int skx_bank_bits(u64 addr, int b0, int b1, int do_xor, int x0, int x1) 545 { 546 int ret = GET_BITFIELD(addr, b0, b0) | (GET_BITFIELD(addr, b1, b1) << 1); 547 548 if (do_xor) 549 ret ^= GET_BITFIELD(addr, x0, x0) | (GET_BITFIELD(addr, x1, x1) << 1); 550 551 return ret; 552 } 553 554 static bool skx_mad_decode(struct decoded_addr *r) 555 { 556 struct skx_dimm *dimm = &r->dev->imc[r->imc].chan[r->channel].dimms[r->dimm]; 557 int bg0 = dimm->fine_grain_bank ? 6 : 13; 558 559 if (dimm->close_pg) { 560 r->row = skx_bits(r->rank_address, dimm->rowbits, skx_close_row); 561 r->column = skx_bits(r->rank_address, dimm->colbits, skx_close_column); 562 r->column |= 0x400; /* C10 is autoprecharge, always set */ 563 r->bank_address = skx_bank_bits(r->rank_address, 8, 9, dimm->bank_xor_enable, 22, 28); 564 r->bank_group = skx_bank_bits(r->rank_address, 6, 7, dimm->bank_xor_enable, 20, 21); 565 } else { 566 r->row = skx_bits(r->rank_address, dimm->rowbits, skx_open_row); 567 if (dimm->fine_grain_bank) 568 r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_fine_column); 569 else 570 r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_column); 571 r->bank_address = skx_bank_bits(r->rank_address, 18, 19, dimm->bank_xor_enable, 22, 23); 572 r->bank_group = skx_bank_bits(r->rank_address, bg0, 17, dimm->bank_xor_enable, 20, 21); 573 } 574 r->row &= (1u << dimm->rowbits) - 1; 575 576 edac_dbg(2, "0x%llx: row=0x%x col=0x%x bank_addr=%d bank_group=%d\n", 577 r->addr, r->row, r->column, r->bank_address, 578 r->bank_group); 579 return true; 580 } 581 582 static bool skx_decode(struct decoded_addr *res) 583 { 584 return skx_sad_decode(res) && skx_tad_decode(res) && 585 skx_rir_decode(res) && skx_mad_decode(res); 586 } 587 588 static struct notifier_block skx_mce_dec = { 589 .notifier_call = skx_mce_check_error, 590 .priority = MCE_PRIO_EDAC, 591 }; 592 593 /* 594 * skx_init: 595 * make sure we are running on the correct cpu model 596 * search for all the devices we need 597 * check which DIMMs are present. 598 */ 599 static int __init skx_init(void) 600 { 601 const struct x86_cpu_id *id; 602 struct res_config *cfg; 603 const struct munit *m; 604 const char *owner; 605 int rc = 0, i, off[3] = {0xd0, 0xd4, 0xd8}; 606 u8 mc = 0, src_id; 607 struct skx_dev *d; 608 609 edac_dbg(2, "\n"); 610 611 if (ghes_get_devices()) 612 return -EBUSY; 613 614 owner = edac_get_owner(); 615 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR))) 616 return -EBUSY; 617 618 if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) 619 return -ENODEV; 620 621 id = x86_match_cpu(skx_cpuids); 622 if (!id) 623 return -ENODEV; 624 625 cfg = (struct res_config *)id->driver_data; 626 skx_set_res_cfg(cfg); 627 628 rc = skx_get_hi_lo(0x2034, off, &skx_tolm, &skx_tohm); 629 if (rc) 630 return rc; 631 632 rc = skx_get_all_bus_mappings(cfg, &skx_edac_list); 633 if (rc < 0) 634 goto fail; 635 if (rc == 0) { 636 edac_dbg(2, "No memory controllers found\n"); 637 return -ENODEV; 638 } 639 skx_num_sockets = rc; 640 641 for (m = skx_all_munits; m->did; m++) { 642 rc = get_all_munits(m); 643 if (rc < 0) 644 goto fail; 645 if (rc != m->per_socket * skx_num_sockets) { 646 edac_dbg(2, "Expected %d, got %d of 0x%x\n", 647 m->per_socket * skx_num_sockets, rc, m->did); 648 rc = -ENODEV; 649 goto fail; 650 } 651 } 652 653 list_for_each_entry(d, skx_edac_list, list) { 654 rc = skx_get_src_id(d, 0xf0, &src_id); 655 if (rc < 0) 656 goto fail; 657 658 edac_dbg(2, "src_id = %d\n", src_id); 659 for (i = 0; i < cfg->ddr_imc_num; i++) { 660 d->imc[i].mc = mc++; 661 d->imc[i].lmc = i; 662 d->imc[i].src_id = src_id; 663 d->imc[i].num_channels = cfg->ddr_chan_num; 664 d->imc[i].num_dimms = cfg->ddr_dimm_num; 665 666 rc = skx_register_mci(&d->imc[i], d->imc[i].chan[0].cdev, 667 "Skylake Socket", EDAC_MOD_STR, 668 skx_get_dimm_config, cfg); 669 if (rc < 0) 670 goto fail; 671 } 672 } 673 674 skx_set_decode(skx_decode, skx_show_retry_rd_err_log); 675 676 if (nvdimm_count && skx_adxl_get() != -ENODEV) { 677 skx_set_decode(NULL, skx_show_retry_rd_err_log); 678 } else { 679 if (nvdimm_count) 680 skx_printk(KERN_NOTICE, "Only decoding DDR4 address!\n"); 681 skx_set_decode(skx_decode, skx_show_retry_rd_err_log); 682 } 683 684 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 685 opstate_init(); 686 687 skx_setup_debug("skx_test"); 688 689 mce_register_decode_chain(&skx_mce_dec); 690 691 return 0; 692 fail: 693 skx_remove(); 694 return rc; 695 } 696 697 static void __exit skx_exit(void) 698 { 699 edac_dbg(2, "\n"); 700 mce_unregister_decode_chain(&skx_mce_dec); 701 skx_teardown_debug(); 702 if (nvdimm_count) 703 skx_adxl_put(); 704 skx_remove(); 705 } 706 707 module_init(skx_init); 708 module_exit(skx_exit); 709 710 module_param(edac_op_state, int, 0444); 711 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 712 713 MODULE_LICENSE("GPL v2"); 714 MODULE_AUTHOR("Tony Luck"); 715 MODULE_DESCRIPTION("MC Driver for Intel Skylake server processors"); 716