1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module 3 * 4 * This driver supports the memory controllers found on the Intel 5 * processor family Sandy Bridge. 6 * 7 * Copyright (c) 2011 by: 8 * Mauro Carvalho Chehab 9 */ 10 11 #include <linux/module.h> 12 #include <linux/init.h> 13 #include <linux/pci.h> 14 #include <linux/pci_ids.h> 15 #include <linux/slab.h> 16 #include <linux/delay.h> 17 #include <linux/edac.h> 18 #include <linux/mmzone.h> 19 #include <linux/smp.h> 20 #include <linux/bitmap.h> 21 #include <linux/math64.h> 22 #include <linux/mod_devicetable.h> 23 #include <asm/cpu_device_id.h> 24 #include <asm/intel-family.h> 25 #include <asm/processor.h> 26 #include <asm/mce.h> 27 28 #include "edac_module.h" 29 30 /* Static vars */ 31 static LIST_HEAD(sbridge_edac_list); 32 33 /* 34 * Alter this version for the module when modifications are made 35 */ 36 #define SBRIDGE_REVISION " Ver: 1.1.2 " 37 #define EDAC_MOD_STR "sb_edac" 38 39 /* 40 * Debug macros 41 */ 42 #define sbridge_printk(level, fmt, arg...) \ 43 edac_printk(level, "sbridge", fmt, ##arg) 44 45 #define sbridge_mc_printk(mci, level, fmt, arg...) \ 46 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg) 47 48 /* 49 * Get a bit field at register value <v>, from bit <lo> to bit <hi> 50 */ 51 #define GET_BITFIELD(v, lo, hi) \ 52 (((v) & GENMASK_ULL(hi, lo)) >> (lo)) 53 54 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */ 55 static const u32 sbridge_dram_rule[] = { 56 0x80, 0x88, 0x90, 0x98, 0xa0, 57 0xa8, 0xb0, 0xb8, 0xc0, 0xc8, 58 }; 59 60 static const u32 ibridge_dram_rule[] = { 61 0x60, 0x68, 0x70, 0x78, 0x80, 62 0x88, 0x90, 0x98, 0xa0, 0xa8, 63 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, 64 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, 65 }; 66 67 static const u32 knl_dram_rule[] = { 68 0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */ 69 0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */ 70 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */ 71 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */ 72 0x100, 0x108, 0x110, 0x118, /* 20-23 */ 73 }; 74 75 #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0) 76 #define A7MODE(reg) GET_BITFIELD(reg, 26, 26) 77 78 static char *show_dram_attr(u32 attr) 79 { 80 switch (attr) { 81 case 0: 82 return "DRAM"; 83 case 1: 84 return "MMCFG"; 85 case 2: 86 return "NXM"; 87 default: 88 return "unknown"; 89 } 90 } 91 92 static const u32 sbridge_interleave_list[] = { 93 0x84, 0x8c, 0x94, 0x9c, 0xa4, 94 0xac, 0xb4, 0xbc, 0xc4, 0xcc, 95 }; 96 97 static const u32 ibridge_interleave_list[] = { 98 0x64, 0x6c, 0x74, 0x7c, 0x84, 99 0x8c, 0x94, 0x9c, 0xa4, 0xac, 100 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, 101 0xdc, 0xe4, 0xec, 0xf4, 0xfc, 102 }; 103 104 static const u32 knl_interleave_list[] = { 105 0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */ 106 0x8c, 0x94, 0x9c, 0xa4, 0xac, /* 5-9 */ 107 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, /* 10-14 */ 108 0xdc, 0xe4, 0xec, 0xf4, 0xfc, /* 15-19 */ 109 0x104, 0x10c, 0x114, 0x11c, /* 20-23 */ 110 }; 111 #define MAX_INTERLEAVE \ 112 (max_t(unsigned int, ARRAY_SIZE(sbridge_interleave_list), \ 113 max_t(unsigned int, ARRAY_SIZE(ibridge_interleave_list), \ 114 ARRAY_SIZE(knl_interleave_list)))) 115 116 struct interleave_pkg { 117 unsigned char start; 118 unsigned char end; 119 }; 120 121 static const struct interleave_pkg sbridge_interleave_pkg[] = { 122 { 0, 2 }, 123 { 3, 5 }, 124 { 8, 10 }, 125 { 11, 13 }, 126 { 16, 18 }, 127 { 19, 21 }, 128 { 24, 26 }, 129 { 27, 29 }, 130 }; 131 132 static const struct interleave_pkg ibridge_interleave_pkg[] = { 133 { 0, 3 }, 134 { 4, 7 }, 135 { 8, 11 }, 136 { 12, 15 }, 137 { 16, 19 }, 138 { 20, 23 }, 139 { 24, 27 }, 140 { 28, 31 }, 141 }; 142 143 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg, 144 int interleave) 145 { 146 return GET_BITFIELD(reg, table[interleave].start, 147 table[interleave].end); 148 } 149 150 /* Devices 12 Function 7 */ 151 152 #define TOLM 0x80 153 #define TOHM 0x84 154 #define HASWELL_TOLM 0xd0 155 #define HASWELL_TOHM_0 0xd4 156 #define HASWELL_TOHM_1 0xd8 157 #define KNL_TOLM 0xd0 158 #define KNL_TOHM_0 0xd4 159 #define KNL_TOHM_1 0xd8 160 161 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff) 162 #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff) 163 164 /* Device 13 Function 6 */ 165 166 #define SAD_TARGET 0xf0 167 168 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11) 169 170 #define SOURCE_ID_KNL(reg) GET_BITFIELD(reg, 12, 14) 171 172 #define SAD_CONTROL 0xf4 173 174 /* Device 14 function 0 */ 175 176 static const u32 tad_dram_rule[] = { 177 0x40, 0x44, 0x48, 0x4c, 178 0x50, 0x54, 0x58, 0x5c, 179 0x60, 0x64, 0x68, 0x6c, 180 }; 181 #define MAX_TAD ARRAY_SIZE(tad_dram_rule) 182 183 #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff) 184 #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11) 185 #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9) 186 #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7) 187 #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5) 188 #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3) 189 #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1) 190 191 /* Device 15, function 0 */ 192 193 #define MCMTR 0x7c 194 #define KNL_MCMTR 0x624 195 196 #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2) 197 #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1) 198 #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0) 199 200 /* Device 15, function 1 */ 201 202 #define RASENABLES 0xac 203 #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0) 204 205 /* Device 15, functions 2-5 */ 206 207 static const int mtr_regs[] = { 208 0x80, 0x84, 0x88, 209 }; 210 211 static const int knl_mtr_reg = 0xb60; 212 213 #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19) 214 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14) 215 #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13) 216 #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4) 217 #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1) 218 219 static const u32 tad_ch_nilv_offset[] = { 220 0x90, 0x94, 0x98, 0x9c, 221 0xa0, 0xa4, 0xa8, 0xac, 222 0xb0, 0xb4, 0xb8, 0xbc, 223 }; 224 #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29) 225 #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26) 226 227 static const u32 rir_way_limit[] = { 228 0x108, 0x10c, 0x110, 0x114, 0x118, 229 }; 230 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit) 231 232 #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31) 233 #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29) 234 235 #define MAX_RIR_WAY 8 236 237 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = { 238 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c }, 239 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c }, 240 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c }, 241 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c }, 242 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc }, 243 }; 244 245 #define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \ 246 GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19)) 247 248 #define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \ 249 GET_BITFIELD(reg, 2, 15) : GET_BITFIELD(reg, 2, 14)) 250 251 /* Device 16, functions 2-7 */ 252 253 /* 254 * FIXME: Implement the error count reads directly 255 */ 256 257 #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31) 258 #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30) 259 #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15) 260 #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14) 261 262 #if 0 /* Currently unused*/ 263 static const u32 correrrcnt[] = { 264 0x104, 0x108, 0x10c, 0x110, 265 }; 266 267 static const u32 correrrthrsld[] = { 268 0x11c, 0x120, 0x124, 0x128, 269 }; 270 #endif 271 272 #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30) 273 #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14) 274 275 276 /* Device 17, function 0 */ 277 278 #define SB_RANK_CFG_A 0x0328 279 280 #define IB_RANK_CFG_A 0x0320 281 282 /* 283 * sbridge structs 284 */ 285 286 #define NUM_CHANNELS 6 /* Max channels per MC */ 287 #define MAX_DIMMS 3 /* Max DIMMS per channel */ 288 #define KNL_MAX_CHAS 38 /* KNL max num. of Cache Home Agents */ 289 #define KNL_MAX_CHANNELS 6 /* KNL max num. of PCI channels */ 290 #define KNL_MAX_EDCS 8 /* Embedded DRAM controllers */ 291 #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */ 292 293 enum type { 294 SANDY_BRIDGE, 295 IVY_BRIDGE, 296 HASWELL, 297 BROADWELL, 298 KNIGHTS_LANDING, 299 }; 300 301 enum domain { 302 IMC0 = 0, 303 IMC1, 304 SOCK, 305 }; 306 307 enum mirroring_mode { 308 NON_MIRRORING, 309 ADDR_RANGE_MIRRORING, 310 FULL_MIRRORING, 311 }; 312 313 struct sbridge_pvt; 314 struct sbridge_info { 315 enum type type; 316 u32 mcmtr; 317 u32 rankcfgr; 318 u64 (*get_tolm)(struct sbridge_pvt *pvt); 319 u64 (*get_tohm)(struct sbridge_pvt *pvt); 320 u64 (*rir_limit)(u32 reg); 321 u64 (*sad_limit)(u32 reg); 322 u32 (*interleave_mode)(u32 reg); 323 u32 (*dram_attr)(u32 reg); 324 const u32 *dram_rule; 325 const u32 *interleave_list; 326 const struct interleave_pkg *interleave_pkg; 327 u8 max_sad; 328 u8 (*get_node_id)(struct sbridge_pvt *pvt); 329 u8 (*get_ha)(u8 bank); 330 enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt); 331 enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr); 332 struct pci_dev *pci_vtd; 333 }; 334 335 struct sbridge_channel { 336 u32 ranks; 337 u32 dimms; 338 }; 339 340 struct pci_id_descr { 341 int dev_id; 342 int optional; 343 enum domain dom; 344 }; 345 346 struct pci_id_table { 347 const struct pci_id_descr *descr; 348 int n_devs_per_imc; 349 int n_devs_per_sock; 350 int n_imcs_per_sock; 351 enum type type; 352 }; 353 354 struct sbridge_dev { 355 struct list_head list; 356 int seg; 357 u8 bus, mc; 358 u8 node_id, source_id; 359 struct pci_dev **pdev; 360 enum domain dom; 361 int n_devs; 362 int i_devs; 363 struct mem_ctl_info *mci; 364 }; 365 366 struct knl_pvt { 367 struct pci_dev *pci_cha[KNL_MAX_CHAS]; 368 struct pci_dev *pci_channel[KNL_MAX_CHANNELS]; 369 struct pci_dev *pci_mc0; 370 struct pci_dev *pci_mc1; 371 struct pci_dev *pci_mc0_misc; 372 struct pci_dev *pci_mc1_misc; 373 struct pci_dev *pci_mc_info; /* tolm, tohm */ 374 }; 375 376 struct sbridge_pvt { 377 /* Devices per socket */ 378 struct pci_dev *pci_ddrio; 379 struct pci_dev *pci_sad0, *pci_sad1; 380 struct pci_dev *pci_br0, *pci_br1; 381 /* Devices per memory controller */ 382 struct pci_dev *pci_ha, *pci_ta, *pci_ras; 383 struct pci_dev *pci_tad[NUM_CHANNELS]; 384 385 struct sbridge_dev *sbridge_dev; 386 387 struct sbridge_info info; 388 struct sbridge_channel channel[NUM_CHANNELS]; 389 390 /* Memory type detection */ 391 bool is_cur_addr_mirrored, is_lockstep, is_close_pg; 392 bool is_chan_hash; 393 enum mirroring_mode mirror_mode; 394 395 /* Memory description */ 396 u64 tolm, tohm; 397 struct knl_pvt knl; 398 }; 399 400 #define PCI_DESCR(device_id, opt, domain) \ 401 .dev_id = (device_id), \ 402 .optional = opt, \ 403 .dom = domain 404 405 static const struct pci_id_descr pci_dev_descr_sbridge[] = { 406 /* Processor Home Agent */ 407 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0, IMC0) }, 408 409 /* Memory controller */ 410 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0, IMC0) }, 411 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0, IMC0) }, 412 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0, IMC0) }, 413 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0, IMC0) }, 414 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0, IMC0) }, 415 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0, IMC0) }, 416 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1, SOCK) }, 417 418 /* System Address Decoder */ 419 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0, SOCK) }, 420 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0, SOCK) }, 421 422 /* Broadcast Registers */ 423 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0, SOCK) }, 424 }; 425 426 #define PCI_ID_TABLE_ENTRY(A, N, M, T) { \ 427 .descr = A, \ 428 .n_devs_per_imc = N, \ 429 .n_devs_per_sock = ARRAY_SIZE(A), \ 430 .n_imcs_per_sock = M, \ 431 .type = T \ 432 } 433 434 static const struct pci_id_table pci_dev_descr_sbridge_table[] = { 435 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge, ARRAY_SIZE(pci_dev_descr_sbridge), 1, SANDY_BRIDGE), 436 {0,} /* 0 terminated list. */ 437 }; 438 439 /* This changes depending if 1HA or 2HA: 440 * 1HA: 441 * 0x0eb8 (17.0) is DDRIO0 442 * 2HA: 443 * 0x0ebc (17.4) is DDRIO0 444 */ 445 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8 446 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc 447 448 /* pci ids */ 449 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0 450 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8 451 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71 452 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa 453 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab 454 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac 455 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead 456 #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8 457 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9 458 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca 459 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60 460 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68 461 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79 462 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a 463 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b 464 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2 0x0e6c 465 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3 0x0e6d 466 467 static const struct pci_id_descr pci_dev_descr_ibridge[] = { 468 /* Processor Home Agent */ 469 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0, IMC0) }, 470 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1, IMC1) }, 471 472 /* Memory controller */ 473 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0, IMC0) }, 474 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0, IMC0) }, 475 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0, IMC0) }, 476 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0, IMC0) }, 477 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0, IMC0) }, 478 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0, IMC0) }, 479 480 /* Optional, mode 2HA */ 481 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1, IMC1) }, 482 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1, IMC1) }, 483 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1, IMC1) }, 484 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1, IMC1) }, 485 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1, IMC1) }, 486 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1, IMC1) }, 487 488 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1, SOCK) }, 489 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1, SOCK) }, 490 491 /* System Address Decoder */ 492 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0, SOCK) }, 493 494 /* Broadcast Registers */ 495 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1, SOCK) }, 496 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0, SOCK) }, 497 498 }; 499 500 static const struct pci_id_table pci_dev_descr_ibridge_table[] = { 501 PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge, 12, 2, IVY_BRIDGE), 502 {0,} /* 0 terminated list. */ 503 }; 504 505 /* Haswell support */ 506 /* EN processor: 507 * - 1 IMC 508 * - 3 DDR3 channels, 2 DPC per channel 509 * EP processor: 510 * - 1 or 2 IMC 511 * - 4 DDR4 channels, 3 DPC per channel 512 * EP 4S processor: 513 * - 2 IMC 514 * - 4 DDR4 channels, 3 DPC per channel 515 * EX processor: 516 * - 2 IMC 517 * - each IMC interfaces with a SMI 2 channel 518 * - each SMI channel interfaces with a scalable memory buffer 519 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC 520 */ 521 #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */ 522 #define HASWELL_HASYSDEFEATURE2 0x84 523 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28 524 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0 525 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60 526 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8 527 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM 0x2f71 528 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68 529 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM 0x2f79 530 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc 531 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd 532 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa 533 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab 534 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac 535 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad 536 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a 537 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b 538 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c 539 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d 540 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd 541 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf 542 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9 543 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb 544 static const struct pci_id_descr pci_dev_descr_haswell[] = { 545 /* first item must be the HA */ 546 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0, IMC0) }, 547 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1, IMC1) }, 548 549 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0, IMC0) }, 550 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM, 0, IMC0) }, 551 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0, IMC0) }, 552 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0, IMC0) }, 553 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1, IMC0) }, 554 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1, IMC0) }, 555 556 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1, IMC1) }, 557 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM, 1, IMC1) }, 558 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1, IMC1) }, 559 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1, IMC1) }, 560 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1, IMC1) }, 561 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1, IMC1) }, 562 563 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0, SOCK) }, 564 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0, SOCK) }, 565 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1, SOCK) }, 566 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1, SOCK) }, 567 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1, SOCK) }, 568 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1, SOCK) }, 569 }; 570 571 static const struct pci_id_table pci_dev_descr_haswell_table[] = { 572 PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell, 13, 2, HASWELL), 573 {0,} /* 0 terminated list. */ 574 }; 575 576 /* Knight's Landing Support */ 577 /* 578 * KNL's memory channels are swizzled between memory controllers. 579 * MC0 is mapped to CH3,4,5 and MC1 is mapped to CH0,1,2 580 */ 581 #define knl_channel_remap(mc, chan) ((mc) ? (chan) : (chan) + 3) 582 583 /* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */ 584 #define PCI_DEVICE_ID_INTEL_KNL_IMC_MC 0x7840 585 /* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */ 586 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN 0x7843 587 /* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */ 588 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TA 0x7844 589 /* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */ 590 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0 0x782a 591 /* SAD target - 1-29-1 (1 of these) */ 592 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1 0x782b 593 /* Caching / Home Agent */ 594 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHA 0x782c 595 /* Device with TOLM and TOHM, 0-5-0 (1 of these) */ 596 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM 0x7810 597 598 /* 599 * KNL differs from SB, IB, and Haswell in that it has multiple 600 * instances of the same device with the same device ID, so we handle that 601 * by creating as many copies in the table as we expect to find. 602 * (Like device ID must be grouped together.) 603 */ 604 605 static const struct pci_id_descr pci_dev_descr_knl[] = { 606 [0 ... 1] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_MC, 0, IMC0)}, 607 [2 ... 7] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN, 0, IMC0) }, 608 [8] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TA, 0, IMC0) }, 609 [9] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM, 0, IMC0) }, 610 [10] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0, 0, SOCK) }, 611 [11] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1, 0, SOCK) }, 612 [12 ... 49] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHA, 0, SOCK) }, 613 }; 614 615 static const struct pci_id_table pci_dev_descr_knl_table[] = { 616 PCI_ID_TABLE_ENTRY(pci_dev_descr_knl, ARRAY_SIZE(pci_dev_descr_knl), 1, KNIGHTS_LANDING), 617 {0,} 618 }; 619 620 /* 621 * Broadwell support 622 * 623 * DE processor: 624 * - 1 IMC 625 * - 2 DDR3 channels, 2 DPC per channel 626 * EP processor: 627 * - 1 or 2 IMC 628 * - 4 DDR4 channels, 3 DPC per channel 629 * EP 4S processor: 630 * - 2 IMC 631 * - 4 DDR4 channels, 3 DPC per channel 632 * EX processor: 633 * - 2 IMC 634 * - each IMC interfaces with a SMI 2 channel 635 * - each SMI channel interfaces with a scalable memory buffer 636 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC 637 */ 638 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28 639 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0x6fa0 640 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1 0x6f60 641 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0x6fa8 642 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM 0x6f71 643 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA 0x6f68 644 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM 0x6f79 645 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc 646 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd 647 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa 648 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab 649 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac 650 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad 651 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a 652 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b 653 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c 654 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d 655 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf 656 657 static const struct pci_id_descr pci_dev_descr_broadwell[] = { 658 /* first item must be the HA */ 659 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0, IMC0) }, 660 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1, IMC1) }, 661 662 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0, IMC0) }, 663 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM, 0, IMC0) }, 664 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0, IMC0) }, 665 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0, IMC0) }, 666 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1, IMC0) }, 667 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1, IMC0) }, 668 669 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1, IMC1) }, 670 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM, 1, IMC1) }, 671 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1, IMC1) }, 672 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1, IMC1) }, 673 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1, IMC1) }, 674 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1, IMC1) }, 675 676 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0, SOCK) }, 677 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0, SOCK) }, 678 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1, SOCK) }, 679 }; 680 681 static const struct pci_id_table pci_dev_descr_broadwell_table[] = { 682 PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell, 10, 2, BROADWELL), 683 {0,} /* 0 terminated list. */ 684 }; 685 686 687 /**************************************************************************** 688 Ancillary status routines 689 ****************************************************************************/ 690 691 static inline int numrank(enum type type, u32 mtr) 692 { 693 int ranks = (1 << RANK_CNT_BITS(mtr)); 694 int max = 4; 695 696 if (type == HASWELL || type == BROADWELL || type == KNIGHTS_LANDING) 697 max = 8; 698 699 if (ranks > max) { 700 edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n", 701 ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr); 702 return -EINVAL; 703 } 704 705 return ranks; 706 } 707 708 static inline int numrow(u32 mtr) 709 { 710 int rows = (RANK_WIDTH_BITS(mtr) + 12); 711 712 if (rows < 13 || rows > 18) { 713 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n", 714 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr); 715 return -EINVAL; 716 } 717 718 return 1 << rows; 719 } 720 721 static inline int numcol(u32 mtr) 722 { 723 int cols = (COL_WIDTH_BITS(mtr) + 10); 724 725 if (cols > 12) { 726 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n", 727 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr); 728 return -EINVAL; 729 } 730 731 return 1 << cols; 732 } 733 734 static struct sbridge_dev *get_sbridge_dev(int seg, u8 bus, enum domain dom, 735 int multi_bus, 736 struct sbridge_dev *prev) 737 { 738 struct sbridge_dev *sbridge_dev; 739 740 /* 741 * If we have devices scattered across several busses that pertain 742 * to the same memory controller, we'll lump them all together. 743 */ 744 if (multi_bus) { 745 return list_first_entry_or_null(&sbridge_edac_list, 746 struct sbridge_dev, list); 747 } 748 749 sbridge_dev = list_entry(prev ? prev->list.next 750 : sbridge_edac_list.next, struct sbridge_dev, list); 751 752 list_for_each_entry_from(sbridge_dev, &sbridge_edac_list, list) { 753 if ((sbridge_dev->seg == seg) && (sbridge_dev->bus == bus) && 754 (dom == SOCK || dom == sbridge_dev->dom)) 755 return sbridge_dev; 756 } 757 758 return NULL; 759 } 760 761 static struct sbridge_dev *alloc_sbridge_dev(int seg, u8 bus, enum domain dom, 762 const struct pci_id_table *table) 763 { 764 struct sbridge_dev *sbridge_dev; 765 766 sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL); 767 if (!sbridge_dev) 768 return NULL; 769 770 sbridge_dev->pdev = kcalloc(table->n_devs_per_imc, 771 sizeof(*sbridge_dev->pdev), 772 GFP_KERNEL); 773 if (!sbridge_dev->pdev) { 774 kfree(sbridge_dev); 775 return NULL; 776 } 777 778 sbridge_dev->seg = seg; 779 sbridge_dev->bus = bus; 780 sbridge_dev->dom = dom; 781 sbridge_dev->n_devs = table->n_devs_per_imc; 782 list_add_tail(&sbridge_dev->list, &sbridge_edac_list); 783 784 return sbridge_dev; 785 } 786 787 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev) 788 { 789 list_del(&sbridge_dev->list); 790 kfree(sbridge_dev->pdev); 791 kfree(sbridge_dev); 792 } 793 794 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt) 795 { 796 u32 reg; 797 798 /* Address range is 32:28 */ 799 pci_read_config_dword(pvt->pci_sad1, TOLM, ®); 800 return GET_TOLM(reg); 801 } 802 803 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt) 804 { 805 u32 reg; 806 807 pci_read_config_dword(pvt->pci_sad1, TOHM, ®); 808 return GET_TOHM(reg); 809 } 810 811 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt) 812 { 813 u32 reg; 814 815 pci_read_config_dword(pvt->pci_br1, TOLM, ®); 816 817 return GET_TOLM(reg); 818 } 819 820 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt) 821 { 822 u32 reg; 823 824 pci_read_config_dword(pvt->pci_br1, TOHM, ®); 825 826 return GET_TOHM(reg); 827 } 828 829 static u64 rir_limit(u32 reg) 830 { 831 return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff; 832 } 833 834 static u64 sad_limit(u32 reg) 835 { 836 return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff; 837 } 838 839 static u32 interleave_mode(u32 reg) 840 { 841 return GET_BITFIELD(reg, 1, 1); 842 } 843 844 static u32 dram_attr(u32 reg) 845 { 846 return GET_BITFIELD(reg, 2, 3); 847 } 848 849 static u64 knl_sad_limit(u32 reg) 850 { 851 return (GET_BITFIELD(reg, 7, 26) << 26) | 0x3ffffff; 852 } 853 854 static u32 knl_interleave_mode(u32 reg) 855 { 856 return GET_BITFIELD(reg, 1, 2); 857 } 858 859 static const char * const knl_intlv_mode[] = { 860 "[8:6]", "[10:8]", "[14:12]", "[32:30]" 861 }; 862 863 static const char *get_intlv_mode_str(u32 reg, enum type t) 864 { 865 if (t == KNIGHTS_LANDING) 866 return knl_intlv_mode[knl_interleave_mode(reg)]; 867 else 868 return interleave_mode(reg) ? "[8:6]" : "[8:6]XOR[18:16]"; 869 } 870 871 static u32 dram_attr_knl(u32 reg) 872 { 873 return GET_BITFIELD(reg, 3, 4); 874 } 875 876 877 static enum mem_type get_memory_type(struct sbridge_pvt *pvt) 878 { 879 u32 reg; 880 enum mem_type mtype; 881 882 if (pvt->pci_ddrio) { 883 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr, 884 ®); 885 if (GET_BITFIELD(reg, 11, 11)) 886 /* FIXME: Can also be LRDIMM */ 887 mtype = MEM_RDDR3; 888 else 889 mtype = MEM_DDR3; 890 } else 891 mtype = MEM_UNKNOWN; 892 893 return mtype; 894 } 895 896 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt) 897 { 898 u32 reg; 899 bool registered = false; 900 enum mem_type mtype = MEM_UNKNOWN; 901 902 if (!pvt->pci_ddrio) 903 goto out; 904 905 pci_read_config_dword(pvt->pci_ddrio, 906 HASWELL_DDRCRCLKCONTROLS, ®); 907 /* Is_Rdimm */ 908 if (GET_BITFIELD(reg, 16, 16)) 909 registered = true; 910 911 pci_read_config_dword(pvt->pci_ta, MCMTR, ®); 912 if (GET_BITFIELD(reg, 14, 14)) { 913 if (registered) 914 mtype = MEM_RDDR4; 915 else 916 mtype = MEM_DDR4; 917 } else { 918 if (registered) 919 mtype = MEM_RDDR3; 920 else 921 mtype = MEM_DDR3; 922 } 923 924 out: 925 return mtype; 926 } 927 928 static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr) 929 { 930 /* for KNL value is fixed */ 931 return DEV_X16; 932 } 933 934 static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr) 935 { 936 /* there's no way to figure out */ 937 return DEV_UNKNOWN; 938 } 939 940 static enum dev_type __ibridge_get_width(u32 mtr) 941 { 942 enum dev_type type; 943 944 switch (mtr) { 945 case 3: 946 type = DEV_UNKNOWN; 947 break; 948 case 2: 949 type = DEV_X16; 950 break; 951 case 1: 952 type = DEV_X8; 953 break; 954 case 0: 955 type = DEV_X4; 956 break; 957 } 958 959 return type; 960 } 961 962 static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr) 963 { 964 /* 965 * ddr3_width on the documentation but also valid for DDR4 on 966 * Haswell 967 */ 968 return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8)); 969 } 970 971 static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr) 972 { 973 /* ddr3_width on the documentation but also valid for DDR4 */ 974 return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9)); 975 } 976 977 static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt) 978 { 979 /* DDR4 RDIMMS and LRDIMMS are supported */ 980 return MEM_RDDR4; 981 } 982 983 static u8 get_node_id(struct sbridge_pvt *pvt) 984 { 985 u32 reg; 986 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®); 987 return GET_BITFIELD(reg, 0, 2); 988 } 989 990 static u8 haswell_get_node_id(struct sbridge_pvt *pvt) 991 { 992 u32 reg; 993 994 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); 995 return GET_BITFIELD(reg, 0, 3); 996 } 997 998 static u8 knl_get_node_id(struct sbridge_pvt *pvt) 999 { 1000 u32 reg; 1001 1002 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); 1003 return GET_BITFIELD(reg, 0, 2); 1004 } 1005 1006 /* 1007 * Use the reporting bank number to determine which memory 1008 * controller (also known as "ha" for "home agent"). Sandy 1009 * Bridge only has one memory controller per socket, so the 1010 * answer is always zero. 1011 */ 1012 static u8 sbridge_get_ha(u8 bank) 1013 { 1014 return 0; 1015 } 1016 1017 /* 1018 * On Ivy Bridge, Haswell and Broadwell the error may be in a 1019 * home agent bank (7, 8), or one of the per-channel memory 1020 * controller banks (9 .. 16). 1021 */ 1022 static u8 ibridge_get_ha(u8 bank) 1023 { 1024 switch (bank) { 1025 case 7 ... 8: 1026 return bank - 7; 1027 case 9 ... 16: 1028 return (bank - 9) / 4; 1029 default: 1030 return 0xff; 1031 } 1032 } 1033 1034 /* Not used, but included for safety/symmetry */ 1035 static u8 knl_get_ha(u8 bank) 1036 { 1037 return 0xff; 1038 } 1039 1040 static u64 haswell_get_tolm(struct sbridge_pvt *pvt) 1041 { 1042 u32 reg; 1043 1044 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®); 1045 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff; 1046 } 1047 1048 static u64 haswell_get_tohm(struct sbridge_pvt *pvt) 1049 { 1050 u64 rc; 1051 u32 reg; 1052 1053 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®); 1054 rc = GET_BITFIELD(reg, 26, 31); 1055 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®); 1056 rc = ((reg << 6) | rc) << 26; 1057 1058 return rc | 0x1ffffff; 1059 } 1060 1061 static u64 knl_get_tolm(struct sbridge_pvt *pvt) 1062 { 1063 u32 reg; 1064 1065 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, ®); 1066 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff; 1067 } 1068 1069 static u64 knl_get_tohm(struct sbridge_pvt *pvt) 1070 { 1071 u64 rc; 1072 u32 reg_lo, reg_hi; 1073 1074 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, ®_lo); 1075 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, ®_hi); 1076 rc = ((u64)reg_hi << 32) | reg_lo; 1077 return rc | 0x3ffffff; 1078 } 1079 1080 1081 static u64 haswell_rir_limit(u32 reg) 1082 { 1083 return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1; 1084 } 1085 1086 static inline u8 sad_pkg_socket(u8 pkg) 1087 { 1088 /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */ 1089 return ((pkg >> 3) << 2) | (pkg & 0x3); 1090 } 1091 1092 static inline u8 sad_pkg_ha(u8 pkg) 1093 { 1094 return (pkg >> 2) & 0x1; 1095 } 1096 1097 static int haswell_chan_hash(int idx, u64 addr) 1098 { 1099 int i; 1100 1101 /* 1102 * XOR even bits from 12:26 to bit0 of idx, 1103 * odd bits from 13:27 to bit1 1104 */ 1105 for (i = 12; i < 28; i += 2) 1106 idx ^= (addr >> i) & 3; 1107 1108 return idx; 1109 } 1110 1111 /* Low bits of TAD limit, and some metadata. */ 1112 static const u32 knl_tad_dram_limit_lo[] = { 1113 0x400, 0x500, 0x600, 0x700, 1114 0x800, 0x900, 0xa00, 0xb00, 1115 }; 1116 1117 /* Low bits of TAD offset. */ 1118 static const u32 knl_tad_dram_offset_lo[] = { 1119 0x404, 0x504, 0x604, 0x704, 1120 0x804, 0x904, 0xa04, 0xb04, 1121 }; 1122 1123 /* High 16 bits of TAD limit and offset. */ 1124 static const u32 knl_tad_dram_hi[] = { 1125 0x408, 0x508, 0x608, 0x708, 1126 0x808, 0x908, 0xa08, 0xb08, 1127 }; 1128 1129 /* Number of ways a tad entry is interleaved. */ 1130 static const u32 knl_tad_ways[] = { 1131 8, 6, 4, 3, 2, 1, 1132 }; 1133 1134 /* 1135 * Retrieve the n'th Target Address Decode table entry 1136 * from the memory controller's TAD table. 1137 * 1138 * @pvt: driver private data 1139 * @entry: which entry you want to retrieve 1140 * @mc: which memory controller (0 or 1) 1141 * @offset: output tad range offset 1142 * @limit: output address of first byte above tad range 1143 * @ways: output number of interleave ways 1144 * 1145 * The offset value has curious semantics. It's a sort of running total 1146 * of the sizes of all the memory regions that aren't mapped in this 1147 * tad table. 1148 */ 1149 static int knl_get_tad(const struct sbridge_pvt *pvt, 1150 const int entry, 1151 const int mc, 1152 u64 *offset, 1153 u64 *limit, 1154 int *ways) 1155 { 1156 u32 reg_limit_lo, reg_offset_lo, reg_hi; 1157 struct pci_dev *pci_mc; 1158 int way_id; 1159 1160 switch (mc) { 1161 case 0: 1162 pci_mc = pvt->knl.pci_mc0; 1163 break; 1164 case 1: 1165 pci_mc = pvt->knl.pci_mc1; 1166 break; 1167 default: 1168 WARN_ON(1); 1169 return -EINVAL; 1170 } 1171 1172 pci_read_config_dword(pci_mc, 1173 knl_tad_dram_limit_lo[entry], ®_limit_lo); 1174 pci_read_config_dword(pci_mc, 1175 knl_tad_dram_offset_lo[entry], ®_offset_lo); 1176 pci_read_config_dword(pci_mc, 1177 knl_tad_dram_hi[entry], ®_hi); 1178 1179 /* Is this TAD entry enabled? */ 1180 if (!GET_BITFIELD(reg_limit_lo, 0, 0)) 1181 return -ENODEV; 1182 1183 way_id = GET_BITFIELD(reg_limit_lo, 3, 5); 1184 1185 if (way_id < ARRAY_SIZE(knl_tad_ways)) { 1186 *ways = knl_tad_ways[way_id]; 1187 } else { 1188 *ways = 0; 1189 sbridge_printk(KERN_ERR, 1190 "Unexpected value %d in mc_tad_limit_lo wayness field\n", 1191 way_id); 1192 return -ENODEV; 1193 } 1194 1195 /* 1196 * The least significant 6 bits of base and limit are truncated. 1197 * For limit, we fill the missing bits with 1s. 1198 */ 1199 *offset = ((u64) GET_BITFIELD(reg_offset_lo, 6, 31) << 6) | 1200 ((u64) GET_BITFIELD(reg_hi, 0, 15) << 32); 1201 *limit = ((u64) GET_BITFIELD(reg_limit_lo, 6, 31) << 6) | 63 | 1202 ((u64) GET_BITFIELD(reg_hi, 16, 31) << 32); 1203 1204 return 0; 1205 } 1206 1207 /* Determine which memory controller is responsible for a given channel. */ 1208 static int knl_channel_mc(int channel) 1209 { 1210 WARN_ON(channel < 0 || channel >= 6); 1211 1212 return channel < 3 ? 1 : 0; 1213 } 1214 1215 /* 1216 * Get the Nth entry from EDC_ROUTE_TABLE register. 1217 * (This is the per-tile mapping of logical interleave targets to 1218 * physical EDC modules.) 1219 * 1220 * entry 0: 0:2 1221 * 1: 3:5 1222 * 2: 6:8 1223 * 3: 9:11 1224 * 4: 12:14 1225 * 5: 15:17 1226 * 6: 18:20 1227 * 7: 21:23 1228 * reserved: 24:31 1229 */ 1230 static u32 knl_get_edc_route(int entry, u32 reg) 1231 { 1232 WARN_ON(entry >= KNL_MAX_EDCS); 1233 return GET_BITFIELD(reg, entry*3, (entry*3)+2); 1234 } 1235 1236 /* 1237 * Get the Nth entry from MC_ROUTE_TABLE register. 1238 * (This is the per-tile mapping of logical interleave targets to 1239 * physical DRAM channels modules.) 1240 * 1241 * entry 0: mc 0:2 channel 18:19 1242 * 1: mc 3:5 channel 20:21 1243 * 2: mc 6:8 channel 22:23 1244 * 3: mc 9:11 channel 24:25 1245 * 4: mc 12:14 channel 26:27 1246 * 5: mc 15:17 channel 28:29 1247 * reserved: 30:31 1248 * 1249 * Though we have 3 bits to identify the MC, we should only see 1250 * the values 0 or 1. 1251 */ 1252 1253 static u32 knl_get_mc_route(int entry, u32 reg) 1254 { 1255 int mc, chan; 1256 1257 WARN_ON(entry >= KNL_MAX_CHANNELS); 1258 1259 mc = GET_BITFIELD(reg, entry*3, (entry*3)+2); 1260 chan = GET_BITFIELD(reg, (entry*2) + 18, (entry*2) + 18 + 1); 1261 1262 return knl_channel_remap(mc, chan); 1263 } 1264 1265 /* 1266 * Render the EDC_ROUTE register in human-readable form. 1267 * Output string s should be at least KNL_MAX_EDCS*2 bytes. 1268 */ 1269 static void knl_show_edc_route(u32 reg, char *s) 1270 { 1271 int i; 1272 1273 for (i = 0; i < KNL_MAX_EDCS; i++) { 1274 s[i*2] = knl_get_edc_route(i, reg) + '0'; 1275 s[i*2+1] = '-'; 1276 } 1277 1278 s[KNL_MAX_EDCS*2 - 1] = '\0'; 1279 } 1280 1281 /* 1282 * Render the MC_ROUTE register in human-readable form. 1283 * Output string s should be at least KNL_MAX_CHANNELS*2 bytes. 1284 */ 1285 static void knl_show_mc_route(u32 reg, char *s) 1286 { 1287 int i; 1288 1289 for (i = 0; i < KNL_MAX_CHANNELS; i++) { 1290 s[i*2] = knl_get_mc_route(i, reg) + '0'; 1291 s[i*2+1] = '-'; 1292 } 1293 1294 s[KNL_MAX_CHANNELS*2 - 1] = '\0'; 1295 } 1296 1297 #define KNL_EDC_ROUTE 0xb8 1298 #define KNL_MC_ROUTE 0xb4 1299 1300 /* Is this dram rule backed by regular DRAM in flat mode? */ 1301 #define KNL_EDRAM(reg) GET_BITFIELD(reg, 29, 29) 1302 1303 /* Is this dram rule cached? */ 1304 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28) 1305 1306 /* Is this rule backed by edc ? */ 1307 #define KNL_EDRAM_ONLY(reg) GET_BITFIELD(reg, 29, 29) 1308 1309 /* Is this rule backed by DRAM, cacheable in EDRAM? */ 1310 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28) 1311 1312 /* Is this rule mod3? */ 1313 #define KNL_MOD3(reg) GET_BITFIELD(reg, 27, 27) 1314 1315 /* 1316 * Figure out how big our RAM modules are. 1317 * 1318 * The DIMMMTR register in KNL doesn't tell us the size of the DIMMs, so we 1319 * have to figure this out from the SAD rules, interleave lists, route tables, 1320 * and TAD rules. 1321 * 1322 * SAD rules can have holes in them (e.g. the 3G-4G hole), so we have to 1323 * inspect the TAD rules to figure out how large the SAD regions really are. 1324 * 1325 * When we know the real size of a SAD region and how many ways it's 1326 * interleaved, we know the individual contribution of each channel to 1327 * TAD is size/ways. 1328 * 1329 * Finally, we have to check whether each channel participates in each SAD 1330 * region. 1331 * 1332 * Fortunately, KNL only supports one DIMM per channel, so once we know how 1333 * much memory the channel uses, we know the DIMM is at least that large. 1334 * (The BIOS might possibly choose not to map all available memory, in which 1335 * case we will underreport the size of the DIMM.) 1336 * 1337 * In theory, we could try to determine the EDC sizes as well, but that would 1338 * only work in flat mode, not in cache mode. 1339 * 1340 * @mc_sizes: Output sizes of channels (must have space for KNL_MAX_CHANNELS 1341 * elements) 1342 */ 1343 static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes) 1344 { 1345 u64 sad_base, sad_limit = 0; 1346 u64 tad_base, tad_size, tad_limit, tad_deadspace, tad_livespace; 1347 int sad_rule = 0; 1348 int tad_rule = 0; 1349 int intrlv_ways, tad_ways; 1350 u32 first_pkg, pkg; 1351 int i; 1352 u64 sad_actual_size[2]; /* sad size accounting for holes, per mc */ 1353 u32 dram_rule, interleave_reg; 1354 u32 mc_route_reg[KNL_MAX_CHAS]; 1355 u32 edc_route_reg[KNL_MAX_CHAS]; 1356 int edram_only; 1357 char edc_route_string[KNL_MAX_EDCS*2]; 1358 char mc_route_string[KNL_MAX_CHANNELS*2]; 1359 int cur_reg_start; 1360 int mc; 1361 int channel; 1362 int participants[KNL_MAX_CHANNELS]; 1363 1364 for (i = 0; i < KNL_MAX_CHANNELS; i++) 1365 mc_sizes[i] = 0; 1366 1367 /* Read the EDC route table in each CHA. */ 1368 cur_reg_start = 0; 1369 for (i = 0; i < KNL_MAX_CHAS; i++) { 1370 pci_read_config_dword(pvt->knl.pci_cha[i], 1371 KNL_EDC_ROUTE, &edc_route_reg[i]); 1372 1373 if (i > 0 && edc_route_reg[i] != edc_route_reg[i-1]) { 1374 knl_show_edc_route(edc_route_reg[i-1], 1375 edc_route_string); 1376 if (cur_reg_start == i-1) 1377 edac_dbg(0, "edc route table for CHA %d: %s\n", 1378 cur_reg_start, edc_route_string); 1379 else 1380 edac_dbg(0, "edc route table for CHA %d-%d: %s\n", 1381 cur_reg_start, i-1, edc_route_string); 1382 cur_reg_start = i; 1383 } 1384 } 1385 knl_show_edc_route(edc_route_reg[i-1], edc_route_string); 1386 if (cur_reg_start == i-1) 1387 edac_dbg(0, "edc route table for CHA %d: %s\n", 1388 cur_reg_start, edc_route_string); 1389 else 1390 edac_dbg(0, "edc route table for CHA %d-%d: %s\n", 1391 cur_reg_start, i-1, edc_route_string); 1392 1393 /* Read the MC route table in each CHA. */ 1394 cur_reg_start = 0; 1395 for (i = 0; i < KNL_MAX_CHAS; i++) { 1396 pci_read_config_dword(pvt->knl.pci_cha[i], 1397 KNL_MC_ROUTE, &mc_route_reg[i]); 1398 1399 if (i > 0 && mc_route_reg[i] != mc_route_reg[i-1]) { 1400 knl_show_mc_route(mc_route_reg[i-1], mc_route_string); 1401 if (cur_reg_start == i-1) 1402 edac_dbg(0, "mc route table for CHA %d: %s\n", 1403 cur_reg_start, mc_route_string); 1404 else 1405 edac_dbg(0, "mc route table for CHA %d-%d: %s\n", 1406 cur_reg_start, i-1, mc_route_string); 1407 cur_reg_start = i; 1408 } 1409 } 1410 knl_show_mc_route(mc_route_reg[i-1], mc_route_string); 1411 if (cur_reg_start == i-1) 1412 edac_dbg(0, "mc route table for CHA %d: %s\n", 1413 cur_reg_start, mc_route_string); 1414 else 1415 edac_dbg(0, "mc route table for CHA %d-%d: %s\n", 1416 cur_reg_start, i-1, mc_route_string); 1417 1418 /* Process DRAM rules */ 1419 for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) { 1420 /* previous limit becomes the new base */ 1421 sad_base = sad_limit; 1422 1423 pci_read_config_dword(pvt->pci_sad0, 1424 pvt->info.dram_rule[sad_rule], &dram_rule); 1425 1426 if (!DRAM_RULE_ENABLE(dram_rule)) 1427 break; 1428 1429 edram_only = KNL_EDRAM_ONLY(dram_rule); 1430 1431 sad_limit = pvt->info.sad_limit(dram_rule)+1; 1432 1433 pci_read_config_dword(pvt->pci_sad0, 1434 pvt->info.interleave_list[sad_rule], &interleave_reg); 1435 1436 /* 1437 * Find out how many ways this dram rule is interleaved. 1438 * We stop when we see the first channel again. 1439 */ 1440 first_pkg = sad_pkg(pvt->info.interleave_pkg, 1441 interleave_reg, 0); 1442 for (intrlv_ways = 1; intrlv_ways < 8; intrlv_ways++) { 1443 pkg = sad_pkg(pvt->info.interleave_pkg, 1444 interleave_reg, intrlv_ways); 1445 1446 if ((pkg & 0x8) == 0) { 1447 /* 1448 * 0 bit means memory is non-local, 1449 * which KNL doesn't support 1450 */ 1451 edac_dbg(0, "Unexpected interleave target %d\n", 1452 pkg); 1453 return -1; 1454 } 1455 1456 if (pkg == first_pkg) 1457 break; 1458 } 1459 if (KNL_MOD3(dram_rule)) 1460 intrlv_ways *= 3; 1461 1462 edac_dbg(3, "dram rule %d (base 0x%llx, limit 0x%llx), %d way interleave%s\n", 1463 sad_rule, 1464 sad_base, 1465 sad_limit, 1466 intrlv_ways, 1467 edram_only ? ", EDRAM" : ""); 1468 1469 /* 1470 * Find out how big the SAD region really is by iterating 1471 * over TAD tables (SAD regions may contain holes). 1472 * Each memory controller might have a different TAD table, so 1473 * we have to look at both. 1474 * 1475 * Livespace is the memory that's mapped in this TAD table, 1476 * deadspace is the holes (this could be the MMIO hole, or it 1477 * could be memory that's mapped by the other TAD table but 1478 * not this one). 1479 */ 1480 for (mc = 0; mc < 2; mc++) { 1481 sad_actual_size[mc] = 0; 1482 tad_livespace = 0; 1483 for (tad_rule = 0; 1484 tad_rule < ARRAY_SIZE( 1485 knl_tad_dram_limit_lo); 1486 tad_rule++) { 1487 if (knl_get_tad(pvt, 1488 tad_rule, 1489 mc, 1490 &tad_deadspace, 1491 &tad_limit, 1492 &tad_ways)) 1493 break; 1494 1495 tad_size = (tad_limit+1) - 1496 (tad_livespace + tad_deadspace); 1497 tad_livespace += tad_size; 1498 tad_base = (tad_limit+1) - tad_size; 1499 1500 if (tad_base < sad_base) { 1501 if (tad_limit > sad_base) 1502 edac_dbg(0, "TAD region overlaps lower SAD boundary -- TAD tables may be configured incorrectly.\n"); 1503 } else if (tad_base < sad_limit) { 1504 if (tad_limit+1 > sad_limit) { 1505 edac_dbg(0, "TAD region overlaps upper SAD boundary -- TAD tables may be configured incorrectly.\n"); 1506 } else { 1507 /* TAD region is completely inside SAD region */ 1508 edac_dbg(3, "TAD region %d 0x%llx - 0x%llx (%lld bytes) table%d\n", 1509 tad_rule, tad_base, 1510 tad_limit, tad_size, 1511 mc); 1512 sad_actual_size[mc] += tad_size; 1513 } 1514 } 1515 } 1516 } 1517 1518 for (mc = 0; mc < 2; mc++) { 1519 edac_dbg(3, " total TAD DRAM footprint in table%d : 0x%llx (%lld bytes)\n", 1520 mc, sad_actual_size[mc], sad_actual_size[mc]); 1521 } 1522 1523 /* Ignore EDRAM rule */ 1524 if (edram_only) 1525 continue; 1526 1527 /* Figure out which channels participate in interleave. */ 1528 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) 1529 participants[channel] = 0; 1530 1531 /* For each channel, does at least one CHA have 1532 * this channel mapped to the given target? 1533 */ 1534 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) { 1535 int target; 1536 int cha; 1537 1538 for (target = 0; target < KNL_MAX_CHANNELS; target++) { 1539 for (cha = 0; cha < KNL_MAX_CHAS; cha++) { 1540 if (knl_get_mc_route(target, 1541 mc_route_reg[cha]) == channel 1542 && !participants[channel]) { 1543 participants[channel] = 1; 1544 break; 1545 } 1546 } 1547 } 1548 } 1549 1550 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) { 1551 mc = knl_channel_mc(channel); 1552 if (participants[channel]) { 1553 edac_dbg(4, "mc channel %d contributes %lld bytes via sad entry %d\n", 1554 channel, 1555 sad_actual_size[mc]/intrlv_ways, 1556 sad_rule); 1557 mc_sizes[channel] += 1558 sad_actual_size[mc]/intrlv_ways; 1559 } 1560 } 1561 } 1562 1563 return 0; 1564 } 1565 1566 static void get_source_id(struct mem_ctl_info *mci) 1567 { 1568 struct sbridge_pvt *pvt = mci->pvt_info; 1569 u32 reg; 1570 1571 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL || 1572 pvt->info.type == KNIGHTS_LANDING) 1573 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®); 1574 else 1575 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®); 1576 1577 if (pvt->info.type == KNIGHTS_LANDING) 1578 pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg); 1579 else 1580 pvt->sbridge_dev->source_id = SOURCE_ID(reg); 1581 } 1582 1583 static int __populate_dimms(struct mem_ctl_info *mci, 1584 u64 knl_mc_sizes[KNL_MAX_CHANNELS], 1585 enum edac_type mode) 1586 { 1587 struct sbridge_pvt *pvt = mci->pvt_info; 1588 int channels = pvt->info.type == KNIGHTS_LANDING ? KNL_MAX_CHANNELS 1589 : NUM_CHANNELS; 1590 unsigned int i, j, banks, ranks, rows, cols, npages; 1591 struct dimm_info *dimm; 1592 enum mem_type mtype; 1593 u64 size; 1594 1595 mtype = pvt->info.get_memory_type(pvt); 1596 if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4) 1597 edac_dbg(0, "Memory is registered\n"); 1598 else if (mtype == MEM_UNKNOWN) 1599 edac_dbg(0, "Cannot determine memory type\n"); 1600 else 1601 edac_dbg(0, "Memory is unregistered\n"); 1602 1603 if (mtype == MEM_DDR4 || mtype == MEM_RDDR4) 1604 banks = 16; 1605 else 1606 banks = 8; 1607 1608 for (i = 0; i < channels; i++) { 1609 u32 mtr; 1610 1611 int max_dimms_per_channel; 1612 1613 if (pvt->info.type == KNIGHTS_LANDING) { 1614 max_dimms_per_channel = 1; 1615 if (!pvt->knl.pci_channel[i]) 1616 continue; 1617 } else { 1618 max_dimms_per_channel = ARRAY_SIZE(mtr_regs); 1619 if (!pvt->pci_tad[i]) 1620 continue; 1621 } 1622 1623 for (j = 0; j < max_dimms_per_channel; j++) { 1624 dimm = edac_get_dimm(mci, i, j, 0); 1625 if (pvt->info.type == KNIGHTS_LANDING) { 1626 pci_read_config_dword(pvt->knl.pci_channel[i], 1627 knl_mtr_reg, &mtr); 1628 } else { 1629 pci_read_config_dword(pvt->pci_tad[i], 1630 mtr_regs[j], &mtr); 1631 } 1632 edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr); 1633 if (IS_DIMM_PRESENT(mtr)) { 1634 if (!IS_ECC_ENABLED(pvt->info.mcmtr)) { 1635 sbridge_printk(KERN_ERR, "CPU SrcID #%d, Ha #%d, Channel #%d has DIMMs, but ECC is disabled\n", 1636 pvt->sbridge_dev->source_id, 1637 pvt->sbridge_dev->dom, i); 1638 return -ENODEV; 1639 } 1640 pvt->channel[i].dimms++; 1641 1642 ranks = numrank(pvt->info.type, mtr); 1643 1644 if (pvt->info.type == KNIGHTS_LANDING) { 1645 /* For DDR4, this is fixed. */ 1646 cols = 1 << 10; 1647 rows = knl_mc_sizes[i] / 1648 ((u64) cols * ranks * banks * 8); 1649 } else { 1650 rows = numrow(mtr); 1651 cols = numcol(mtr); 1652 } 1653 1654 size = ((u64)rows * cols * banks * ranks) >> (20 - 3); 1655 npages = MiB_TO_PAGES(size); 1656 1657 edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n", 1658 pvt->sbridge_dev->mc, pvt->sbridge_dev->dom, i, j, 1659 size, npages, 1660 banks, ranks, rows, cols); 1661 1662 dimm->nr_pages = npages; 1663 dimm->grain = 32; 1664 dimm->dtype = pvt->info.get_width(pvt, mtr); 1665 dimm->mtype = mtype; 1666 dimm->edac_mode = mode; 1667 snprintf(dimm->label, sizeof(dimm->label), 1668 "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u", 1669 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom, i, j); 1670 } 1671 } 1672 } 1673 1674 return 0; 1675 } 1676 1677 static int get_dimm_config(struct mem_ctl_info *mci) 1678 { 1679 struct sbridge_pvt *pvt = mci->pvt_info; 1680 u64 knl_mc_sizes[KNL_MAX_CHANNELS]; 1681 enum edac_type mode; 1682 u32 reg; 1683 1684 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt); 1685 edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n", 1686 pvt->sbridge_dev->mc, 1687 pvt->sbridge_dev->node_id, 1688 pvt->sbridge_dev->source_id); 1689 1690 /* KNL doesn't support mirroring or lockstep, 1691 * and is always closed page 1692 */ 1693 if (pvt->info.type == KNIGHTS_LANDING) { 1694 mode = EDAC_S4ECD4ED; 1695 pvt->mirror_mode = NON_MIRRORING; 1696 pvt->is_cur_addr_mirrored = false; 1697 1698 if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0) 1699 return -1; 1700 if (pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr)) { 1701 edac_dbg(0, "Failed to read KNL_MCMTR register\n"); 1702 return -ENODEV; 1703 } 1704 } else { 1705 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { 1706 if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®)) { 1707 edac_dbg(0, "Failed to read HASWELL_HASYSDEFEATURE2 register\n"); 1708 return -ENODEV; 1709 } 1710 pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21); 1711 if (GET_BITFIELD(reg, 28, 28)) { 1712 pvt->mirror_mode = ADDR_RANGE_MIRRORING; 1713 edac_dbg(0, "Address range partial memory mirroring is enabled\n"); 1714 goto next; 1715 } 1716 } 1717 if (pci_read_config_dword(pvt->pci_ras, RASENABLES, ®)) { 1718 edac_dbg(0, "Failed to read RASENABLES register\n"); 1719 return -ENODEV; 1720 } 1721 if (IS_MIRROR_ENABLED(reg)) { 1722 pvt->mirror_mode = FULL_MIRRORING; 1723 edac_dbg(0, "Full memory mirroring is enabled\n"); 1724 } else { 1725 pvt->mirror_mode = NON_MIRRORING; 1726 edac_dbg(0, "Memory mirroring is disabled\n"); 1727 } 1728 1729 next: 1730 if (pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr)) { 1731 edac_dbg(0, "Failed to read MCMTR register\n"); 1732 return -ENODEV; 1733 } 1734 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { 1735 edac_dbg(0, "Lockstep is enabled\n"); 1736 mode = EDAC_S8ECD8ED; 1737 pvt->is_lockstep = true; 1738 } else { 1739 edac_dbg(0, "Lockstep is disabled\n"); 1740 mode = EDAC_S4ECD4ED; 1741 pvt->is_lockstep = false; 1742 } 1743 if (IS_CLOSE_PG(pvt->info.mcmtr)) { 1744 edac_dbg(0, "address map is on closed page mode\n"); 1745 pvt->is_close_pg = true; 1746 } else { 1747 edac_dbg(0, "address map is on open page mode\n"); 1748 pvt->is_close_pg = false; 1749 } 1750 } 1751 1752 return __populate_dimms(mci, knl_mc_sizes, mode); 1753 } 1754 1755 static void get_memory_layout(const struct mem_ctl_info *mci) 1756 { 1757 struct sbridge_pvt *pvt = mci->pvt_info; 1758 int i, j, k, n_sads, n_tads, sad_interl; 1759 u32 reg; 1760 u64 limit, prv = 0; 1761 u64 tmp_mb; 1762 u32 gb, mb; 1763 u32 rir_way; 1764 1765 /* 1766 * Step 1) Get TOLM/TOHM ranges 1767 */ 1768 1769 pvt->tolm = pvt->info.get_tolm(pvt); 1770 tmp_mb = (1 + pvt->tolm) >> 20; 1771 1772 gb = div_u64_rem(tmp_mb, 1024, &mb); 1773 edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n", 1774 gb, (mb*1000)/1024, (u64)pvt->tolm); 1775 1776 /* Address range is already 45:25 */ 1777 pvt->tohm = pvt->info.get_tohm(pvt); 1778 tmp_mb = (1 + pvt->tohm) >> 20; 1779 1780 gb = div_u64_rem(tmp_mb, 1024, &mb); 1781 edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n", 1782 gb, (mb*1000)/1024, (u64)pvt->tohm); 1783 1784 /* 1785 * Step 2) Get SAD range and SAD Interleave list 1786 * TAD registers contain the interleave wayness. However, it 1787 * seems simpler to just discover it indirectly, with the 1788 * algorithm bellow. 1789 */ 1790 prv = 0; 1791 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { 1792 /* SAD_LIMIT Address range is 45:26 */ 1793 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], 1794 ®); 1795 limit = pvt->info.sad_limit(reg); 1796 1797 if (!DRAM_RULE_ENABLE(reg)) 1798 continue; 1799 1800 if (limit <= prv) 1801 break; 1802 1803 tmp_mb = (limit + 1) >> 20; 1804 gb = div_u64_rem(tmp_mb, 1024, &mb); 1805 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n", 1806 n_sads, 1807 show_dram_attr(pvt->info.dram_attr(reg)), 1808 gb, (mb*1000)/1024, 1809 ((u64)tmp_mb) << 20L, 1810 get_intlv_mode_str(reg, pvt->info.type), 1811 reg); 1812 prv = limit; 1813 1814 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], 1815 ®); 1816 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); 1817 for (j = 0; j < 8; j++) { 1818 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j); 1819 if (j > 0 && sad_interl == pkg) 1820 break; 1821 1822 edac_dbg(0, "SAD#%d, interleave #%d: %d\n", 1823 n_sads, j, pkg); 1824 } 1825 } 1826 1827 if (pvt->info.type == KNIGHTS_LANDING) 1828 return; 1829 1830 /* 1831 * Step 3) Get TAD range 1832 */ 1833 prv = 0; 1834 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { 1835 pci_read_config_dword(pvt->pci_ha, tad_dram_rule[n_tads], ®); 1836 limit = TAD_LIMIT(reg); 1837 if (limit <= prv) 1838 break; 1839 tmp_mb = (limit + 1) >> 20; 1840 1841 gb = div_u64_rem(tmp_mb, 1024, &mb); 1842 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n", 1843 n_tads, gb, (mb*1000)/1024, 1844 ((u64)tmp_mb) << 20L, 1845 (u32)(1 << TAD_SOCK(reg)), 1846 (u32)TAD_CH(reg) + 1, 1847 (u32)TAD_TGT0(reg), 1848 (u32)TAD_TGT1(reg), 1849 (u32)TAD_TGT2(reg), 1850 (u32)TAD_TGT3(reg), 1851 reg); 1852 prv = limit; 1853 } 1854 1855 /* 1856 * Step 4) Get TAD offsets, per each channel 1857 */ 1858 for (i = 0; i < NUM_CHANNELS; i++) { 1859 if (!pvt->channel[i].dimms) 1860 continue; 1861 for (j = 0; j < n_tads; j++) { 1862 pci_read_config_dword(pvt->pci_tad[i], 1863 tad_ch_nilv_offset[j], 1864 ®); 1865 tmp_mb = TAD_OFFSET(reg) >> 20; 1866 gb = div_u64_rem(tmp_mb, 1024, &mb); 1867 edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n", 1868 i, j, 1869 gb, (mb*1000)/1024, 1870 ((u64)tmp_mb) << 20L, 1871 reg); 1872 } 1873 } 1874 1875 /* 1876 * Step 6) Get RIR Wayness/Limit, per each channel 1877 */ 1878 for (i = 0; i < NUM_CHANNELS; i++) { 1879 if (!pvt->channel[i].dimms) 1880 continue; 1881 for (j = 0; j < MAX_RIR_RANGES; j++) { 1882 pci_read_config_dword(pvt->pci_tad[i], 1883 rir_way_limit[j], 1884 ®); 1885 1886 if (!IS_RIR_VALID(reg)) 1887 continue; 1888 1889 tmp_mb = pvt->info.rir_limit(reg) >> 20; 1890 rir_way = 1 << RIR_WAY(reg); 1891 gb = div_u64_rem(tmp_mb, 1024, &mb); 1892 edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n", 1893 i, j, 1894 gb, (mb*1000)/1024, 1895 ((u64)tmp_mb) << 20L, 1896 rir_way, 1897 reg); 1898 1899 for (k = 0; k < rir_way; k++) { 1900 pci_read_config_dword(pvt->pci_tad[i], 1901 rir_offset[j][k], 1902 ®); 1903 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6; 1904 1905 gb = div_u64_rem(tmp_mb, 1024, &mb); 1906 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n", 1907 i, j, k, 1908 gb, (mb*1000)/1024, 1909 ((u64)tmp_mb) << 20L, 1910 (u32)RIR_RNK_TGT(pvt->info.type, reg), 1911 reg); 1912 } 1913 } 1914 } 1915 } 1916 1917 static struct mem_ctl_info *get_mci_for_node_id(u8 node_id, u8 ha) 1918 { 1919 struct sbridge_dev *sbridge_dev; 1920 1921 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { 1922 if (sbridge_dev->node_id == node_id && sbridge_dev->dom == ha) 1923 return sbridge_dev->mci; 1924 } 1925 return NULL; 1926 } 1927 1928 static int get_memory_error_data(struct mem_ctl_info *mci, 1929 u64 addr, 1930 u8 *socket, u8 *ha, 1931 long *channel_mask, 1932 u8 *rank, 1933 char **area_type, char *msg) 1934 { 1935 struct mem_ctl_info *new_mci; 1936 struct sbridge_pvt *pvt = mci->pvt_info; 1937 struct pci_dev *pci_ha; 1938 int n_rir, n_sads, n_tads, sad_way, sck_xch; 1939 int sad_interl, idx, base_ch; 1940 int interleave_mode, shiftup = 0; 1941 unsigned int sad_interleave[MAX_INTERLEAVE]; 1942 u32 reg, dram_rule; 1943 u8 ch_way, sck_way, pkg, sad_ha = 0; 1944 u32 tad_offset; 1945 u32 rir_way; 1946 u32 mb, gb; 1947 u64 ch_addr, offset, limit = 0, prv = 0; 1948 1949 1950 /* 1951 * Step 0) Check if the address is at special memory ranges 1952 * The check bellow is probably enough to fill all cases where 1953 * the error is not inside a memory, except for the legacy 1954 * range (e. g. VGA addresses). It is unlikely, however, that the 1955 * memory controller would generate an error on that range. 1956 */ 1957 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) { 1958 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr); 1959 return -EINVAL; 1960 } 1961 if (addr >= (u64)pvt->tohm) { 1962 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr); 1963 return -EINVAL; 1964 } 1965 1966 /* 1967 * Step 1) Get socket 1968 */ 1969 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { 1970 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], 1971 ®); 1972 1973 if (!DRAM_RULE_ENABLE(reg)) 1974 continue; 1975 1976 limit = pvt->info.sad_limit(reg); 1977 if (limit <= prv) { 1978 sprintf(msg, "Can't discover the memory socket"); 1979 return -EINVAL; 1980 } 1981 if (addr <= limit) 1982 break; 1983 prv = limit; 1984 } 1985 if (n_sads == pvt->info.max_sad) { 1986 sprintf(msg, "Can't discover the memory socket"); 1987 return -EINVAL; 1988 } 1989 dram_rule = reg; 1990 *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule)); 1991 interleave_mode = pvt->info.interleave_mode(dram_rule); 1992 1993 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], 1994 ®); 1995 1996 if (pvt->info.type == SANDY_BRIDGE) { 1997 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); 1998 for (sad_way = 0; sad_way < 8; sad_way++) { 1999 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way); 2000 if (sad_way > 0 && sad_interl == pkg) 2001 break; 2002 sad_interleave[sad_way] = pkg; 2003 edac_dbg(0, "SAD interleave #%d: %d\n", 2004 sad_way, sad_interleave[sad_way]); 2005 } 2006 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n", 2007 pvt->sbridge_dev->mc, 2008 n_sads, 2009 addr, 2010 limit, 2011 sad_way + 7, 2012 !interleave_mode ? "" : "XOR[18:16]"); 2013 if (interleave_mode) 2014 idx = ((addr >> 6) ^ (addr >> 16)) & 7; 2015 else 2016 idx = (addr >> 6) & 7; 2017 switch (sad_way) { 2018 case 1: 2019 idx = 0; 2020 break; 2021 case 2: 2022 idx = idx & 1; 2023 break; 2024 case 4: 2025 idx = idx & 3; 2026 break; 2027 case 8: 2028 break; 2029 default: 2030 sprintf(msg, "Can't discover socket interleave"); 2031 return -EINVAL; 2032 } 2033 *socket = sad_interleave[idx]; 2034 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n", 2035 idx, sad_way, *socket); 2036 } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { 2037 int bits, a7mode = A7MODE(dram_rule); 2038 2039 if (a7mode) { 2040 /* A7 mode swaps P9 with P6 */ 2041 bits = GET_BITFIELD(addr, 7, 8) << 1; 2042 bits |= GET_BITFIELD(addr, 9, 9); 2043 } else 2044 bits = GET_BITFIELD(addr, 6, 8); 2045 2046 if (interleave_mode == 0) { 2047 /* interleave mode will XOR {8,7,6} with {18,17,16} */ 2048 idx = GET_BITFIELD(addr, 16, 18); 2049 idx ^= bits; 2050 } else 2051 idx = bits; 2052 2053 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); 2054 *socket = sad_pkg_socket(pkg); 2055 sad_ha = sad_pkg_ha(pkg); 2056 2057 if (a7mode) { 2058 /* MCChanShiftUpEnable */ 2059 pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®); 2060 shiftup = GET_BITFIELD(reg, 22, 22); 2061 } 2062 2063 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n", 2064 idx, *socket, sad_ha, shiftup); 2065 } else { 2066 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */ 2067 idx = (addr >> 6) & 7; 2068 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); 2069 *socket = sad_pkg_socket(pkg); 2070 sad_ha = sad_pkg_ha(pkg); 2071 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n", 2072 idx, *socket, sad_ha); 2073 } 2074 2075 *ha = sad_ha; 2076 2077 /* 2078 * Move to the proper node structure, in order to access the 2079 * right PCI registers 2080 */ 2081 new_mci = get_mci_for_node_id(*socket, sad_ha); 2082 if (!new_mci) { 2083 sprintf(msg, "Struct for socket #%u wasn't initialized", 2084 *socket); 2085 return -EINVAL; 2086 } 2087 mci = new_mci; 2088 pvt = mci->pvt_info; 2089 2090 /* 2091 * Step 2) Get memory channel 2092 */ 2093 prv = 0; 2094 pci_ha = pvt->pci_ha; 2095 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { 2096 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], ®); 2097 limit = TAD_LIMIT(reg); 2098 if (limit <= prv) { 2099 sprintf(msg, "Can't discover the memory channel"); 2100 return -EINVAL; 2101 } 2102 if (addr <= limit) 2103 break; 2104 prv = limit; 2105 } 2106 if (n_tads == MAX_TAD) { 2107 sprintf(msg, "Can't discover the memory channel"); 2108 return -EINVAL; 2109 } 2110 2111 ch_way = TAD_CH(reg) + 1; 2112 sck_way = TAD_SOCK(reg); 2113 2114 if (ch_way == 3) 2115 idx = addr >> 6; 2116 else { 2117 idx = (addr >> (6 + sck_way + shiftup)) & 0x3; 2118 if (pvt->is_chan_hash) 2119 idx = haswell_chan_hash(idx, addr); 2120 } 2121 idx = idx % ch_way; 2122 2123 /* 2124 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ??? 2125 */ 2126 switch (idx) { 2127 case 0: 2128 base_ch = TAD_TGT0(reg); 2129 break; 2130 case 1: 2131 base_ch = TAD_TGT1(reg); 2132 break; 2133 case 2: 2134 base_ch = TAD_TGT2(reg); 2135 break; 2136 case 3: 2137 base_ch = TAD_TGT3(reg); 2138 break; 2139 default: 2140 sprintf(msg, "Can't discover the TAD target"); 2141 return -EINVAL; 2142 } 2143 *channel_mask = 1 << base_ch; 2144 2145 pci_read_config_dword(pvt->pci_tad[base_ch], tad_ch_nilv_offset[n_tads], &tad_offset); 2146 2147 if (pvt->mirror_mode == FULL_MIRRORING || 2148 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && n_tads == 0)) { 2149 *channel_mask |= 1 << ((base_ch + 2) % 4); 2150 switch(ch_way) { 2151 case 2: 2152 case 4: 2153 sck_xch = (1 << sck_way) * (ch_way >> 1); 2154 break; 2155 default: 2156 sprintf(msg, "Invalid mirror set. Can't decode addr"); 2157 return -EINVAL; 2158 } 2159 2160 pvt->is_cur_addr_mirrored = true; 2161 } else { 2162 sck_xch = (1 << sck_way) * ch_way; 2163 pvt->is_cur_addr_mirrored = false; 2164 } 2165 2166 if (pvt->is_lockstep) 2167 *channel_mask |= 1 << ((base_ch + 1) % 4); 2168 2169 offset = TAD_OFFSET(tad_offset); 2170 2171 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n", 2172 n_tads, 2173 addr, 2174 limit, 2175 sck_way, 2176 ch_way, 2177 offset, 2178 idx, 2179 base_ch, 2180 *channel_mask); 2181 2182 /* Calculate channel address */ 2183 /* Remove the TAD offset */ 2184 2185 if (offset > addr) { 2186 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!", 2187 offset, addr); 2188 return -EINVAL; 2189 } 2190 2191 ch_addr = addr - offset; 2192 ch_addr >>= (6 + shiftup); 2193 ch_addr /= sck_xch; 2194 ch_addr <<= (6 + shiftup); 2195 ch_addr |= addr & ((1 << (6 + shiftup)) - 1); 2196 2197 /* 2198 * Step 3) Decode rank 2199 */ 2200 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) { 2201 pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], ®); 2202 2203 if (!IS_RIR_VALID(reg)) 2204 continue; 2205 2206 limit = pvt->info.rir_limit(reg); 2207 gb = div_u64_rem(limit >> 20, 1024, &mb); 2208 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n", 2209 n_rir, 2210 gb, (mb*1000)/1024, 2211 limit, 2212 1 << RIR_WAY(reg)); 2213 if (ch_addr <= limit) 2214 break; 2215 } 2216 if (n_rir == MAX_RIR_RANGES) { 2217 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx", 2218 ch_addr); 2219 return -EINVAL; 2220 } 2221 rir_way = RIR_WAY(reg); 2222 2223 if (pvt->is_close_pg) 2224 idx = (ch_addr >> 6); 2225 else 2226 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */ 2227 idx %= 1 << rir_way; 2228 2229 pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], ®); 2230 *rank = RIR_RNK_TGT(pvt->info.type, reg); 2231 2232 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", 2233 n_rir, 2234 ch_addr, 2235 limit, 2236 rir_way, 2237 idx); 2238 2239 return 0; 2240 } 2241 2242 static int get_memory_error_data_from_mce(struct mem_ctl_info *mci, 2243 const struct mce *m, u8 *socket, 2244 u8 *ha, long *channel_mask, 2245 char *msg) 2246 { 2247 u32 reg, channel = GET_BITFIELD(m->status, 0, 3); 2248 struct mem_ctl_info *new_mci; 2249 struct sbridge_pvt *pvt; 2250 struct pci_dev *pci_ha; 2251 bool tad0; 2252 2253 if (channel >= NUM_CHANNELS) { 2254 sprintf(msg, "Invalid channel 0x%x", channel); 2255 return -EINVAL; 2256 } 2257 2258 pvt = mci->pvt_info; 2259 if (!pvt->info.get_ha) { 2260 sprintf(msg, "No get_ha()"); 2261 return -EINVAL; 2262 } 2263 *ha = pvt->info.get_ha(m->bank); 2264 if (*ha != 0 && *ha != 1) { 2265 sprintf(msg, "Impossible bank %d", m->bank); 2266 return -EINVAL; 2267 } 2268 2269 *socket = m->socketid; 2270 new_mci = get_mci_for_node_id(*socket, *ha); 2271 if (!new_mci) { 2272 strcpy(msg, "mci socket got corrupted!"); 2273 return -EINVAL; 2274 } 2275 2276 pvt = new_mci->pvt_info; 2277 pci_ha = pvt->pci_ha; 2278 pci_read_config_dword(pci_ha, tad_dram_rule[0], ®); 2279 tad0 = m->addr <= TAD_LIMIT(reg); 2280 2281 *channel_mask = 1 << channel; 2282 if (pvt->mirror_mode == FULL_MIRRORING || 2283 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && tad0)) { 2284 *channel_mask |= 1 << ((channel + 2) % 4); 2285 pvt->is_cur_addr_mirrored = true; 2286 } else { 2287 pvt->is_cur_addr_mirrored = false; 2288 } 2289 2290 if (pvt->is_lockstep) 2291 *channel_mask |= 1 << ((channel + 1) % 4); 2292 2293 return 0; 2294 } 2295 2296 /**************************************************************************** 2297 Device initialization routines: put/get, init/exit 2298 ****************************************************************************/ 2299 2300 /* 2301 * sbridge_put_all_devices 'put' all the devices that we have 2302 * reserved via 'get' 2303 */ 2304 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev) 2305 { 2306 int i; 2307 2308 edac_dbg(0, "\n"); 2309 for (i = 0; i < sbridge_dev->n_devs; i++) { 2310 struct pci_dev *pdev = sbridge_dev->pdev[i]; 2311 if (!pdev) 2312 continue; 2313 edac_dbg(0, "Removing dev %02x:%02x.%d\n", 2314 pdev->bus->number, 2315 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 2316 pci_dev_put(pdev); 2317 } 2318 } 2319 2320 static void sbridge_put_all_devices(void) 2321 { 2322 struct sbridge_dev *sbridge_dev, *tmp; 2323 2324 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) { 2325 sbridge_put_devices(sbridge_dev); 2326 free_sbridge_dev(sbridge_dev); 2327 } 2328 } 2329 2330 static int sbridge_get_onedevice(struct pci_dev **prev, 2331 u8 *num_mc, 2332 const struct pci_id_table *table, 2333 const unsigned devno, 2334 const int multi_bus) 2335 { 2336 struct sbridge_dev *sbridge_dev = NULL; 2337 const struct pci_id_descr *dev_descr = &table->descr[devno]; 2338 struct pci_dev *pdev = NULL; 2339 int seg = 0; 2340 u8 bus = 0; 2341 int i = 0; 2342 2343 sbridge_printk(KERN_DEBUG, 2344 "Seeking for: PCI ID %04x:%04x\n", 2345 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 2346 2347 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 2348 dev_descr->dev_id, *prev); 2349 2350 if (!pdev) { 2351 if (*prev) { 2352 *prev = pdev; 2353 return 0; 2354 } 2355 2356 if (dev_descr->optional) 2357 return 0; 2358 2359 /* if the HA wasn't found */ 2360 if (devno == 0) 2361 return -ENODEV; 2362 2363 sbridge_printk(KERN_INFO, 2364 "Device not found: %04x:%04x\n", 2365 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 2366 2367 /* End of list, leave */ 2368 return -ENODEV; 2369 } 2370 seg = pci_domain_nr(pdev->bus); 2371 bus = pdev->bus->number; 2372 2373 next_imc: 2374 sbridge_dev = get_sbridge_dev(seg, bus, dev_descr->dom, 2375 multi_bus, sbridge_dev); 2376 if (!sbridge_dev) { 2377 /* If the HA1 wasn't found, don't create EDAC second memory controller */ 2378 if (dev_descr->dom == IMC1 && devno != 1) { 2379 edac_dbg(0, "Skip IMC1: %04x:%04x (since HA1 was absent)\n", 2380 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 2381 pci_dev_put(pdev); 2382 return 0; 2383 } 2384 2385 if (dev_descr->dom == SOCK) 2386 goto out_imc; 2387 2388 sbridge_dev = alloc_sbridge_dev(seg, bus, dev_descr->dom, table); 2389 if (!sbridge_dev) { 2390 pci_dev_put(pdev); 2391 return -ENOMEM; 2392 } 2393 (*num_mc)++; 2394 } 2395 2396 if (sbridge_dev->pdev[sbridge_dev->i_devs]) { 2397 sbridge_printk(KERN_ERR, 2398 "Duplicated device for %04x:%04x\n", 2399 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 2400 pci_dev_put(pdev); 2401 return -ENODEV; 2402 } 2403 2404 sbridge_dev->pdev[sbridge_dev->i_devs++] = pdev; 2405 2406 /* pdev belongs to more than one IMC, do extra gets */ 2407 if (++i > 1) 2408 pci_dev_get(pdev); 2409 2410 if (dev_descr->dom == SOCK && i < table->n_imcs_per_sock) 2411 goto next_imc; 2412 2413 out_imc: 2414 /* Be sure that the device is enabled */ 2415 if (unlikely(pci_enable_device(pdev) < 0)) { 2416 sbridge_printk(KERN_ERR, 2417 "Couldn't enable %04x:%04x\n", 2418 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 2419 return -ENODEV; 2420 } 2421 2422 edac_dbg(0, "Detected %04x:%04x\n", 2423 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 2424 2425 /* 2426 * As stated on drivers/pci/search.c, the reference count for 2427 * @from is always decremented if it is not %NULL. So, as we need 2428 * to get all devices up to null, we need to do a get for the device 2429 */ 2430 pci_dev_get(pdev); 2431 2432 *prev = pdev; 2433 2434 return 0; 2435 } 2436 2437 /* 2438 * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's 2439 * devices we want to reference for this driver. 2440 * @num_mc: pointer to the memory controllers count, to be incremented in case 2441 * of success. 2442 * @table: model specific table 2443 * 2444 * returns 0 in case of success or error code 2445 */ 2446 static int sbridge_get_all_devices(u8 *num_mc, 2447 const struct pci_id_table *table) 2448 { 2449 int i, rc; 2450 struct pci_dev *pdev = NULL; 2451 int allow_dups = 0; 2452 int multi_bus = 0; 2453 2454 if (table->type == KNIGHTS_LANDING) 2455 allow_dups = multi_bus = 1; 2456 while (table && table->descr) { 2457 for (i = 0; i < table->n_devs_per_sock; i++) { 2458 if (!allow_dups || i == 0 || 2459 table->descr[i].dev_id != 2460 table->descr[i-1].dev_id) { 2461 pdev = NULL; 2462 } 2463 do { 2464 rc = sbridge_get_onedevice(&pdev, num_mc, 2465 table, i, multi_bus); 2466 if (rc < 0) { 2467 if (i == 0) { 2468 i = table->n_devs_per_sock; 2469 break; 2470 } 2471 sbridge_put_all_devices(); 2472 return -ENODEV; 2473 } 2474 } while (pdev && !allow_dups); 2475 } 2476 table++; 2477 } 2478 2479 return 0; 2480 } 2481 2482 /* 2483 * Device IDs for {SBRIDGE,IBRIDGE,HASWELL,BROADWELL}_IMC_HA0_TAD0 are in 2484 * the format: XXXa. So we can convert from a device to the corresponding 2485 * channel like this 2486 */ 2487 #define TAD_DEV_TO_CHAN(dev) (((dev) & 0xf) - 0xa) 2488 2489 static int sbridge_mci_bind_devs(struct mem_ctl_info *mci, 2490 struct sbridge_dev *sbridge_dev) 2491 { 2492 struct sbridge_pvt *pvt = mci->pvt_info; 2493 struct pci_dev *pdev; 2494 u8 saw_chan_mask = 0; 2495 int i; 2496 2497 for (i = 0; i < sbridge_dev->n_devs; i++) { 2498 pdev = sbridge_dev->pdev[i]; 2499 if (!pdev) 2500 continue; 2501 2502 switch (pdev->device) { 2503 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0: 2504 pvt->pci_sad0 = pdev; 2505 break; 2506 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1: 2507 pvt->pci_sad1 = pdev; 2508 break; 2509 case PCI_DEVICE_ID_INTEL_SBRIDGE_BR: 2510 pvt->pci_br0 = pdev; 2511 break; 2512 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0: 2513 pvt->pci_ha = pdev; 2514 break; 2515 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA: 2516 pvt->pci_ta = pdev; 2517 break; 2518 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS: 2519 pvt->pci_ras = pdev; 2520 break; 2521 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0: 2522 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1: 2523 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2: 2524 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3: 2525 { 2526 int id = TAD_DEV_TO_CHAN(pdev->device); 2527 pvt->pci_tad[id] = pdev; 2528 saw_chan_mask |= 1 << id; 2529 } 2530 break; 2531 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO: 2532 pvt->pci_ddrio = pdev; 2533 break; 2534 default: 2535 goto error; 2536 } 2537 2538 edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n", 2539 pdev->vendor, pdev->device, 2540 sbridge_dev->bus, 2541 pdev); 2542 } 2543 2544 /* Check if everything were registered */ 2545 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha || 2546 !pvt->pci_ras || !pvt->pci_ta) 2547 goto enodev; 2548 2549 if (saw_chan_mask != 0x0f) 2550 goto enodev; 2551 return 0; 2552 2553 enodev: 2554 sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); 2555 return -ENODEV; 2556 2557 error: 2558 sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n", 2559 PCI_VENDOR_ID_INTEL, pdev->device); 2560 return -EINVAL; 2561 } 2562 2563 static int ibridge_mci_bind_devs(struct mem_ctl_info *mci, 2564 struct sbridge_dev *sbridge_dev) 2565 { 2566 struct sbridge_pvt *pvt = mci->pvt_info; 2567 struct pci_dev *pdev; 2568 u8 saw_chan_mask = 0; 2569 int i; 2570 2571 for (i = 0; i < sbridge_dev->n_devs; i++) { 2572 pdev = sbridge_dev->pdev[i]; 2573 if (!pdev) 2574 continue; 2575 2576 switch (pdev->device) { 2577 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0: 2578 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1: 2579 pvt->pci_ha = pdev; 2580 break; 2581 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA: 2582 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA: 2583 pvt->pci_ta = pdev; 2584 break; 2585 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS: 2586 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS: 2587 pvt->pci_ras = pdev; 2588 break; 2589 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0: 2590 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1: 2591 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2: 2592 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3: 2593 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0: 2594 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1: 2595 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2: 2596 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3: 2597 { 2598 int id = TAD_DEV_TO_CHAN(pdev->device); 2599 pvt->pci_tad[id] = pdev; 2600 saw_chan_mask |= 1 << id; 2601 } 2602 break; 2603 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0: 2604 pvt->pci_ddrio = pdev; 2605 break; 2606 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0: 2607 pvt->pci_ddrio = pdev; 2608 break; 2609 case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD: 2610 pvt->pci_sad0 = pdev; 2611 break; 2612 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0: 2613 pvt->pci_br0 = pdev; 2614 break; 2615 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1: 2616 pvt->pci_br1 = pdev; 2617 break; 2618 default: 2619 goto error; 2620 } 2621 2622 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", 2623 sbridge_dev->bus, 2624 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2625 pdev); 2626 } 2627 2628 /* Check if everything were registered */ 2629 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_br0 || 2630 !pvt->pci_br1 || !pvt->pci_ras || !pvt->pci_ta) 2631 goto enodev; 2632 2633 if (saw_chan_mask != 0x0f && /* -EN/-EX */ 2634 saw_chan_mask != 0x03) /* -EP */ 2635 goto enodev; 2636 return 0; 2637 2638 enodev: 2639 sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); 2640 return -ENODEV; 2641 2642 error: 2643 sbridge_printk(KERN_ERR, 2644 "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL, 2645 pdev->device); 2646 return -EINVAL; 2647 } 2648 2649 static int haswell_mci_bind_devs(struct mem_ctl_info *mci, 2650 struct sbridge_dev *sbridge_dev) 2651 { 2652 struct sbridge_pvt *pvt = mci->pvt_info; 2653 struct pci_dev *pdev; 2654 u8 saw_chan_mask = 0; 2655 int i; 2656 2657 /* there's only one device per system; not tied to any bus */ 2658 if (pvt->info.pci_vtd == NULL) 2659 /* result will be checked later */ 2660 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, 2661 PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC, 2662 NULL); 2663 2664 for (i = 0; i < sbridge_dev->n_devs; i++) { 2665 pdev = sbridge_dev->pdev[i]; 2666 if (!pdev) 2667 continue; 2668 2669 switch (pdev->device) { 2670 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0: 2671 pvt->pci_sad0 = pdev; 2672 break; 2673 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1: 2674 pvt->pci_sad1 = pdev; 2675 break; 2676 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0: 2677 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1: 2678 pvt->pci_ha = pdev; 2679 break; 2680 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA: 2681 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA: 2682 pvt->pci_ta = pdev; 2683 break; 2684 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM: 2685 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM: 2686 pvt->pci_ras = pdev; 2687 break; 2688 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0: 2689 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1: 2690 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2: 2691 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3: 2692 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0: 2693 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1: 2694 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2: 2695 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3: 2696 { 2697 int id = TAD_DEV_TO_CHAN(pdev->device); 2698 pvt->pci_tad[id] = pdev; 2699 saw_chan_mask |= 1 << id; 2700 } 2701 break; 2702 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0: 2703 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1: 2704 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2: 2705 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3: 2706 if (!pvt->pci_ddrio) 2707 pvt->pci_ddrio = pdev; 2708 break; 2709 default: 2710 break; 2711 } 2712 2713 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", 2714 sbridge_dev->bus, 2715 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2716 pdev); 2717 } 2718 2719 /* Check if everything were registered */ 2720 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 || 2721 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) 2722 goto enodev; 2723 2724 if (saw_chan_mask != 0x0f && /* -EN/-EX */ 2725 saw_chan_mask != 0x03) /* -EP */ 2726 goto enodev; 2727 return 0; 2728 2729 enodev: 2730 sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); 2731 return -ENODEV; 2732 } 2733 2734 static int broadwell_mci_bind_devs(struct mem_ctl_info *mci, 2735 struct sbridge_dev *sbridge_dev) 2736 { 2737 struct sbridge_pvt *pvt = mci->pvt_info; 2738 struct pci_dev *pdev; 2739 u8 saw_chan_mask = 0; 2740 int i; 2741 2742 /* there's only one device per system; not tied to any bus */ 2743 if (pvt->info.pci_vtd == NULL) 2744 /* result will be checked later */ 2745 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, 2746 PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC, 2747 NULL); 2748 2749 for (i = 0; i < sbridge_dev->n_devs; i++) { 2750 pdev = sbridge_dev->pdev[i]; 2751 if (!pdev) 2752 continue; 2753 2754 switch (pdev->device) { 2755 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0: 2756 pvt->pci_sad0 = pdev; 2757 break; 2758 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1: 2759 pvt->pci_sad1 = pdev; 2760 break; 2761 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0: 2762 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1: 2763 pvt->pci_ha = pdev; 2764 break; 2765 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA: 2766 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA: 2767 pvt->pci_ta = pdev; 2768 break; 2769 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM: 2770 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM: 2771 pvt->pci_ras = pdev; 2772 break; 2773 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0: 2774 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1: 2775 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2: 2776 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3: 2777 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0: 2778 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1: 2779 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2: 2780 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3: 2781 { 2782 int id = TAD_DEV_TO_CHAN(pdev->device); 2783 pvt->pci_tad[id] = pdev; 2784 saw_chan_mask |= 1 << id; 2785 } 2786 break; 2787 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0: 2788 pvt->pci_ddrio = pdev; 2789 break; 2790 default: 2791 break; 2792 } 2793 2794 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", 2795 sbridge_dev->bus, 2796 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2797 pdev); 2798 } 2799 2800 /* Check if everything were registered */ 2801 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 || 2802 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) 2803 goto enodev; 2804 2805 if (saw_chan_mask != 0x0f && /* -EN/-EX */ 2806 saw_chan_mask != 0x03) /* -EP */ 2807 goto enodev; 2808 return 0; 2809 2810 enodev: 2811 sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); 2812 return -ENODEV; 2813 } 2814 2815 static int knl_mci_bind_devs(struct mem_ctl_info *mci, 2816 struct sbridge_dev *sbridge_dev) 2817 { 2818 struct sbridge_pvt *pvt = mci->pvt_info; 2819 struct pci_dev *pdev; 2820 int dev, func; 2821 2822 int i; 2823 int devidx; 2824 2825 for (i = 0; i < sbridge_dev->n_devs; i++) { 2826 pdev = sbridge_dev->pdev[i]; 2827 if (!pdev) 2828 continue; 2829 2830 /* Extract PCI device and function. */ 2831 dev = (pdev->devfn >> 3) & 0x1f; 2832 func = pdev->devfn & 0x7; 2833 2834 switch (pdev->device) { 2835 case PCI_DEVICE_ID_INTEL_KNL_IMC_MC: 2836 if (dev == 8) 2837 pvt->knl.pci_mc0 = pdev; 2838 else if (dev == 9) 2839 pvt->knl.pci_mc1 = pdev; 2840 else { 2841 sbridge_printk(KERN_ERR, 2842 "Memory controller in unexpected place! (dev %d, fn %d)\n", 2843 dev, func); 2844 continue; 2845 } 2846 break; 2847 2848 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0: 2849 pvt->pci_sad0 = pdev; 2850 break; 2851 2852 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1: 2853 pvt->pci_sad1 = pdev; 2854 break; 2855 2856 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHA: 2857 /* There are one of these per tile, and range from 2858 * 1.14.0 to 1.18.5. 2859 */ 2860 devidx = ((dev-14)*8)+func; 2861 2862 if (devidx < 0 || devidx >= KNL_MAX_CHAS) { 2863 sbridge_printk(KERN_ERR, 2864 "Caching and Home Agent in unexpected place! (dev %d, fn %d)\n", 2865 dev, func); 2866 continue; 2867 } 2868 2869 WARN_ON(pvt->knl.pci_cha[devidx] != NULL); 2870 2871 pvt->knl.pci_cha[devidx] = pdev; 2872 break; 2873 2874 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN: 2875 devidx = -1; 2876 2877 /* 2878 * MC0 channels 0-2 are device 9 function 2-4, 2879 * MC1 channels 3-5 are device 8 function 2-4. 2880 */ 2881 2882 if (dev == 9) 2883 devidx = func-2; 2884 else if (dev == 8) 2885 devidx = 3 + (func-2); 2886 2887 if (devidx < 0 || devidx >= KNL_MAX_CHANNELS) { 2888 sbridge_printk(KERN_ERR, 2889 "DRAM Channel Registers in unexpected place! (dev %d, fn %d)\n", 2890 dev, func); 2891 continue; 2892 } 2893 2894 WARN_ON(pvt->knl.pci_channel[devidx] != NULL); 2895 pvt->knl.pci_channel[devidx] = pdev; 2896 break; 2897 2898 case PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM: 2899 pvt->knl.pci_mc_info = pdev; 2900 break; 2901 2902 case PCI_DEVICE_ID_INTEL_KNL_IMC_TA: 2903 pvt->pci_ta = pdev; 2904 break; 2905 2906 default: 2907 sbridge_printk(KERN_ERR, "Unexpected device %d\n", 2908 pdev->device); 2909 break; 2910 } 2911 } 2912 2913 if (!pvt->knl.pci_mc0 || !pvt->knl.pci_mc1 || 2914 !pvt->pci_sad0 || !pvt->pci_sad1 || 2915 !pvt->pci_ta) { 2916 goto enodev; 2917 } 2918 2919 for (i = 0; i < KNL_MAX_CHANNELS; i++) { 2920 if (!pvt->knl.pci_channel[i]) { 2921 sbridge_printk(KERN_ERR, "Missing channel %d\n", i); 2922 goto enodev; 2923 } 2924 } 2925 2926 for (i = 0; i < KNL_MAX_CHAS; i++) { 2927 if (!pvt->knl.pci_cha[i]) { 2928 sbridge_printk(KERN_ERR, "Missing CHA %d\n", i); 2929 goto enodev; 2930 } 2931 } 2932 2933 return 0; 2934 2935 enodev: 2936 sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); 2937 return -ENODEV; 2938 } 2939 2940 /**************************************************************************** 2941 Error check routines 2942 ****************************************************************************/ 2943 2944 /* 2945 * While Sandy Bridge has error count registers, SMI BIOS read values from 2946 * and resets the counters. So, they are not reliable for the OS to read 2947 * from them. So, we have no option but to just trust on whatever MCE is 2948 * telling us about the errors. 2949 */ 2950 static void sbridge_mce_output_error(struct mem_ctl_info *mci, 2951 const struct mce *m) 2952 { 2953 struct mem_ctl_info *new_mci; 2954 struct sbridge_pvt *pvt = mci->pvt_info; 2955 enum hw_event_mc_err_type tp_event; 2956 char *optype, msg[256]; 2957 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); 2958 bool overflow = GET_BITFIELD(m->status, 62, 62); 2959 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); 2960 bool recoverable; 2961 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); 2962 u32 mscod = GET_BITFIELD(m->status, 16, 31); 2963 u32 errcode = GET_BITFIELD(m->status, 0, 15); 2964 u32 channel = GET_BITFIELD(m->status, 0, 3); 2965 u32 optypenum = GET_BITFIELD(m->status, 4, 6); 2966 /* 2967 * Bits 5-0 of MCi_MISC give the least significant bit that is valid. 2968 * A value 6 is for cache line aligned address, a value 12 is for page 2969 * aligned address reported by patrol scrubber. 2970 */ 2971 u32 lsb = GET_BITFIELD(m->misc, 0, 5); 2972 long channel_mask, first_channel; 2973 u8 rank = 0xff, socket, ha; 2974 int rc, dimm; 2975 char *area_type = "DRAM"; 2976 2977 if (pvt->info.type != SANDY_BRIDGE) 2978 recoverable = true; 2979 else 2980 recoverable = GET_BITFIELD(m->status, 56, 56); 2981 2982 if (uncorrected_error) { 2983 core_err_cnt = 1; 2984 if (ripv) { 2985 tp_event = HW_EVENT_ERR_FATAL; 2986 } else { 2987 tp_event = HW_EVENT_ERR_UNCORRECTED; 2988 } 2989 } else { 2990 tp_event = HW_EVENT_ERR_CORRECTED; 2991 } 2992 2993 /* 2994 * According with Table 15-9 of the Intel Architecture spec vol 3A, 2995 * memory errors should fit in this mask: 2996 * 000f 0000 1mmm cccc (binary) 2997 * where: 2998 * f = Correction Report Filtering Bit. If 1, subsequent errors 2999 * won't be shown 3000 * mmm = error type 3001 * cccc = channel 3002 * If the mask doesn't match, report an error to the parsing logic 3003 */ 3004 switch (optypenum) { 3005 case 0: 3006 optype = "generic undef request error"; 3007 break; 3008 case 1: 3009 optype = "memory read error"; 3010 break; 3011 case 2: 3012 optype = "memory write error"; 3013 break; 3014 case 3: 3015 optype = "addr/cmd error"; 3016 break; 3017 case 4: 3018 optype = "memory scrubbing error"; 3019 break; 3020 default: 3021 optype = "reserved"; 3022 break; 3023 } 3024 3025 if (pvt->info.type == KNIGHTS_LANDING) { 3026 if (channel == 14) { 3027 edac_dbg(0, "%s%s err_code:%04x:%04x EDRAM bank %d\n", 3028 overflow ? " OVERFLOW" : "", 3029 (uncorrected_error && recoverable) 3030 ? " recoverable" : "", 3031 mscod, errcode, 3032 m->bank); 3033 } else { 3034 char A = *("A"); 3035 3036 /* 3037 * Reported channel is in range 0-2, so we can't map it 3038 * back to mc. To figure out mc we check machine check 3039 * bank register that reported this error. 3040 * bank15 means mc0 and bank16 means mc1. 3041 */ 3042 channel = knl_channel_remap(m->bank == 16, channel); 3043 channel_mask = 1 << channel; 3044 3045 snprintf(msg, sizeof(msg), 3046 "%s%s err_code:%04x:%04x channel:%d (DIMM_%c)", 3047 overflow ? " OVERFLOW" : "", 3048 (uncorrected_error && recoverable) 3049 ? " recoverable" : " ", 3050 mscod, errcode, channel, A + channel); 3051 edac_mc_handle_error(tp_event, mci, core_err_cnt, 3052 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, 3053 channel, 0, -1, 3054 optype, msg); 3055 } 3056 return; 3057 } else if (lsb < 12) { 3058 rc = get_memory_error_data(mci, m->addr, &socket, &ha, 3059 &channel_mask, &rank, 3060 &area_type, msg); 3061 } else { 3062 rc = get_memory_error_data_from_mce(mci, m, &socket, &ha, 3063 &channel_mask, msg); 3064 } 3065 3066 if (rc < 0) 3067 goto err_parsing; 3068 new_mci = get_mci_for_node_id(socket, ha); 3069 if (!new_mci) { 3070 strcpy(msg, "Error: socket got corrupted!"); 3071 goto err_parsing; 3072 } 3073 mci = new_mci; 3074 pvt = mci->pvt_info; 3075 3076 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS); 3077 3078 if (rank == 0xff) 3079 dimm = -1; 3080 else if (rank < 4) 3081 dimm = 0; 3082 else if (rank < 8) 3083 dimm = 1; 3084 else 3085 dimm = 2; 3086 3087 /* 3088 * FIXME: On some memory configurations (mirror, lockstep), the 3089 * Memory Controller can't point the error to a single DIMM. The 3090 * EDAC core should be handling the channel mask, in order to point 3091 * to the group of dimm's where the error may be happening. 3092 */ 3093 if (!pvt->is_lockstep && !pvt->is_cur_addr_mirrored && !pvt->is_close_pg) 3094 channel = first_channel; 3095 3096 snprintf(msg, sizeof(msg), 3097 "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d", 3098 overflow ? " OVERFLOW" : "", 3099 (uncorrected_error && recoverable) ? " recoverable" : "", 3100 area_type, 3101 mscod, errcode, 3102 socket, ha, 3103 channel_mask, 3104 rank); 3105 3106 edac_dbg(0, "%s\n", msg); 3107 3108 /* FIXME: need support for channel mask */ 3109 3110 if (channel == CHANNEL_UNSPECIFIED) 3111 channel = -1; 3112 3113 /* Call the helper to output message */ 3114 edac_mc_handle_error(tp_event, mci, core_err_cnt, 3115 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, 3116 channel, dimm, -1, 3117 optype, msg); 3118 return; 3119 err_parsing: 3120 edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0, 3121 -1, -1, -1, 3122 msg, ""); 3123 3124 } 3125 3126 /* 3127 * Check that logging is enabled and that this is the right type 3128 * of error for us to handle. 3129 */ 3130 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val, 3131 void *data) 3132 { 3133 struct mce *mce = (struct mce *)data; 3134 struct mem_ctl_info *mci; 3135 char *type; 3136 3137 if (edac_get_report_status() == EDAC_REPORTING_DISABLED) 3138 return NOTIFY_DONE; 3139 3140 /* 3141 * Just let mcelog handle it if the error is 3142 * outside the memory controller. A memory error 3143 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0. 3144 * bit 12 has an special meaning. 3145 */ 3146 if ((mce->status & 0xefff) >> 7 != 1) 3147 return NOTIFY_DONE; 3148 3149 /* Check ADDRV bit in STATUS */ 3150 if (!GET_BITFIELD(mce->status, 58, 58)) 3151 return NOTIFY_DONE; 3152 3153 /* Check MISCV bit in STATUS */ 3154 if (!GET_BITFIELD(mce->status, 59, 59)) 3155 return NOTIFY_DONE; 3156 3157 /* Check address type in MISC (physical address only) */ 3158 if (GET_BITFIELD(mce->misc, 6, 8) != 2) 3159 return NOTIFY_DONE; 3160 3161 mci = get_mci_for_node_id(mce->socketid, IMC0); 3162 if (!mci) 3163 return NOTIFY_DONE; 3164 3165 if (mce->mcgstatus & MCG_STATUS_MCIP) 3166 type = "Exception"; 3167 else 3168 type = "Event"; 3169 3170 sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n"); 3171 3172 sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx " 3173 "Bank %d: %016Lx\n", mce->extcpu, type, 3174 mce->mcgstatus, mce->bank, mce->status); 3175 sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc); 3176 sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr); 3177 sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc); 3178 3179 sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET " 3180 "%u APIC %x\n", mce->cpuvendor, mce->cpuid, 3181 mce->time, mce->socketid, mce->apicid); 3182 3183 sbridge_mce_output_error(mci, mce); 3184 3185 /* Advice mcelog that the error were handled */ 3186 return NOTIFY_STOP; 3187 } 3188 3189 static struct notifier_block sbridge_mce_dec = { 3190 .notifier_call = sbridge_mce_check_error, 3191 .priority = MCE_PRIO_EDAC, 3192 }; 3193 3194 /**************************************************************************** 3195 EDAC register/unregister logic 3196 ****************************************************************************/ 3197 3198 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev) 3199 { 3200 struct mem_ctl_info *mci = sbridge_dev->mci; 3201 3202 if (unlikely(!mci || !mci->pvt_info)) { 3203 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev); 3204 3205 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n"); 3206 return; 3207 } 3208 3209 edac_dbg(0, "MC: mci = %p, dev = %p\n", 3210 mci, &sbridge_dev->pdev[0]->dev); 3211 3212 /* Remove MC sysfs nodes */ 3213 edac_mc_del_mc(mci->pdev); 3214 3215 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); 3216 kfree(mci->ctl_name); 3217 edac_mc_free(mci); 3218 sbridge_dev->mci = NULL; 3219 } 3220 3221 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type) 3222 { 3223 struct mem_ctl_info *mci; 3224 struct edac_mc_layer layers[2]; 3225 struct sbridge_pvt *pvt; 3226 struct pci_dev *pdev = sbridge_dev->pdev[0]; 3227 int rc; 3228 3229 /* allocate a new MC control structure */ 3230 layers[0].type = EDAC_MC_LAYER_CHANNEL; 3231 layers[0].size = type == KNIGHTS_LANDING ? 3232 KNL_MAX_CHANNELS : NUM_CHANNELS; 3233 layers[0].is_virt_csrow = false; 3234 layers[1].type = EDAC_MC_LAYER_SLOT; 3235 layers[1].size = type == KNIGHTS_LANDING ? 1 : MAX_DIMMS; 3236 layers[1].is_virt_csrow = true; 3237 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers, 3238 sizeof(*pvt)); 3239 3240 if (unlikely(!mci)) 3241 return -ENOMEM; 3242 3243 edac_dbg(0, "MC: mci = %p, dev = %p\n", 3244 mci, &pdev->dev); 3245 3246 pvt = mci->pvt_info; 3247 memset(pvt, 0, sizeof(*pvt)); 3248 3249 /* Associate sbridge_dev and mci for future usage */ 3250 pvt->sbridge_dev = sbridge_dev; 3251 sbridge_dev->mci = mci; 3252 3253 mci->mtype_cap = type == KNIGHTS_LANDING ? 3254 MEM_FLAG_DDR4 : MEM_FLAG_DDR3; 3255 mci->edac_ctl_cap = EDAC_FLAG_NONE; 3256 mci->edac_cap = EDAC_FLAG_NONE; 3257 mci->mod_name = EDAC_MOD_STR; 3258 mci->dev_name = pci_name(pdev); 3259 mci->ctl_page_to_phys = NULL; 3260 3261 pvt->info.type = type; 3262 switch (type) { 3263 case IVY_BRIDGE: 3264 pvt->info.rankcfgr = IB_RANK_CFG_A; 3265 pvt->info.get_tolm = ibridge_get_tolm; 3266 pvt->info.get_tohm = ibridge_get_tohm; 3267 pvt->info.dram_rule = ibridge_dram_rule; 3268 pvt->info.get_memory_type = get_memory_type; 3269 pvt->info.get_node_id = get_node_id; 3270 pvt->info.get_ha = ibridge_get_ha; 3271 pvt->info.rir_limit = rir_limit; 3272 pvt->info.sad_limit = sad_limit; 3273 pvt->info.interleave_mode = interleave_mode; 3274 pvt->info.dram_attr = dram_attr; 3275 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); 3276 pvt->info.interleave_list = ibridge_interleave_list; 3277 pvt->info.interleave_pkg = ibridge_interleave_pkg; 3278 pvt->info.get_width = ibridge_get_width; 3279 3280 /* Store pci devices at mci for faster access */ 3281 rc = ibridge_mci_bind_devs(mci, sbridge_dev); 3282 if (unlikely(rc < 0)) 3283 goto fail0; 3284 get_source_id(mci); 3285 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge SrcID#%d_Ha#%d", 3286 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); 3287 break; 3288 case SANDY_BRIDGE: 3289 pvt->info.rankcfgr = SB_RANK_CFG_A; 3290 pvt->info.get_tolm = sbridge_get_tolm; 3291 pvt->info.get_tohm = sbridge_get_tohm; 3292 pvt->info.dram_rule = sbridge_dram_rule; 3293 pvt->info.get_memory_type = get_memory_type; 3294 pvt->info.get_node_id = get_node_id; 3295 pvt->info.get_ha = sbridge_get_ha; 3296 pvt->info.rir_limit = rir_limit; 3297 pvt->info.sad_limit = sad_limit; 3298 pvt->info.interleave_mode = interleave_mode; 3299 pvt->info.dram_attr = dram_attr; 3300 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule); 3301 pvt->info.interleave_list = sbridge_interleave_list; 3302 pvt->info.interleave_pkg = sbridge_interleave_pkg; 3303 pvt->info.get_width = sbridge_get_width; 3304 3305 /* Store pci devices at mci for faster access */ 3306 rc = sbridge_mci_bind_devs(mci, sbridge_dev); 3307 if (unlikely(rc < 0)) 3308 goto fail0; 3309 get_source_id(mci); 3310 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge SrcID#%d_Ha#%d", 3311 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); 3312 break; 3313 case HASWELL: 3314 /* rankcfgr isn't used */ 3315 pvt->info.get_tolm = haswell_get_tolm; 3316 pvt->info.get_tohm = haswell_get_tohm; 3317 pvt->info.dram_rule = ibridge_dram_rule; 3318 pvt->info.get_memory_type = haswell_get_memory_type; 3319 pvt->info.get_node_id = haswell_get_node_id; 3320 pvt->info.get_ha = ibridge_get_ha; 3321 pvt->info.rir_limit = haswell_rir_limit; 3322 pvt->info.sad_limit = sad_limit; 3323 pvt->info.interleave_mode = interleave_mode; 3324 pvt->info.dram_attr = dram_attr; 3325 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); 3326 pvt->info.interleave_list = ibridge_interleave_list; 3327 pvt->info.interleave_pkg = ibridge_interleave_pkg; 3328 pvt->info.get_width = ibridge_get_width; 3329 3330 /* Store pci devices at mci for faster access */ 3331 rc = haswell_mci_bind_devs(mci, sbridge_dev); 3332 if (unlikely(rc < 0)) 3333 goto fail0; 3334 get_source_id(mci); 3335 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell SrcID#%d_Ha#%d", 3336 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); 3337 break; 3338 case BROADWELL: 3339 /* rankcfgr isn't used */ 3340 pvt->info.get_tolm = haswell_get_tolm; 3341 pvt->info.get_tohm = haswell_get_tohm; 3342 pvt->info.dram_rule = ibridge_dram_rule; 3343 pvt->info.get_memory_type = haswell_get_memory_type; 3344 pvt->info.get_node_id = haswell_get_node_id; 3345 pvt->info.get_ha = ibridge_get_ha; 3346 pvt->info.rir_limit = haswell_rir_limit; 3347 pvt->info.sad_limit = sad_limit; 3348 pvt->info.interleave_mode = interleave_mode; 3349 pvt->info.dram_attr = dram_attr; 3350 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); 3351 pvt->info.interleave_list = ibridge_interleave_list; 3352 pvt->info.interleave_pkg = ibridge_interleave_pkg; 3353 pvt->info.get_width = broadwell_get_width; 3354 3355 /* Store pci devices at mci for faster access */ 3356 rc = broadwell_mci_bind_devs(mci, sbridge_dev); 3357 if (unlikely(rc < 0)) 3358 goto fail0; 3359 get_source_id(mci); 3360 mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell SrcID#%d_Ha#%d", 3361 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); 3362 break; 3363 case KNIGHTS_LANDING: 3364 /* pvt->info.rankcfgr == ??? */ 3365 pvt->info.get_tolm = knl_get_tolm; 3366 pvt->info.get_tohm = knl_get_tohm; 3367 pvt->info.dram_rule = knl_dram_rule; 3368 pvt->info.get_memory_type = knl_get_memory_type; 3369 pvt->info.get_node_id = knl_get_node_id; 3370 pvt->info.get_ha = knl_get_ha; 3371 pvt->info.rir_limit = NULL; 3372 pvt->info.sad_limit = knl_sad_limit; 3373 pvt->info.interleave_mode = knl_interleave_mode; 3374 pvt->info.dram_attr = dram_attr_knl; 3375 pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule); 3376 pvt->info.interleave_list = knl_interleave_list; 3377 pvt->info.interleave_pkg = ibridge_interleave_pkg; 3378 pvt->info.get_width = knl_get_width; 3379 3380 rc = knl_mci_bind_devs(mci, sbridge_dev); 3381 if (unlikely(rc < 0)) 3382 goto fail0; 3383 get_source_id(mci); 3384 mci->ctl_name = kasprintf(GFP_KERNEL, "Knights Landing SrcID#%d_Ha#%d", 3385 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); 3386 break; 3387 } 3388 3389 if (!mci->ctl_name) { 3390 rc = -ENOMEM; 3391 goto fail0; 3392 } 3393 3394 /* Get dimm basic config and the memory layout */ 3395 rc = get_dimm_config(mci); 3396 if (rc < 0) { 3397 edac_dbg(0, "MC: failed to get_dimm_config()\n"); 3398 goto fail; 3399 } 3400 get_memory_layout(mci); 3401 3402 /* record ptr to the generic device */ 3403 mci->pdev = &pdev->dev; 3404 3405 /* add this new MC control structure to EDAC's list of MCs */ 3406 if (unlikely(edac_mc_add_mc(mci))) { 3407 edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); 3408 rc = -EINVAL; 3409 goto fail; 3410 } 3411 3412 return 0; 3413 3414 fail: 3415 kfree(mci->ctl_name); 3416 fail0: 3417 edac_mc_free(mci); 3418 sbridge_dev->mci = NULL; 3419 return rc; 3420 } 3421 3422 static const struct x86_cpu_id sbridge_cpuids[] = { 3423 X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X, &pci_dev_descr_sbridge_table), 3424 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &pci_dev_descr_ibridge_table), 3425 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &pci_dev_descr_haswell_table), 3426 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &pci_dev_descr_broadwell_table), 3427 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &pci_dev_descr_broadwell_table), 3428 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &pci_dev_descr_knl_table), 3429 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &pci_dev_descr_knl_table), 3430 { } 3431 }; 3432 MODULE_DEVICE_TABLE(x86cpu, sbridge_cpuids); 3433 3434 /* 3435 * sbridge_probe Get all devices and register memory controllers 3436 * present. 3437 * return: 3438 * 0 for FOUND a device 3439 * < 0 for error code 3440 */ 3441 3442 static int sbridge_probe(const struct x86_cpu_id *id) 3443 { 3444 int rc = -ENODEV; 3445 u8 mc, num_mc = 0; 3446 struct sbridge_dev *sbridge_dev; 3447 struct pci_id_table *ptable = (struct pci_id_table *)id->driver_data; 3448 3449 /* get the pci devices we want to reserve for our use */ 3450 rc = sbridge_get_all_devices(&num_mc, ptable); 3451 3452 if (unlikely(rc < 0)) { 3453 edac_dbg(0, "couldn't get all devices\n"); 3454 goto fail0; 3455 } 3456 3457 mc = 0; 3458 3459 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { 3460 edac_dbg(0, "Registering MC#%d (%d of %d)\n", 3461 mc, mc + 1, num_mc); 3462 3463 sbridge_dev->mc = mc++; 3464 rc = sbridge_register_mci(sbridge_dev, ptable->type); 3465 if (unlikely(rc < 0)) 3466 goto fail1; 3467 } 3468 3469 sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION); 3470 3471 return 0; 3472 3473 fail1: 3474 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) 3475 sbridge_unregister_mci(sbridge_dev); 3476 3477 sbridge_put_all_devices(); 3478 fail0: 3479 return rc; 3480 } 3481 3482 /* 3483 * sbridge_remove cleanup 3484 * 3485 */ 3486 static void sbridge_remove(void) 3487 { 3488 struct sbridge_dev *sbridge_dev; 3489 3490 edac_dbg(0, "\n"); 3491 3492 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) 3493 sbridge_unregister_mci(sbridge_dev); 3494 3495 /* Release PCI resources */ 3496 sbridge_put_all_devices(); 3497 } 3498 3499 /* 3500 * sbridge_init Module entry function 3501 * Try to initialize this module for its devices 3502 */ 3503 static int __init sbridge_init(void) 3504 { 3505 const struct x86_cpu_id *id; 3506 const char *owner; 3507 int rc; 3508 3509 edac_dbg(2, "\n"); 3510 3511 owner = edac_get_owner(); 3512 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR))) 3513 return -EBUSY; 3514 3515 id = x86_match_cpu(sbridge_cpuids); 3516 if (!id) 3517 return -ENODEV; 3518 3519 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 3520 opstate_init(); 3521 3522 rc = sbridge_probe(id); 3523 3524 if (rc >= 0) { 3525 mce_register_decode_chain(&sbridge_mce_dec); 3526 if (edac_get_report_status() == EDAC_REPORTING_DISABLED) 3527 sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n"); 3528 return 0; 3529 } 3530 3531 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n", 3532 rc); 3533 3534 return rc; 3535 } 3536 3537 /* 3538 * sbridge_exit() Module exit function 3539 * Unregister the driver 3540 */ 3541 static void __exit sbridge_exit(void) 3542 { 3543 edac_dbg(2, "\n"); 3544 sbridge_remove(); 3545 mce_unregister_decode_chain(&sbridge_mce_dec); 3546 } 3547 3548 module_init(sbridge_init); 3549 module_exit(sbridge_exit); 3550 3551 module_param(edac_op_state, int, 0444); 3552 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 3553 3554 MODULE_LICENSE("GPL"); 3555 MODULE_AUTHOR("Mauro Carvalho Chehab"); 3556 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); 3557 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - " 3558 SBRIDGE_REVISION); 3559